Div fixes

Summary: More widening and fix division which depends upon sign.

Reviewed By: alexmalyshev

Differential Revision: D93906168

fbshipit-source-id: f54461455b5f5c52e25b43064f83204f35e22ff8

Author: DinoV

cinderx/Jit/codegen/autogen.cpp

@@ -2140,6 +2140,12 @@ void translateMove(Environ* env, const Instruction* instr) {
             as->mov(a64::w(scratch1.id()), input->getConstant());
             as->strh(a64::w(scratch1.id()), ptr);
             break;
+          case OperandBase::k32bit:
+            // Use w register for 4-byte store to avoid overflowing
+            // tightly-packed fields.
+            as->mov(a64::w(scratch1.id()), input->getConstant());
+            as->str(a64::w(scratch1.id()), ptr);
+            break;
           default:
             as->mov(scratch1, input->getConstant());
             as->str(scratch1, ptr);
@@ -2254,7 +2260,7 @@ void translateMovSXD(Environ* env, const Instruction* instr) {
   const OperandBase* input = instr->getInput(0);
 
   if (input->isReg()) {
-    auto input_reg = AT::getGp(input);
+    auto input_reg = asmjit::a64::w(input->getPhyRegister().loc);
     as->sxtw(output, input_reg);
   } else if (input->isStack()) {
     auto loc = input->getStackSlot().loc;
@@ -2418,20 +2424,32 @@ void translateDivOp(
 
   const OperandBase* output =
       instr->getNumOutputs() > 0 ? instr->output() : instr->getInput(0);
-  const OperandBase* opnd0 = instr->getInput(0);
-  const OperandBase* opnd1 = instr->getInput(1);
+
+  // Division instructions may have an extra leading Imm{0} input (used by x86
+  // for the high half of the dividend). Skip it on AArch64.
+  size_t base = 0;
+  if (instr->getNumInputs() == 3 && instr->getInput(0)->isImm()) {
+    base = 1;
+  }
+  const OperandBase* opnd0 = instr->getInput(base);
+  const OperandBase* opnd1 = instr->getInput(base + 1);
 
   JIT_CHECK(output->isReg(), "Expected output to be a register");
   JIT_CHECK(opnd0->isReg(), "Expected opnd0 to be a register");
 
-  auto output_reg = AT::getGpWiden(output);
-  auto opnd0_reg = AT::getGpWiden(opnd0);
+  // Use getGpOutput to get the correct register width. sdiv/udiv require all
+  // operands to be the same width. getGpOutput returns w(reg) for k32bit and
+  // x(reg) for k64bit, matching the hardware instruction requirements.
+  // (getGpWiden would return x(reg) for k32bit, causing sdiv to interpret
+  // zero-extended 32-bit values as 64-bit, giving wrong results for negatives.)
+  auto output_reg = AT::getGpOutput(output);
+  auto opnd0_reg = AT::getGpOutput(opnd0);
 
   if (opnd1->isReg()) {
-    emit(as, output_reg, opnd0_reg, AT::getGpWiden(opnd1));
+    emit(as, output_reg, opnd0_reg, AT::getGpOutput(opnd1));
   } else if (opnd1->isStack()) {
     auto loc = opnd1->getStackSlot().loc;
-    auto scratch = AT::getGpWiden(output->dataType(), arch::reg_scratch_0.id());
+    auto scratch = AT::getGpOutput(output, arch::reg_scratch_0.id());
     auto ptr = arch::ptr_resolve(as, arch::fp, loc, arch::reg_scratch_0);
     as->ldr(scratch, ptr);
     emit(as, output_reg, opnd0_reg, scratch);
@@ -2790,13 +2808,17 @@ BEGIN_RULES(Instruction::kDiv)
   GEN("rrm", CALL_C(translateDiv))
   GEN("rr", CALL_C(translateDiv))
   GEN("rm", CALL_C(translateDiv))
+  GEN("Rirr", CALL_C(translateDiv))
+  GEN("Rirm", CALL_C(translateDiv))
 END_RULES
 
 BEGIN_RULES(Instruction::kDivUn)
   GEN("rrr", CALL_C(translateDivUn))
   GEN("rrm", CALL_C(translateDivUn))
   GEN("rr", CALL_C(translateDivUn))
   GEN("rm", CALL_C(translateDivUn))
+  GEN("Rirr", CALL_C(translateDivUn))
+  GEN("Rirm", CALL_C(translateDivUn))
 END_RULES
 
 BEGIN_RULES(Instruction::kFadd)

cinderx/Jit/lir/postgen.cpp

@@ -28,23 +28,29 @@ RewriteResult rewriteBinaryOpConstantPosition(instr_iter_t instr_iter) {
   auto block = instr->basicblock();
 
   if (instr->isDiv() || instr->isDivUn()) {
-    auto divisor = instr->getInput(2);
-    if (!divisor->isImm()) {
-      return kUnchanged;
-    }
-
-    // div doesn't support an immediate as the divisor.
-    auto constant = divisor->getConstant();
-    auto constant_size = divisor->dataType();
+    bool changed = false;
+    // div/sdiv/udiv don't support immediate operands on AArch64.
+    // Input layout is [Imm{0}, dividend, divisor] where input 0 is the x86
+    // high-half placeholder. Convert both dividend (input 1) and divisor
+    // (input 2) to registers if they are immediates.
+    for (int idx = 1; idx <= 2; idx++) {
+      auto operand = instr->getInput(idx);
+      if (!operand->isImm()) {
+        continue;
+      }
+      auto constant = operand->getConstant();
+      auto constant_size = operand->dataType();
 
-    auto move = block->allocateInstrBefore(
-        instr_iter,
-        Instruction::kMove,
-        OutVReg{constant_size},
-        Imm{constant, constant_size});
+      auto move = block->allocateInstrBefore(
+          instr_iter,
+          Instruction::kMove,
+          OutVReg{constant_size},
+          Imm{constant, constant_size});
 
-    instr->setInput(2, std::make_unique<LinkedOperand>(move));
-    return kChanged;
+      instr->setInput(idx, std::make_unique<LinkedOperand>(move));
+      changed = true;
+    }
+    return changed ? kChanged : kUnchanged;
   }
 
   if (!instr->isAdd() && !instr->isSub() && !instr->isXor() &&