Add a LoadPair LIR instruction

Summary:
Take 2 of D114969843. This gets the same treatment as D116050156 so we use an address adjustment + load pair instead of two ldr's.

Adds `kLoadPair`, the load-side counterpart to the existing `kStorePair`, so
adjacent 64-bit loads can be emitted as a single `ldp`. It takes the same
(offset, base) shape as `kStorePair`, with the first destination as the output
and the second as an extra input. On x86 it lowers to two `mov`s.

The first user is `PopulateEntryBlock`, which loads the vectorcall arguments
from consecutive slots of the argument array on every JIT function entry:

```
mov x10, x1              mov x10, x1
ldr x1, [x10]            ldp x1, x2, [x10]
ldr x2, [x10, #8]    ->  ldp x3, x4, [x10, #0x10]
ldr x3, [x10, #0x10]     ldp x5, x6, [x10, #0x20]
ldr x4, [x10, #0x18]
ldr x5, [x10, #0x20]
ldr x6, [x10, #0x28]
```

One important caveat about this - we have no support for instructions w/ multiple outputs. So this instruction is only available after register allocation where we've previously allocated the output register as part of a load instruction. The current usage runs after register allocation and the next diff adds a post-alloc pass as well.

Pairing is limited to aarch64 so x86 output is unchanged.

Reviewed By: yoney, alexmalyshev

Differential Revision: D116050157

fbshipit-source-id: d6102c84812d46a0fc5495b0b6a7064fcc4a24a8

Author: DinoV

cinderx/Jit/codegen/autogen.cpp

@@ -1552,6 +1552,37 @@ void translateStorePair(Environ* env, const Instruction* instr) {
 #endif
 }
 
+void translateLoadPair(Environ* env, const Instruction* instr) {
+  arch::Builder* as = env->as;
+  JIT_DCHECK(
+      instr->getNumInputs() == 3,
+      "LoadPair expects exactly 3 inputs (offset, base, dst1)");
+  int32_t offset = static_cast<int32_t>(instr->getInput(0)->getConstant());
+  auto base_reg = instr->getInput(1)->getPhyRegister();
+  auto dst0_loc = instr->output()->getPhyRegister();
+  auto dst1_loc = instr->getInput(2)->getPhyRegister();
+
+#if defined(CINDER_X86_64)
+  auto base = x86::gpq(base_reg.loc);
+  as->mov(x86::gpq(dst0_loc.loc), x86::qword_ptr(base, offset));
+  as->mov(x86::gpq(dst1_loc.loc), x86::qword_ptr(base, offset + kPointerSize));
+#elif defined(CINDER_AARCH64)
+  auto dst0 = a64::x(dst0_loc.loc);
+  auto dst1 = a64::x(dst1_loc.loc);
+
+  if (auto ptr = getPairPtr(env, base_reg, offset)) {
+    as->ldp(dst0, dst1, *ptr);
+  } else {
+    as->ldp(
+        dst0,
+        dst1,
+        getPairScratchPtr(env, base_reg, offset, dst0_loc, dst1_loc));
+  }
+#else
+  CINDER_UNSUPPORTED
+#endif
+}
+
 // Tear down the frame. On x86, this executes 'leave' (mov rsp, rbp; pop rbp).
 // On aarch64, this restores sp from fp and pops the frame record (fp + lr).
 //
@@ -3285,6 +3316,9 @@ void AutoTranslator::translateInstr(Environ* env, const Instruction* instr)
     case Opcode::kStorePair:
       translateStorePair(env, instr);
       return;
+    case Opcode::kLoadPair:
+      translateLoadPair(env, instr);
+      return;
     case Opcode::kLeave:
       translateLeave(env);
       return;
@@ -3557,6 +3591,9 @@ void AutoTranslator::translateInstr(Environ* env, const Instruction* instr)
     case Opcode::kStorePair:
       translateStorePair(env, instr);
       return;
+    case Opcode::kLoadPair:
+      translateLoadPair(env, instr);
+      return;
     case Opcode::kLeave:
       translateLeave(env);
       return;

cinderx/Jit/lir/generator.cpp

@@ -573,28 +573,79 @@ void PopulateEntryBlock(
   auto kPointerSize = static_cast<int32_t>(sizeof(void*));
 
   bool has_extra_args = false;
+
+  // Consecutive general-purpose arguments live in adjacent slots, so they can
+  // be loaded a pair at a time. This block is built after the post-allocation
+  // pairing pass has run, so the pairs are formed here instead. A double
+  // argument, a gap left by an overflow argument, or a destination that would
+  // clobber the array pointer ends the run.
+#if defined(CINDER_AARCH64)
+  constexpr bool kCanPairArgLoads = true;
+#else
+  constexpr bool kCanPairArgLoads = false;
+#endif
+
+  std::optional<std::pair<int32_t, PhyLocation>> pending;
+  auto flushPending = [&]() {
+    if (!pending.has_value()) {
+      return;
+    }
+    entry_block->allocateInstr(
+        Opcode::kMove,
+        nullptr,
+        OutPhyReg(pending->second),
+        Ind(args_reg, pending->first));
+    pending.reset();
+  };
+
   for (size_t i = 0; i < arg_locations.size(); i++) {
     PhyLocation arg = arg_locations[i];
     if (arg == PhyLocation::REG_INVALID) {
       has_extra_args = true;
+      flushPending();
       continue;
     }
-    if (arg.isGpRegister()) {
+
+    auto offset = static_cast<int32_t>(i * kPointerSize);
+
+    if (!arg.isGpRegister()) {
+      flushPending();
       entry_block->allocateInstr(
           Opcode::kMove,
           nullptr,
-          OutPhyReg(arg),
-          Ind(args_reg, static_cast<int32_t>(i * kPointerSize)));
-    } else {
+          OutPhyReg(arg, Operand::kDouble),
+          Ind(args_reg, offset, Operand::kDouble));
+      continue;
+    }
+
+    // defense in depth: we don't know this will use hardware load pair so
+    // don't generate load pair if the registers overlap.
+    if (arg == args_reg) {
+      flushPending();
       entry_block->allocateInstr(
-          Opcode::kMove,
+          Opcode::kMove, nullptr, OutPhyReg(arg), Ind(args_reg, offset));
+      continue;
+    }
+
+    if (kCanPairArgLoads && pending.has_value() && pending->second != arg) {
+      JIT_DCHECK(
+          offset == pending->first + kPointerSize,
+          "pending arg load should be for the preceding slot");
+      entry_block->allocateInstr(
+          Opcode::kLoadPair,
           nullptr,
-          OutPhyReg(arg, Operand::kDouble),
-          Ind(args_reg,
-              static_cast<int32_t>(i * kPointerSize),
-              Operand::kDouble));
+          OutPhyReg(pending->second),
+          Imm{static_cast<uint64_t>(pending->first)},
+          PhyReg{args_reg},
+          PhyReg{arg});
+      pending.reset();
+      continue;
     }
+
+    flushPending();
+    pending = std::make_pair(offset, arg);
   }
+  flushPending();
   if (has_extra_args) {
     // Point extra_args register past the register-bound args to the
     // start of the overflow args in the vectorcall array.

cinderx/Jit/lir/linear_scan.cpp

@@ -469,6 +469,9 @@ void LinearScanAllocator::calculateLiveIntervals() {
         continue;
       }
 
+      JIT_DCHECK(
+          instr_opcode != Opcode::kLoadPair,
+          "load pair can only be generated after register allocation");
       // output
       auto output_opnd = instr->output();
       if (output_opnd->isVreg()) {

cinderx/Jit/lir/spill_alloc.cpp

@@ -172,6 +172,10 @@ void SpillAllocator::rewriteInstr(BasicBlock* block, instr_iter_t iter) {
     return;
   }
 
+  JIT_DCHECK(
+      !instr->isLoadPair(),
+      "load pair can only be generated after register allocation");
+
   // Generator frame migration: a Move into the frame-pointer register swaps the
   // frame pointer between the machine stack and the heap-allocated generator
   // data.  Handle values that must cross the switch, then fall through so the