Commit 817cfca
Derive per NUMA node DRAM latency on AMD (#598)
Summary:
The amd_l3 sampled-latency counters are per CCX, and the Dram_Near data source
already means "this CCX's own NUMA node". The shared uncore path sums every
CCX instance into a single host sample before any average is taken, so the node
breakdown is lost and only a host-wide latency is available.
Read the `L3DramLat` group a second time through the new keyed API, which
preserves the device key. The key carries the servicing CPU, and a CCX belongs
to exactly one NUMA node, so the values can be bucketed per node and published
as `L3DramLat::node<N>` metric frames alongside the untouched host frame.
`calcAvgL3ToNearDramLatNanoSecForNode()` then reads a node's frame with the
existing latency math.
Notes:
- The per node average sums the accumulators and the request counts separately
before dividing, so busier CCXs weigh proportionally. Averaging the per-CCX
ratios would be wrong.
- The node topology comes from sysfs once at configure time; it is fixed for
the lifetime of the boot. A memory-only node (CXL) has no CPUs and so never
becomes an empty bucket.
- The host path, its metric names, and the perf event count are unchanged, so
the shipped `l3_to_*_dram_lat_avg_ns` keys are unaffected.
- `saveArchSpecificMetricFrames()` is a no-op hook on the base, so Intel and
ARM are unaffected.
Differential Revision: D1168372191 parent aa9fdbe commit 817cfca
1 file changed
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