Update ARM neoverse v2 event for counting last level cache misses (#466)

Summary:
Pull Request resolved: #466

Dynolog was using an incorrect ARM Neoverse V2 eventId to measure the system level L3 cache miss.
We will now start using ll_cache_miss_rd (last-level cache miss for a read transaction) instead of l3d_cache_refill eventId.

Reviewed By: Alston-Tang

Differential Revision: D85590511

fbshipit-source-id: e3104b7c5eeae017e655ec288fdc753eb60a9e23

Author: abhiShedge

hbt/src/perf_event/BuiltinMetrics.cpp

@@ -1766,6 +1766,23 @@ void addArmCoreMetrics(std::shared_ptr<Metrics>& metrics) {
           100'000'000,
           System::Permissions{},
           std::vector<std::string>{}));
+
+  metrics->add(
+      std::make_shared<MetricDesc>(
+          "HW_CORE_LL_CACHE_MISS_RD",
+          "Last level cache miss read",
+          "Counts the number of read transactions that a processor core requests from memory but are not found in the Last-Level cache (L3 cache).",
+          std::map<TOptCpuArch, EventRefs>{
+              {CpuArch::NEOVERSE_V2,
+               EventRefs{EventRef{
+                   "    ",
+                   PmuType::armv8_pmuv3,
+                   "ll_cache_miss_rd",
+                   EventExtraAttr{},
+                   {}}}}},
+          100'000'000,
+          System::Permissions{},
+          std::vector<std::string>{}));
 }
 
 void addIntelCoreMetrics(std::shared_ptr<Metrics>& metrics) {