Fix TLE DSL region inline extract op parent constraints

Author: sunnycase

third_party/tle/dialect/include/IR/TleOps.td

@@ -112,50 +112,50 @@ def Tle_YieldOp : Tle_Op<"yield", [Pure, Terminator, ReturnLike,
 }
 
 def Tle_ExtractAllocatedPtrOp
-    : Tle_Op<"extract_allocated_ptr", [Pure, HasParent<"DSLRegionOp">]> {
+    : Tle_Op<"extract_allocated_ptr", [Pure]> {
   let arguments = (ins Tle_ArgType:$input);
   let results = (outs LLVMPointerType:$ptr);
   let assemblyFormat = "$input attr-dict `:` type($input) `to` type($ptr)";
 }
 
 def Tle_ExtractAlignedPtrOp
-    : Tle_Op<"extract_aligned_ptr", [Pure, HasParent<"DSLRegionOp">]> {
+    : Tle_Op<"extract_aligned_ptr", [Pure]> {
   let arguments = (ins Tle_ArgType:$input);
   let results = (outs LLVMPointerType:$ptr);
   let assemblyFormat = "$input attr-dict `:` type($input) `to` type($ptr)";
 }
 
 def Tle_ExtractOffsetOp
-    : Tle_Op<"extract_offset", [Pure, HasParent<"DSLRegionOp">]> {
+    : Tle_Op<"extract_offset", [Pure]> {
   let arguments = (ins Tle_TensorType:$input);
   let results = (outs I64:$ptr);
   let assemblyFormat = "$input attr-dict `:` type($input) `to` type($ptr)";
 }
 
 def Tle_ExtractSizesOp
-    : Tle_Op<"extract_sizes", [Pure, HasParent<"DSLRegionOp">]> {
+    : Tle_Op<"extract_sizes", [Pure]> {
   let arguments = (ins Tle_TensorType:$input);
   let results = (outs Variadic<I64>:$sizes);
   let assemblyFormat = "$input attr-dict `:` type($input) `to` type($sizes)";
   let builders = [OpBuilder<(ins "size_t":$num, "Value":$input)>];
 }
 
 def Tle_ExtractStridesOp
-    : Tle_Op<"extract_strides", [Pure, HasParent<"DSLRegionOp">]> {
+    : Tle_Op<"extract_strides", [Pure]> {
   let arguments = (ins Tle_TensorType:$input);
   let results = (outs Variadic<I64>:$strides);
   let assemblyFormat = "$input attr-dict `:` type($input) `to` type($strides)";
   let builders = [OpBuilder<(ins "size_t":$num, "Value":$input)>];
 }
 
-def Tle_ExtractPtrOp : Tle_Op<"extract_ptr", [Pure, HasParent<"DSLRegionOp">]> {
+def Tle_ExtractPtrOp : Tle_Op<"extract_ptr", [Pure]> {
   let arguments = (ins TT_Ptr:$input);
   let results = (outs LLVMPointerType:$ptr);
   let assemblyFormat = "$input attr-dict `:` type($input) `to` type($ptr)";
 }
 
 def Tle_PackOp
-    : Tle_Op<"pack", [MemDescViewTrait, Pure, HasParent<"DSLRegionOp">]> {
+    : Tle_Op<"pack", [MemDescViewTrait, Pure]> {
   let arguments = (ins LLVMStructType:$input);
   let results = (outs Tle_TensorType:$output);
   let assemblyFormat = "$input attr-dict `:` type($input) `to` type($output)";

third_party/tle/dialect/lib/Conversion/TleToLLVM/PackOpToLLVM.cpp

@@ -28,7 +28,6 @@ PackOpConversion::PackOpConversion(LLVMTypeConverter &typeConverter,
 LogicalResult
 PackOpConversion::matchAndRewrite(tle::PackOp op, OpAdaptor adaptor,
                                   ConversionPatternRewriter &rewriter) const {
-  auto regionOp = op->getParentOfType<tle::DSLRegionOp>();
   if (ttg::MemDescType memdesc =
           dyn_cast<ttg::MemDescType>(op.getOutput().getType())) {
     LLVM::LLVMStructType llvmStructType =

third_party/tle/test/GPU/test_tle_dslregion_inline_extract_ptr.mlir

@@ -0,0 +1,20 @@
+// RUN: triton-opt %s --tle-dslregion-inline | FileCheck %s
+
+module {
+  llvm.func @_sink(!llvm.ptr)
+
+  tt.func @k(%arg0: !tt.ptr<i32>) {
+    %0 = "tle.dsl_region"(%arg0) ({
+    ^bb0(%in: !tt.ptr<i32>):
+      %p = "tle.extract_ptr"(%in) : (!tt.ptr<i32>) -> !llvm.ptr
+      "tle.yield"(%p) : (!llvm.ptr) -> ()
+    }) : (!tt.ptr<i32>) -> (!llvm.ptr)
+    llvm.call @_sink(%0) : (!llvm.ptr) -> ()
+    tt.return
+  }
+}
+
+// CHECK-LABEL: tt.func @k(
+// CHECK-NOT: tle.dsl_region
+// CHECK: %[[P:.*]] = tle.extract_ptr
+// CHECK: llvm.call @_sink(%[[P]]) : (!llvm.ptr) -> ()