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exur00exur00
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arcv: RPX-100 add mul-mem bypasses
1 parent 9c40215 commit 6643349

2 files changed

Lines changed: 90 additions & 3 deletions

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‎gcc/config/riscv/arcv-rpx100.md‎

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,7 @@
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condmove,mvpair,zicond,cpop,clmul"))
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"((arcv_rpx100_issueA_fuse0 + arcv_rpx100_ALU_A_fuse0_early) | (arcv_rpx100_issueA_fuse1 + arcv_rpx100_ALU_A_fuse1_early)) | ((arcv_rpx100_issueB_fuse0 + arcv_rpx100_ALU_B_fuse0_early) | (arcv_rpx100_issueB_fuse1 + arcv_rpx100_ALU_B_fuse1_early))")
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45-
(define_insn_reservation "arcv_rpx100_imul_fused" 4
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(define_insn_reservation "arcv_rpx100_mpy32_fused" 4
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(and (eq_attr "tune" "arcv_rpx100")
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(eq_attr "type" "imul_fused"))
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"(arcv_rpx100_issueA_fuse0 + arcv_rpx100_issueA_fuse1 + arcv_rpx100_ALU_A_fuse0_early + arcv_rpx100_ALU_A_fuse1_early + arcv_rpx100_MPY), nothing*3")
@@ -127,5 +127,12 @@
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(define_bypass 2 "arcv_rpx100_load_insn" "arcv_rpx100_load_insn")
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(define_bypass 1 "arcv_rpx100_load_insn" "arcv_rpx100_div_insn")
129129

130-
(define_bypass 3 "arcv_rpx100_mpy32_insn" "arcv_rpx100_mpy*_insn")
131-
(define_bypass 3 "arcv_rpx100_mpy32_insn" "arcv_rpx100_div_insn")
130+
(define_bypass 3 "arcv_rpx100_mpy32*_insn" "arcv_rpx100_mpy*_insn")
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(define_bypass 3 "arcv_rpx100_mpy32*_insn" "arcv_rpx100_div_insn")
132+
(define_bypass 1 "arcv_rpx100_mpy*_insn" "arcv_rpx100_store_insn" "riscv_store_data_bypass_p")
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(define_bypass 7 "arcv_rpx100_mpy32*_insn" "arcv_rpx100_load_insn")
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(define_bypass 7 "arcv_rpx100_mpy32*_insn" "arcv_rpx100_store_insn")
135+
(define_bypass 9 "arcv_rpx100_mpy64l_insn" "arcv_rpx100_load_insn")
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(define_bypass 9 "arcv_rpx100_mpy64l_insn" "arcv_rpx100_store_insn")
137+
(define_bypass 10 "arcv_rpx100_mpy64h_insn" "arcv_rpx100_load_insn")
138+
(define_bypass 10 "arcv_rpx100_mpy64h_insn" "arcv_rpx100_store_insn")

‎gcc/testsuite/gcc.target/riscv/arcv-sched-mul-mem-rpx100.c‎

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
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/* { dg-do compile } */
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/* { dg-require-effective-target rv64 } */
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/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Oz" "-Os" "-Og" } } */
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/* { dg-options "-mtune=arc-v-rpx-100-series -march=rv64imd -mabi=lp64d -fdump-rtl-sched2 -Wno-int-to-pointer-cast" } */
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void
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foo (int *a)
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{
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a[2] = a[1] * a[0];
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}
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void foo_high(long *b) {
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b[2] = ((__int128)b[1] * (__int128)b[0]) >> 64;
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}
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void foo_low(long *b) {
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b[2] = b[1] * b[0];
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}
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void
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bar (int *a)
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{
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int *addr = (int *) (a[1] * a[2]);
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*addr = 0;
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}
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void
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bar_low (long *a)
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{
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long *addr = (long *) (a[1] * a[2]);
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*addr = 0;
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}
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void
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bar_high (long *a)
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{
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long *addr = (long *) (((__int128) a[1] * (__int128) a[2]) >> 64);
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*addr = 0;
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}
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int
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baz (int *a)
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{
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int *addr = (int *) (a[1] * a[2]);
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return *addr;
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}
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long
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baz_low (long *a)
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{
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long *addr = (long *) (a[1] * a[2]);
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return *addr;
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}
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long baz_high(long *a) {
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long *addr = (long *)(((__int128) a[1] * (__int128) a[2]) >> 64);
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return *addr;
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}
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/* Verify MULW to STORE data delay is 1 cycle. */
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/* { dg-final { scan-rtl-dump "(?s);; Function foo.*?;;\\s+1-->.*i\\s+\\d+\\s+.*\\*.*:\\(arcv.*?;;\\s+2-->.*\\\[.*0x8\\\]=" "sched2" } } */
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/* Verify MULW to STORE address delay is 7 cycles. */
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/* { dg-final { scan-rtl-dump "(?s);; Function bar.*?;;\\s+1-->.*i\\s+\\d+\\s+.*\\*.*:\\(arcv.*?;;\\s+8-->.*\\\[.*\\\]=0" "sched2" } } */
65+
/* Verify MULW to LOAD address delay is 7 cycles. */
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/* { dg-final { scan-rtl-dump "(?s);; Function baz.*?;;\\s+1-->.*i\\s+\\d+\\s+.*\\*.*:\\(arcv.*?;;\\s+8-->.*=.*\\\[.*\\\]" "sched2" } } */
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/* Verify MUL to STORE data delay is 1 cycle. */
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/* { dg-final { scan-rtl-dump "(?s);; Function foo_low.*?;;\\s+1-->.*i\\s+\\d+\\s+.*\\*.*:\\(arcv.*?;;\\s+2-->.*\\\[.*0x10\\\]=" "sched2" } } */
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/* Verify MUL to STORE address delay is 9 cycles. */
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/* { dg-final { scan-rtl-dump "(?s);; Function bar_low.*?;;\\s+1-->.*i\\s+\\d+\\s+.*\\*.*:\\(arcv.*?;;\\s+10-->.*\\\[.*\\\]=0" "sched2" } } */
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/* Verify MUL to LOAD address delay is 9 cycles. */
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/* { dg-final { scan-rtl-dump "(?s);; Function baz_low.*?;;\\s+1-->.*i\\s+\\d+\\s+.*\\*.*:\\(arcv.*?;;\\s+10-->.*=.*\\\[.*\\\]" "sched2" } } */
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/* Verify MULH to STORE data delay is 1 cycle. */
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/* { dg-final { scan-rtl-dump "(?s);; Function foo_high.*?;;\\s+1-->.*i\\s+\\d+\\s+.*\\*.*:\\(arcv.*?;;\\s+2-->.*\\\[.*0x10\\\]=" "sched2" } } */
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/* Verify MULH to STORE address delay is 10 cycles. */
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/* { dg-final { scan-rtl-dump "(?s);; Function bar_high.*?;;\\s+1-->.*i\\s+\\d+\\s+.*\\*.*:\\(arcv.*?;;\\s+11-->.*\\\[.*\\\]=0" "sched2" } } */
79+
/* Verify MULH to LOAD address delay is 10 cycles. */
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/* { dg-final { scan-rtl-dump "(?s);; Function baz_high.*?;;\\s+1-->.*i\\s+\\d+\\s+.*\\*.*:\\(arcv.*?;;\\s+11-->.*=.*\\\[.*\\\]" "sched2" } } */

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