fix for P10019563-77915

fix to ensure the that the hs5x target produces correct code
despite lacking 64-bit load/store instructions.
I made use of the split mechanism enabled by the # keyword
which forces the compiler to make use of pairs of general
purpose registers and further make use of the define_split.
Then the split pattern takes a single 64bit memory move
and breaks it into two 32-bit moves using gen_lowpart and
gen_highpart.

Would have been possible to make use of a scratch register
by using a match_scratch. However, sometimes this can lead
to a reload failure.

Author: Alexehv77

gcc/config/arc64/arc64.cc

@@ -648,7 +648,6 @@ frame_save_reg (rtx reg, HOST_WIDE_INT offset, HOST_WIDE_INT displacement)
 }
 
 /* ARC prologue saving regs routine.   */
-
 static HOST_WIDE_INT
 arc64_save_callee_saves (void)
 {
@@ -674,6 +673,25 @@ arc64_save_callee_saves (void)
 	{
 	  save_mode = ARC64_HAS_FPUD ? DFmode : SFmode;
 	  disp = UNITS_PER_WORD;
+
+	  /* CRITICAL FIX: If the mode is 64-bit DFmode but the hardware 
+	     does not support 64-bit memory operations (!TARGET_LL64),
+	     decompose the save into two sequential 4-byte SFmode saves. */
+	  if (save_mode == DFmode && !TARGET_LL64)
+	    {
+	      /* Save the lower 4-byte sub-register piece (regno) */
+	      rtx reg_lo = gen_rtx_REG (SFmode, regno);
+	      frame_allocated += frame_save_reg (reg_lo, offset, disp);
+	      offset = 0;
+
+	      /* Save the upper 4-byte sub-register piece (regno + 1).
+		 The displacement or offset is updated implicitly by 
+		 the frame tracker inside frame_save_reg. */
+	      rtx reg_hi = gen_rtx_REG (SFmode, regno + 1);
+	      frame_allocated += frame_save_reg (reg_hi, offset, disp);
+	      
+	      continue; /* Skip the original single-register save logic */
+	    }
 	}
       else if (regno >= 1
 	       && (((regno - 1) % 2) == 0)
@@ -1680,7 +1698,8 @@ arc64_get_effective_mode_for_address_scaling (const machine_mode mode)
 {
   if (GET_MODE_SIZE (mode) == (UNITS_PER_WORD * 2))
     {
-      gcc_assert (DOUBLE_LOAD_STORE);
+      if (!TARGET_LL64)
+        gcc_assert (DOUBLE_LOAD_STORE);
       return Pmode;
     }
   return mode;
@@ -5546,9 +5565,19 @@ arc64_expand_prologue (void)
 
   frame_allocated = frame->frame_size;
 
-  frame_allocated -= arc64_save_callee_saves ();
 
   /* If something left, allocate.  */
+   if (ARC_INTERRUPT_P (cfun->machine->fn_type) && !TARGET_LL64)
+    {
+      if (frame_allocated > 0)
+        {
+          frame_stack_add ((HOST_WIDE_INT) 0 - frame_allocated);
+          frame_allocated = 0;
+        }
+    }
+
+  frame_allocated -= arc64_save_callee_saves ();
+
   if (frame_allocated > 0)
     frame_stack_add ((HOST_WIDE_INT) 0 - frame_allocated);
 
@@ -6117,7 +6146,7 @@ arc64_split_double_move_p (rtx *operands, machine_mode mode)
       return false;
     }
 
-  /* Evereything else is going for a split.  */
+  /* Everything else is going for a split.  */
   return true;
 }
 
@@ -6135,8 +6164,7 @@ arc64_split_double_move (rtx *operands, machine_mode mode)
   machine_mode mvmode = smallest_int_mode_for_size (BITS_PER_WORD).require ();
 
   /* Maximum size handled is twice UNITS_PER_WORD.  */
-  gcc_assert (iregs <= 2);
-
+    gcc_assert(iregs <= 2);
   /* This procedure works as long as the width of the fp regs is the
      same as the width of r regs.  */
   if (FLOAT_MODE_P (mode))

gcc/config/arc64/arc64.md

@@ -865,8 +865,8 @@ xorl"
 
 (define_insn "*arc64_movsi"
   [(set
-    (match_operand:SI 0 "arc64_dest_operand"      "=qh,r,    q,    r,    r,h,r,    q,Ustms,Ustor,Ucnst,RBLNKq,r, Ustk<,Ustor")
-    (match_operand:SI 1 "arc64_movl_operand"  "qhS03MV,r,U08S0,S12S0,SyPic,i,i,Uldms,    q,S06S0,    i, Ustk>,m,RBLNKq,    r"))
+    (match_operand:SI 0 "arc64_dest_operand"      "=w,r,w,qh,r,    q,    r,    r,h,r,    q,Ustms,Ustor,Ucnst,RBLNKq,r, Ustk<,Ustor")
+    (match_operand:SI 1 "arc64_movl_operand"  "r,w,w,qhS03MV,r,U08S0,S12S0,SyPic,i,i,Uldms,    q,S06S0,    i, Ustk>,m,RBLNKq,    r"))
    ]
   "register_operand (operands[0], SImode)
    || register_operand (operands[1], SImode)
@@ -875,6 +875,9 @@ xorl"
    || (CONST_INT_P (operands[1])
        && satisfies_constraint_Ucnst (operands[0]))"
    "@
+    mov\\t%0,%1
+    mov\\t%0,%1
+    mov\\t%0,%1
     mov_s\\t%0,%1
     mov\\t%0,%1
     mov_s\\t%0,%1
@@ -890,8 +893,8 @@ xorl"
     ld%U1\\t%0,%1
     push_s\\t%1
     st%U0\\t%1,%0"
-   [(set_attr "type" "move,move,move,move,add,move,move,ld,st,st,st,ld,ld,st,st")
-    (set_attr "length" "2,4,2,4,8,6,8,2,2,*,8,2,*,2,*")]
+   [(set_attr "type" "fmov,fmov,fmov,move,move,move,move,add,move,move,ld,st,st,st,ld,ld,st,st")
+    (set_attr "length" "4,4,4,2,4,2,4,8,6,8,2,2,*,8,2,*,2,*")]
 )
 
 (define_insn "*mov<mode>_cmp0"
@@ -924,27 +927,56 @@ xorl"
    [(set_attr "type" "move,move,move,move,ld,st,ld,st")
     (set_attr "length" "2,4,6,8,2,2,*,*")])
 
-;; For a fp move I use FSMOV.<cc> instruction. However, we can also
-;; use FSSGNJ.
-;; FIXME! add short instruction selection
 (define_insn "*mov<mode>_hardfp"
   [(set (match_operand:GPF_HF 0 "arc64_dest_operand" "=w,    w,Ufpms,*r,*w,*r,*r,*r,*Ustor")
 	(match_operand:GPF_HF 1 "arc64_movf_operand"  "w,Ufpms,    w,*w,*r,*r,*G,*m,    *r"))]
   "ARC64_HAS_FP_BASE
    && (register_operand (operands[0], <MODE>mode)
        || register_operand (operands[1], <MODE>mode))"
-  "@
-   f<sfxtab>mov\\t%0,%1
-   fld<sizef>%U1\\t%0,%1
-   fst<sizef>%U0\\t%1,%0
-   fmv<fmvftab>2<fmvitab>\\t%0,%1
-   fmv<fmvitab>2<fmvftab>\\t%0,%1
-   mov<mcctab>\\t%0,%1
-   mov<mcctab>\\t%0,%1
-   ld<slfp>%U1\\t%0,%1
-   st<slfp>%U0\\t%1,%0"
+  {
+    switch (which_alternative)
+      {
+      case 0: 
+	return "f<sfxtab>mov\\t%0,%1";
+      case 3: 
+	return "fmv<fmvftab>2<fmvitab>\\t%0,%1";
+      case 4: 
+	return "fmv<fmvitab>2<fmvftab>\\t%0,%1";
+      case 5:
+	return "mov<mcctab>\\t%0,%1";
+      case 6: 
+	return "mov<mcctab>\\t%0,%1";
+      case 7:
+      /* opt 7 (*r, *m) - This is the Load. 
+         It moves 64 bits from Memory into a general purpose pair (e.g. r0:r1).
+       */
+      case 8:
+      /* option 8 (*Ustor, *r) - is a Store. 
+         It moves 64 bits from a GPR pair back into Memory.
+       */
+        if (GET_MODE_SIZE (<MODE>mode) == 8 && !TARGET_LL64)
+          /*for hx5s with fp unit that supports double precision fp
+            we trigger the splitter*/
+          return "#";
+        return (which_alternative == 7) ? 
+	  "ld<slfp>%U1\\t%0,%1" : 
+          "st<slfp>%U0\\t%1,%0";
+      default: gcc_unreachable ();
+      }
+  }
   [(set_attr "type" "fmov,ld,st,move,move,move,move,ld,st")
-   (set_attr "length" "4,*,*,4,4,4,8,*,*")])
+   (set_attr "length" "4,*,*,4,4,4,8,*,*")
+   ;; disable fpu to/from Memory 64 bit on hs5x.
+   ;; This forces the compiler to use general purpose registers as a buffer
+   ;; becasue the alternatives 1 and 2 are disabled.
+   (set (attr "enabled")
+     (if_then_else
+       (and (match_test "GET_MODE_SIZE (<MODE>mode) == 8")
+            (not (match_test "TARGET_LL64"))
+            (ior (eq_attr "alternative" "1")
+                 (eq_attr "alternative" "2")))
+       (const_string "no")
+       (const_string "yes")))])
 
 ;; move 128bit
 (define_insn_and_split "*mov<mode>_insn"
@@ -968,12 +1000,114 @@ xorl"
    }
   [(set_attr "type" "move,ld,ld,st,st")
    (set_attr "length" "8,2,*,2,*")])
+
+;; the split applys for targets where there is no 64 bit ld/st
+;; e.g. -mfpu=fpud -mcpu=hs5x
+
+(define_split
+  [(set (match_operand:GPF_HF 0 "nonimmediate_operand" "")
+        (match_operand:GPF_HF 1 "general_operand" ""))]
+  "reload_completed 
+   && GET_MODE_SIZE (<MODE>mode) == 8 
+   && !TARGET_LL64"
+  [(const_int 0)]
+  {
+    rtx dest = operands[0];
+    rtx src = operands[1];
+    rtx hi_dest, hi_src, lo_dest, lo_src;
+
+    /*extract source lo/hi  */
+    if (MEM_P (src))
+      {
+        rtx addr = XEXP (src, 0);
+        if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
+          addr = XEXP (addr, 0);
+
+        rtx clean_mem = change_address (src, SImode, addr);
+        lo_src = adjust_address (clean_mem, SImode, 0);
+        hi_src = adjust_address (clean_mem, SImode, 4);
+      }
+    else if (REG_P (src))
+      {
+        /* Manually force SImode for source registers */
+        lo_src = gen_rtx_REG (SImode, REGNO (src));
+        hi_src = gen_rtx_REG (SImode, REGNO (src) + 1);
+      }
+    else
+      {
+        lo_src = operand_subword_force (src, 0, <MODE>mode);
+        hi_src = operand_subword_force (src, 1, <MODE>mode);
+      }
+
+    /*extract destination lo/hi  */
+    if (MEM_P (dest))
+      {
+        rtx addr = XEXP (dest, 0);
+        if (GET_RTX_CLASS (GET_CODE (addr)) == RTX_AUTOINC)
+          addr = XEXP (addr, 0);
+
+        rtx clean_mem = change_address (dest, SImode, addr);
+        lo_dest = adjust_address (clean_mem, SImode, 0);
+        hi_dest = adjust_address (clean_mem, SImode, 4);
+      }
+    else if (REG_P (dest))
+      {
+        /* Manually force SImode for destination registers */
+        lo_dest = gen_rtx_REG (SImode, REGNO (dest));
+        hi_dest = gen_rtx_REG (SImode, REGNO (dest) + 1);
+      }
+    else
+      {
+        lo_dest = operand_subword_force (dest, 0, <MODE>mode);
+        hi_dest = operand_subword_force (dest, 1, <MODE>mode);
+      }
+
+    /* preincr - r1 has DImode */
+    if (MEM_P (src) && GET_CODE (XEXP (src, 0)) == PRE_INC)
+      emit_insn (gen_adddi3 (XEXP (XEXP (src, 0), 0), 
+                       XEXP (XEXP (src, 0), 0), GEN_INT (8)));
+    if (MEM_P (dest) && GET_CODE (XEXP (dest, 0)) == PRE_INC)
+      emit_insn (gen_adddi3 (XEXP (XEXP (dest, 0), 0), 
+                       XEXP (XEXP (dest, 0), 0), GEN_INT (8)));
+
+    /* emit SI moves - both are now SImode */
+    if (reg_overlap_mentioned_p (lo_dest, hi_src))
+      { /*move from r0:r1 into r1:r2
+          in this case:
+          lo_src  = r0
+          hi_src  = r1
+          lo_dest = r1
+          hi_dest = r2 so we follow the following order*/
+          emit_move_insn (hi_dest, hi_src);
+          emit_move_insn (lo_dest, lo_src);
+      }
+     else
+      { /*move r1:r2 to r0:r1
+          lo_src  = r1
+          hi_src  = r2
+          lo_dest = r0
+          hi_dest = r1*/
+          emit_move_insn (lo_dest, lo_src);
+          emit_move_insn (hi_dest, hi_src);
+      }
+
+    /* emit post increments  */
+    if (MEM_P (src) && GET_CODE (XEXP (src, 0)) == POST_INC)
+      emit_insn (gen_adddi3 (XEXP (XEXP (src, 0), 0), 
+                       XEXP (XEXP (src, 0), 0), GEN_INT (8)));
+    if (MEM_P (dest) && GET_CODE (XEXP (dest, 0)) == POST_INC)
+      emit_insn (gen_adddi3 (XEXP (XEXP (dest, 0), 0), 
+                       XEXP (XEXP (dest, 0), 0), GEN_INT (8)));
+
+    DONE;
+  })
+
 ;;
 ;; Short insns: movl_s g,h; movl_s b,u8
 ;; Long insns: movl, stl, ldl
 ;;
 (define_insn "*arc64_movdi"
-   [(set (match_operand:DI 0 "arc64_dest_operand" "=qh,    q,    r,    r,r,    r,         r,    r,    r,Ucnst,    r,r,Ustk<,Ustor")
+  [(set (match_operand:DI 0 "arc64_dest_operand" "=qh,    q,    r,    r,r,    r,         r,    r,    r,Ucnst,    r,r,Ustk<,Ustor")
 	 (match_operand:DI 1 "arc64_movl_operand"  "qh,U08S0,BCLRX,BSETX,r,S12S0,S32S0SymMV,U38S0,SyPic,S32S0,Ustk>,m,    r, r"))]
    "TARGET_64BIT
     && (register_operand (operands[0], DImode)
@@ -999,6 +1133,40 @@ xorl"
     (set_attr "length" "2,2,8,8,4,4,8,8,8,8,2,*,2,*")]
 )
 
+(define_insn "*arc64_movdi"
+ [(set (match_operand:DI 0 "arc64_dest_operand" "=qh,    q,    r,    r,r,    r,         r,    r,    r,Ucnst,    r,r,Ustk<,Ustor")
+        (match_operand:DI 1 "arc64_movl_operand"  "qh,U08S0,BCLRX,BSETX,r,S12S0,S32S0SymMV,U38S0,SyPic,S32S0,Ustk>,m,    r, r"))]
+ "TARGET_64BIT
+  && (register_operand (operands[0], DImode)
+      || register_operand (operands[1], DImode)
+      || (CONST_INT_P (operands[1])
+          && satisfies_constraint_Ucnst (operands[0])))"
+ "@
+  movl_s\\t%0,%1
+  movl_s\\t%0,%1
+  bclrl\\t%0,%q1,%t1
+  bsetl\\t%0,%L1,%T1
+  movl\\t%0,%1
+  movl\\t%0,%1
+  movl\\t%0,%1
+  vpack2wl\\t%0,%L1,%H1
+  addl\\t%0,pcl,%1
+  #
+  popl_s\\t%0
+  #
+  pushl_s\\t%1
+  #"
+ [(set_attr "type" "move,move,bclr,bset,move,move,move,vpack,addl,st,ld,ld,st,st")
+  (set_attr "length" "2,2,8,8,4,4,8,8,8,8,2,*,2,*")
+  (set (attr "enabled")
+     (cond [(match_test "TARGET_LL64")
+            (const_string "yes")
+
+            (eq_attr "type" "ld,st")
+            (const_string "no")]
+           (const_string "yes")))
+])
+
 ;; Hi/Low moves for constant and symbol loading.
 
 (define_insn "*movdi_high"

gcc/testsuite/gcc.dg/torture/pr10019563-77915.c

@@ -0,0 +1,13 @@
+/* { dg-do run } */
+
+#include <stdlib.h>
+
+int test0(){
+    float a, b;
+    double c, d;    
+    a = (float)rand()/(float)(RAND_MAX);
+    b = (float)rand()/(float)(RAND_MAX);    
+    c = (double)rand()/(double)(RAND_MAX);
+    d = (double)rand()/(double)(RAND_MAX);    
+    return (int)((double)a + (double)b + c + d);
+}

gcc/testsuite/gcc.dg/torture/pr10019563-77915_n.c

@@ -0,0 +1,12 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mcpu=hs5x -mfpu=fpud" } */
+/* Standard success is return 0 */
+volatile double a = 10.0;
+volatile double b = 5.0;
+
+int main() {
+    double res = a - b;
+    if (res == 5.0)
+        return 0;
+    return 1;
+}