arcv: Fix immediate predicate for arcv_vclr.

arcv_vclr clears the lower imm[4:0] number of elements of vd.  However, the
current pattern uses imm5_operand, which only accepts values < 5 and therefore
rejects valid immediates.

The instruction encoding allows a 5-bit unsigned immediate, i.e. values in the
range 0..31.   Introduce a dedicated const_0_31_operand predicate and use it
for arcv_vclr.

Signed-off-by: Luis Silva <luiss@synopsys.com>

Author: Luis Silva

gcc/config/riscv/arcv-vector.md

@@ -265,7 +265,7 @@
 	     (reg:SI VL_REGNUM)
 	     (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
 	(unspec:V_VLSI
-	[(match_operand 3 "imm5_operand" "i,i,i,i,i,i,i,i,i,i,i,i")]
+	[(match_operand 3 "const_0_31_operand" "i,i,i,i,i,i,i,i,i,i,i,i")]
 	  UNSPEC_ARCV_VCLR)
 	(match_operand:V_VLSI 2 "vector_merge_operand"     "vu,0,vu,0,vu,0,vu,0,vu,0,vu,0")))]
   "TARGET_XARCVVDSP"

gcc/config/riscv/predicates.md

@@ -65,6 +65,10 @@
   (and (match_code "const_int")
        (match_test "IN_RANGE (INTVAL (op), 0, 10)")))
 
+(define_predicate "const_0_31_operand"
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
+
 (define_predicate "csr_operand"
   (ior (match_operand 0 "const_csr_operand")
        (match_operand 0 "register_operand")))