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Expand file tree Collapse file tree Original file line number Diff line number Diff line change 3030CS = "LA3"
3131SPIMaster ._primary_prescaler = PPRE = 0
3232SPIMaster ._secondary_prescaler = SPRE = 0
33- PWM_FERQUENCY = SPIMaster . _frequency * 2 / 3
33+ PWM_FREQUENCY = 1000
3434MICROSECONDS = 1e-6
3535RELTOL = 0.05
3636# Number of expected logic level changes.
@@ -61,7 +61,7 @@ def slave(handler: SerialHandler) -> SPISlave:
6161@pytest .fixture
6262def la (handler : SerialHandler ) -> LogicAnalyzer :
6363 pwm = PWMGenerator (handler )
64- pwm .generate (SDI [1 ], PWM_FERQUENCY , 0.5 )
64+ pwm .generate (SDI [1 ], PWM_FREQUENCY , 0.5 )
6565 return LogicAnalyzer (handler )
6666
6767
@@ -73,7 +73,7 @@ def verify_value(
7373 smp : int = 0 ,
7474):
7575 sck_ts = sck_timestamps [smp ::2 ]
76- pwm_half_period = ((1 / PWM_FERQUENCY ) * 1e6 ) / 2 # microsecond
76+ pwm_half_period = ((1 / PWM_FREQUENCY ) * 1e6 ) / 2 # microsecond
7777
7878 pattern = ""
7979 for t in sck_ts :
Original file line number Diff line number Diff line change 1616WRITE_DATA = 0x55
1717TXD2 = "LA1"
1818RXD2 = "SQ1"
19- PWM_FERQUENCY = UART . _baudrate // 2
19+ PWM_FREQUENCY = 1000
2020MICROSECONDS = 1e-6
2121RELTOL = 0.05
2222# Number of expected logic level changes.
@@ -38,7 +38,7 @@ def la(handler: SerialHandler) -> LogicAnalyzer:
3838@pytest .fixture
3939def pwm (handler : SerialHandler ) -> None :
4040 pwm = PWMGenerator (handler )
41- pwm .generate (RXD2 , PWM_FERQUENCY , 0.5 )
41+ pwm .generate (RXD2 , PWM_FREQUENCY , 0.5 )
4242
4343
4444def test_configure (la : LogicAnalyzer , uart : UART ):
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