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Merge pull request stm32duino#2626 from fpistm/stm32cubeWB_update
system(WB) update STM32WBxx HAL Drivers to v1.14.4
2 parents cd1c6b0 + b064aa2 commit cfe4962

22 files changed

+659
-523
lines changed

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+54-9
Original file line numberDiff line numberDiff line change
@@ -472,7 +472,9 @@ extern "C" {
472472
#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
473473
#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
474474
#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
475+
#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7)
475476
#define PAGESIZE FLASH_PAGE_SIZE
477+
#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 */
476478
#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
477479
#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
478480
#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
@@ -601,6 +603,15 @@ extern "C" {
601603
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
602604
#endif /* STM32G4 */
603605

606+
#if defined(STM32U5)
607+
608+
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster
609+
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster
610+
#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection
611+
#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection
612+
613+
#endif /* STM32U5 */
614+
604615
#if defined(STM32H5)
605616
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
606617
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
@@ -875,6 +886,10 @@ extern "C" {
875886
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
876887
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
877888

889+
#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7)
890+
#define HRTIMInterruptResquests HRTIMInterruptRequests
891+
#endif /* STM32F3 || STM32G4 || STM32H7 */
892+
878893
#if defined(STM32G4)
879894
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
880895
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
@@ -1012,8 +1027,8 @@ extern "C" {
10121027
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
10131028
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
10141029
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
1015-
10161030
#endif /* STM32F3 */
1031+
10171032
/**
10181033
* @}
10191034
*/
@@ -1264,10 +1279,10 @@ extern "C" {
12641279
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
12651280
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
12661281

1267-
#if defined(STM32H5) || defined(STM32H7RS)
1282+
#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6)
12681283
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
12691284
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
1270-
#endif /* STM32H5 || STM32H7RS */
1285+
#endif /* STM32H5 || STM32H7RS || STM32N6 */
12711286

12721287
#if defined(STM32WBA)
12731288
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1279,10 +1294,10 @@ extern "C" {
12791294
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
12801295
#endif /* STM32WBA */
12811296

1282-
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
1297+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
12831298
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
12841299
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
1285-
#endif /* STM32H5 || STM32WBA || STM32H7RS */
1300+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
12861301

12871302
#if defined(STM32F7)
12881303
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -2014,12 +2029,12 @@ extern "C" {
20142029
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
20152030
* @{
20162031
*/
2017-
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
2032+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6)
20182033
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
20192034
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
20202035
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
20212036
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
2022-
#endif /* STM32H5 || STM32WBA || STM32H7RS */
2037+
#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */
20232038

20242039
/**
20252040
* @}
@@ -3679,8 +3694,10 @@ extern "C" {
36793694
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
36803695
#endif
36813696

3697+
36823698
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3683-
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
3699+
defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \
3700+
defined(STM32U0)
36843701
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
36853702
#else
36863703
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3931,7 +3948,8 @@ extern "C" {
39313948
*/
39323949
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
39333950
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3934-
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
3951+
defined (STM32WBA) || defined (STM32H5) || \
3952+
defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3)
39353953
#else
39363954
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
39373955
#endif
@@ -4225,6 +4243,33 @@ extern "C" {
42254243

42264244
#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
42274245
#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
4246+
#if defined(STM32U5)
4247+
#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD
4248+
#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK
4249+
#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC
4250+
#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST
4251+
#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF
4252+
#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT
4253+
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM
4254+
#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM
4255+
#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK
4256+
#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ
4257+
#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT
4258+
#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0
4259+
#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1
4260+
#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM
4261+
#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG
4262+
#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM
4263+
#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM
4264+
#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT
4265+
#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM
4266+
#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM
4267+
#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID
4268+
#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0
4269+
#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1
4270+
#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK
4271+
#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK
4272+
#endif
42284273
/**
42294274
* @}
42304275
*/

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd.h

+7-10
Original file line numberDiff line numberDiff line change
@@ -806,20 +806,17 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd);
806806
\
807807
*(pdwReg) &= 0x3FFU; \
808808
\
809-
if ((wCount) > 62U) \
809+
if ((wCount) == 0U) \
810810
{ \
811-
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
811+
*(pdwReg) |= USB_CNTRX_BLSIZE; \
812+
} \
813+
else if ((wCount) <= 62U) \
814+
{ \
815+
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
812816
} \
813817
else \
814818
{ \
815-
if ((wCount) == 0U) \
816-
{ \
817-
*(pdwReg) |= USB_CNTRX_BLSIZE; \
818-
} \
819-
else \
820-
{ \
821-
PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \
822-
} \
819+
PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \
823820
} \
824821
} while(0) /* PCD_SET_EP_CNT_RX_REG */
825822

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_pcd_ex.h

-1
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,6 @@ extern "C" {
4747
*/
4848

4949

50-
5150
HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr,
5251
uint16_t ep_kind, uint32_t pmaadress);
5352

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_hal_spi.h

+25-21
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef
118118

119119
SPI_InitTypeDef Init; /*!< SPI communication parameters */
120120

121-
uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
121+
const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */
122122

123123
uint16_t TxXferSize; /*!< SPI Tx Transfer size */
124124

@@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
426426
* @retval None
427427
*/
428428
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
429-
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \
430-
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
431-
(__HANDLE__)->MspInitCallback = NULL; \
432-
(__HANDLE__)->MspDeInitCallback = NULL; \
433-
} while(0)
429+
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
430+
do{ \
431+
(__HANDLE__)->State = HAL_SPI_STATE_RESET; \
432+
(__HANDLE__)->MspInitCallback = NULL; \
433+
(__HANDLE__)->MspDeInitCallback = NULL; \
434+
} while(0)
434435
#else
435436
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
436437
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
@@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
533534
__IO uint32_t tmpreg_fre = 0x00U; \
534535
tmpreg_fre = (__HANDLE__)->Instance->SR; \
535536
UNUSED(tmpreg_fre); \
536-
}while(0U)
537+
} while(0U)
537538

538539
/** @brief Enable the SPI peripheral.
539540
* @param __HANDLE__ specifies the SPI Handle.
@@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
577578
* This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
578579
* @retval None
579580
*/
580-
#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
581-
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U)
581+
#define SPI_RESET_CRC(__HANDLE__) \
582+
do{ \
583+
CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
584+
SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
585+
} while(0U)
582586

583587
/** @brief Check whether the specified SPI flag is set or not.
584588
* @param __SR__ copy of SPI SR register.
@@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
596600
* @retval SET or RESET.
597601
*/
598602
#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
599-
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
603+
((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
600604

601605
/** @brief Check whether the specified SPI Interrupt is set or not.
602606
* @param __CR2__ copy of SPI CR2 register.
@@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
608612
* @retval SET or RESET.
609613
*/
610614
#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
611-
(__INTERRUPT__)) ? SET : RESET)
615+
(__INTERRUPT__)) ? SET : RESET)
612616

613617
/** @brief Checks if SPI Mode parameter is in allowed range.
614618
* @param __MODE__ specifies the SPI Mode.
@@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
746750
*/
747751
#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
748752
((__POLYNOMIAL__) <= 0xFFFFU) && \
749-
(((__POLYNOMIAL__)&0x1U) != 0U))
753+
(((__POLYNOMIAL__)&0x1U) != 0U))
750754

751755
/** @brief Checks if DMA handle is valid.
752756
* @param __HANDLE__ specifies a DMA Handle.
@@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
789793
* @{
790794
*/
791795
/* I/O operation functions ***************************************************/
792-
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
796+
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
793797
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
794-
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
795-
uint32_t Timeout);
796-
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
798+
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
799+
uint16_t Size, uint32_t Timeout);
800+
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
797801
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
798-
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
802+
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
799803
uint16_t Size);
800-
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
804+
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size);
801805
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
802-
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
806+
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData,
803807
uint16_t Size);
804808
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
805809
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
@@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
825829
* @{
826830
*/
827831
/* Peripheral State and Error functions ***************************************/
828-
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
829-
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
832+
HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi);
833+
uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi);
830834
/**
831835
* @}
832836
*/

Diff for: ‎system/Drivers/STM32WBxx_HAL_Driver/Inc/stm32wbxx_ll_adc.h

+5-5
Original file line numberDiff line numberDiff line change
@@ -7204,7 +7204,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx)
72047204
}
72057205

72067206
#else
7207-
#endif /* ADC_SUPPORT_2_5_MSPS */
7207+
#endif
72087208
/**
72097209
* @brief Get flag ADC group regular end of unitary conversion.
72107210
* @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC
@@ -7359,7 +7359,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)
73597359
}
73607360

73617361
#else
7362-
#endif /* ADC_SUPPORT_2_5_MSPS */
7362+
#endif
73637363
/**
73647364
* @brief Clear flag ADC group regular end of unitary conversion.
73657365
* @rmtoll ISR EOC LL_ADC_ClearFlag_EOC
@@ -7519,7 +7519,7 @@ __STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)
75197519
}
75207520

75217521
#else
7522-
#endif /* ADC_SUPPORT_2_5_MSPS */
7522+
#endif
75237523
/**
75247524
* @brief Enable interruption ADC group regular end of unitary conversion.
75257525
* @rmtoll IER EOCIE LL_ADC_EnableIT_EOC
@@ -7671,7 +7671,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)
76717671
}
76727672

76737673
#else
7674-
#endif /* ADC_SUPPORT_2_5_MSPS */
7674+
#endif
76757675
/**
76767676
* @brief Disable interruption ADC group regular end of unitary conversion.
76777677
* @rmtoll IER EOCIE LL_ADC_DisableIT_EOC
@@ -7824,7 +7824,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx)
78247824
}
78257825

78267826
#else
7827-
#endif /* ADC_SUPPORT_2_5_MSPS */
7827+
#endif
78287828
/**
78297829
* @brief Get state of interruption ADC group regular end of unitary conversion
78307830
* (0: interrupt disabled, 1: interrupt enabled).

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