dt-bindings: pinctrl: mt7988 update pin names

Author: frank-w

Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml

@@ -4,7 +4,7 @@
 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7988-pinctrl.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: MediaTek MT7986 Pin Controller
+title: MediaTek MT7988 Pin Controller
 
 maintainers:
   - Sean Wang <[email protected]>
@@ -792,26 +792,25 @@ mt7988_int_usxgmii_groups
             description:
               An array of strings. Each string contains the name of a pin.
             items:
-              enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0,
-                     GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7,
-                     GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13,
-                     GPIO_14, GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI,
-                     SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK,
-                     SPI1_MOSI, SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI,
-                     SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP, UART0_RXD,
-                     UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD, UART1_CTS,
-                     UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS, UART2_RTS,
-                     EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2, EMMC_DATA_3,
-                     EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6, EMMC_DATA_7,
-                     EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX, PCM_DRX,
-                     PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO,
-                     WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK,
-                     WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0,
-                     WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9,
-                     WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ,
-                     WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3,
-                     WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7,
-                     WF1_HB8]
+              enum: [UART2_RXD,UART2_TXD,UART2_CTS,UART2_RTS,GPIO_A,SMI_0_MDC,
+                     SMI_0_MDIO,PCIE30_2L_0_WAKE_N,PCIE30_2L_0_CLKREQ_N,
+                     PCIE30_1L_1_WAKE_N,PCIE30_1L_1_CLKREQ_N,GPIO_P,WATCHDOG,
+                     GPIO_RESET,GPIO_WPS,PMIC_I2C_SCL,PMIC_I2C_SDA,I2C_1_SCL,
+                     I2C_1_SDA,PCIE30_2L_0_PRESET_N,PCIE30_1L_1_PRESET_N,PWMD1,
+                     SPI0_WP,SPI0_HOLD,SPI0_CSB,SPI0_MISO,SPI0_MOSI,SPI0_CLK,
+                     SPI1_CSB,SPI1_MISO,SPI1_MOSI,SPI1_CLK,SPI2_CLK,SPI2_MOSI,
+                     SPI2_MISO,SPI2_CSB,SPI2_HOLD,SPI2_WP,EMMC_RSTB,EMMC_DSL,
+                     EMMC_CK,EMMC_CMD,EMMC_DATA_7,EMMC_DATA_6,EMMC_DATA_5,
+                     EMMC_DATA_4,EMMC_DATA_3,EMMC_DATA_2,EMMC_DATA_1,
+                     EMMC_DATA_0,PCM_FS_I2S_LRCK,PCM_CLK_I2S_BCLK,
+                     PCM_DRX_I2S_DIN,PCM_DTX_I2S_DOUT,PCM_MCK_I2S_MCLK,
+                     UART0_RXD,UART0_TXD,PWMD0,JTAG_JTDI,JTAG_JTDO,JTAG_JTMS,
+                     JTAG_JTCLK,JTAG_JTRST_N,USB_DRV_VBUS_P1,LED_A,LED_B,LED_C,
+                     LED_D,LED_E,GPIO_B,GPIO_C,I2C_2_SCL,I2C_2_SDA,
+                     PCIE30_2L_1_PRESET_N,PCIE30_1L_0_PRESET_N,
+                     PCIE30_2L_1_WAKE_N,PCIE30_2L_1_CLKREQ_N,
+                     PCIE30_1L_0_WAKE_N,PCIE30_1L_0_CLKREQ_N,USB_DRV_VBUS_P0,
+                     UART1_RXD,UART1_TXD,UART1_CTS,UART1_RTS] //mt7988
             maxItems: 101
 
           bias-disable: true