equality comparison puts parens in labels

[chick]

Certain equality comparisons can
created broken .dot files.

circuit HasPrintfProblem :
  module HasPrintfProblem :
    input clock : Clock
    input reset : UInt<1>
    output io : {flip in : UInt<10>, out : UInt<10>}

    wire y : UInt<10> @[PrintfTreadleVsVerilatorTest.scala 62:15]
    reg regY : UInt<10>, clock @[PrintfTreadleVsVerilatorTest.scala 65:17]
    reg regRegY : UInt<10>, clock @[PrintfTreadleVsVerilatorTest.scala 66:20]
    regY <= y @[PrintfTreadleVsVerilatorTest.scala 68:8]
    regRegY <= regY @[PrintfTreadleVsVerilatorTest.scala 69:11]
    y <= io.in @[PrintfTreadleVsVerilatorTest.scala 70:5]
    node _T = eq(regRegY, UInt<9>("h01e0")) @[PrintfTreadleVsVerilatorTest.scala 72:16]
    when _T : @[PrintfTreadleVsVerilatorTest.scala 72:27]
      node _T_1 = eq(regRegY, UInt<1>("h00")) @[PrintfTreadleVsVerilatorTest.scala 73:93]
      node _T_2 = eq(regRegY, UInt<9>("h01e0")) @[PrintfTreadleVsVerilatorTest.scala 73:110]
      node _T_3 = bits(reset, 0, 0) @[PrintfTreadleVsVerilatorTest.scala 73:11]
      node _T_4 = eq(_T_3, UInt<1>("h00")) @[PrintfTreadleVsVerilatorTest.scala 73:11]
      when _T_4 : @[PrintfTreadleVsVerilatorTest.scala 73:11]
        printf(clock, UInt<1>(1), "PRINTF y=%d ry=%d rry=%d isZero=%x regRegY=480=%x\n", y, regY, regRegY, _T_1, _T_2) @[PrintfTreadleVsVerilatorTest.scala 73:11]
        skip @[PrintfTreadleVsVerilatorTest.scala 73:11]
      skip @[PrintfTreadleVsVerilatorTest.scala 72:27]
    io.out <= regRegY @[PrintfTreadleVsVerilatorTest.scala 76:10]

[chick]

This should be fixed by PR #26