additional timing value, fix georam image saving, self-healing menu

Author: frntc

Source/Firmware/config.cpp

@@ -33,7 +33,7 @@
 #include "helpers.h"
 #include "linux/kernel.h"
 
-u32 radStartup = 0, radStartupSize = 0;
+u32 radStartup = 0, radStartupSize = 0, radSilentMode = 0, radWaitCycles = 200000;
 
 int atoi( char* str )
 {
@@ -86,6 +86,21 @@ int readConfig( CLogger *logger, const char *DRIVE, const char *FILENAME )
 
 			if ( ptr )
 			{
+				if ( strcmp( ptr, "BOOT_DELAY" ) == 0 && ( ptr = strtok_r( NULL, "\"", &rest ) )  )
+				{
+					s32 delay = atoi( ptr );
+					while ( *ptr == '\t' || *ptr == ' ' ) ptr++;
+					if ( delay < 200 ) delay = 200;
+					radWaitCycles = delay * 1000;
+				}
+
+				if ( strcmp( ptr, "VERBOSITY" ) == 0 )
+				{
+					ptr = strtok_r( NULL, " \t", &rest );
+					if ( strcmp( ptr, "NORMAL" ) == 0 ) radSilentMode = 0;
+					if ( strcmp( ptr, "SILENT" ) == 0 ) radSilentMode = 0xffffffff; 
+				}
+
 				if ( strcmp( ptr, "STARTUP" ) == 0 )
 				{
 					ptr = strtok_r( NULL, " \t", &rest );
@@ -145,6 +160,8 @@ int readConfig( CLogger *logger, const char *DRIVE, const char *FILENAME )
 	if ( timingValues[ 19 ] ) CACHING_L2_OFFSET_KB = timingValues[ 19 ];
 	if ( timingValues[ 20 ] ) CACHING_L2_PRELOADS_PER_CYCLE = timingValues[ 20 ];
 
+	if ( timingValues[ 21 ] ) TIMING_RW_BEFORE_ADDR = timingValues[ 21 ];
+
 	return 1;
 }
 

Source/Firmware/config.h

@@ -28,9 +28,9 @@
 #ifndef _config_h
 #define _config_h
 
-extern u32 radStartup, radStartupSize;
+extern u32 radStartup, radStartupSize, radSilentMode, radWaitCycles;
 
-#define TIMING_NAMES 21
+#define TIMING_NAMES 22
 const char timingNames[TIMING_NAMES][32] = {
 	"WAIT_FOR_SIGNALS", 
 	"WAIT_CYCLE_READ", 
@@ -52,7 +52,8 @@ const char timingNames[TIMING_NAMES][32] = {
 	"WAIT_BA_SIGNAL_AVAIL",
 	"CACHING_L1_WINDOW_KB",
 	"CACHING_L2_OFFSET_KB",
-	"CACHING_L2_PRELOADS_PER_CYCLE"
+	"CACHING_L2_PRELOADS_PER_CYCLE",
+	"WAIT_RW_BEFORE_ADDR"
 };
 
 extern int readConfig( CLogger *logger, const char *DRIVE, const char *FILENAME );

Source/Firmware/lowlevel_arm64.cpp

@@ -52,6 +52,8 @@ u32 CACHING_L1_WINDOW_KB = 0;
 u32 CACHING_L2_OFFSET_KB = 0;
 u32 CACHING_L2_PRELOADS_PER_CYCLE = 0;
 
+u32 TIMING_RW_BEFORE_ADDR = 40;
+
 // initialize what we need for the performance counters
 void initCycleCounter()
 {

Source/Firmware/lowlevel_arm64.h

@@ -62,6 +62,8 @@ extern u32 CACHING_L1_WINDOW_KB;
 extern u32 CACHING_L2_OFFSET_KB;
 extern u32 CACHING_L2_PRELOADS_PER_CYCLE;
 
+extern u32 TIMING_RW_BEFORE_ADDR;
+
 extern u32 modeC128;
 extern u32 modeVIC, modePALNTSC;
 extern u32 hasSIDKick;

Source/Firmware/lowlevel_dma.h

@@ -96,6 +96,7 @@ __attribute__( ( always_inline ) ) inline u8 flipByte( u8 x )
 	return *(u8*)&t;
 }
 
+
 #define DISABLE_ADDRESS_LATCH_AND_BUSTRANSCEIVER( releaseDMA )								\
 	SET_GPIO( bLATCH_A_OE | bGAME_OUT | bOE_Dx | bRW_OUT | (releaseDMA ? bDMA_OUT : 0) );	\
 	INP_GPIO_RW();																			\
@@ -139,7 +140,20 @@ __attribute__( ( always_inline ) ) inline u8 flipByte( u8 x )
 		} while ( !(g2 & bBA) );							\
 	}								
 
+#define HANDLE_BUS_AVAILABLE \
+	WAIT_UP_TO_CYCLE( reu.TIMING_READ_BA_WRITING );			\
+	/*g2 = read32( ARM_GPIO_GPLEV0 );						*/	\
+	if ( VIC_BA ) {											\
+		do {												\
+			WAIT_FOR_CPU_HALFCYCLE							\
+			WAIT_FOR_VIC_HALFCYCLE							\
+			RESTART_CYCLE_COUNTER							\
+			WAIT_UP_TO_CYCLE( reu.TIMING_READ_BA_WRITING );	\
+			g2 = read32( ARM_GPIO_GPLEV0 );					\
+		} while ( !(g2 & bBA) );							\
+	}								
 
+#if 0
 #define HANDLE_BUS_AVAILABLE \
 	WAIT_UP_TO_CYCLE( reu.TIMING_READ_BA_WRITING );			\
 	/*g2 = read32( ARM_GPIO_GPLEV0 );*/						\
@@ -149,7 +163,7 @@ __attribute__( ( always_inline ) ) inline u8 flipByte( u8 x )
 		RESTART_CYCLE_COUNTER								\
 		WAIT_UP_TO_CYCLE( reu.TIMING_READ_BA_WRITING );		\
 		g2 = read32( ARM_GPIO_GPLEV0 ); }
-
+#endif
 
 __attribute__( ( always_inline ) ) inline 
 void emuReadByteREU_p1( register u32 &g2, u16 addr )
@@ -204,26 +218,30 @@ void emuReadByteREU_p3( register u32 &g2, register u8 &x, bool releaseDMA )
 __attribute__( ( always_inline ) ) inline  
 void emuWriteByteREU_p1( register u32 &g2, u16 addr, u8 data )
 {
-	register u32 DD = flipByte( ( addr ) & 255 ) << D0;
+	register u32 A asm ("r3" ) = addr;
+	register u32 DD asm ("r4" );
+	asm volatile( "rbit %w0, %w1" : "=r" ( A ) : "r" ( A ) );	// flip all bits in 32-bit-DWORD
+	DD = ( A & 0x00ff0000 ) << ( D0 - 16 );
+
 	SET_GPIO( bLATCH_A0 | bLATCH_A8 | DD );
 	CLR_GPIO( bDMA_OUT | ( D_FLAG & ( ~DD ) ) );
-	DD = flipByte( ( ( addr ) >> 8 ) & 255 ) << D0;
-	CLR_GPIO( bDIR_Dx | bRW_OUT | bLATCH_A0 );
+	DD = ( A & 0xff000000 ) >> ( 24 - D0 );
+
+	CLR_GPIO( bDIR_Dx | bRW_OUT | bLATCH_A8 );
 	SET_GPIO( DD );
 	CLR_GPIO( ( D_FLAG & ( ~DD ) ) );
-	DD = ( ( data ) & 255 ) << D0;
-	CLR_GPIO( bLATCH_A8 );
+	DD = data << D0;
+	CLR_GPIO( bLATCH_A0 );
+
 	SET_GPIO( DD );
 	CLR_GPIO( ( D_FLAG & ( ~DD ) ) );
 
 	HANDLE_BUS_AVAILABLE
 
-	// this RW_OUT a bit before A_OE and DIR_Dx is important for old VICs,
-	// and took me quite a while to figure out...
-	WAIT_UP_TO_CYCLE(reu.TIMING_ENABLE_RWOUT_ADDR_LATCH_WRITING - 40 );
+	WAIT_UP_TO_CYCLE(reu.TIMING_ENABLE_RWOUT_ADDR_LATCH_WRITING_MINUS_RW_BEFORE_ADDR );
 	OUT_GPIO( RW_OUT );
 	WAIT_UP_TO_CYCLE( reu.TIMING_ENABLE_RWOUT_ADDR_LATCH_WRITING + 0 );
-	CLR_GPIO( bLATCH_A_OE | bDIR_Dx );
+	CLR_GPIO( bLATCH_A_OE );
 
 	WAIT_UP_TO_CYCLE( reu.TIMING_ENABLE_DATA_WRITING );
 	CLR_GPIO( bOE_Dx );

Source/Firmware/rad_georam.h

@@ -53,7 +53,8 @@ typedef struct
 volatile static GEOSTATE geo AAA;
 
 // geoRAM memory pool 
-static u8  *geoRAM_Pool = mempool;
+extern u8* mempoolPtr;
+static u8  *geoRAM_Pool = (u8*)mempoolPtr;
 
 // u8* to current window
 #define GEORAM_WINDOW (&geo.RAM[ ( geo.reg[ 1 ] * 16384 ) + ( geo.reg[ 0 ] * 256 ) ])
@@ -62,7 +63,7 @@ static u8  *geoRAM_Pool = mempool;
 static void geoRAM_Init()
 {
 	geo.reg[ 0 ] = geo.reg[ 1 ] = 0;
-	geo.RAM = (u8*)( ( (u64)&geoRAM_Pool[0] + 128 ) & ~127 );
+	geo.RAM = &geoRAM_Pool[0]; //(u8*)( ( (u64)&geoRAM_Pool[0] + 128 ) & ~127 );
 	memset( geo.RAM, 0, geoSizeKB * 1024 );
 
 	geo.c64CycleCount = 0;