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1 | 1 | /* |
2 | | - ______/ _____/ _____/ / _/ / / |
3 | | - _/ / / / / _/ / ______/ / _/ ____/ / ______/ ____/ |
4 | | - ___/ / / / ___/ / / __/ _/ / / / / |
5 | | - _/ _/ _/ _/ / _/ / _/ / _/ _____/ / _/ _/ _/ |
| 2 | + ______/ _____/ _____/ / _/ / / |
| 3 | + _/ / / / / _/ / ______/ / _/ ____/ / ______/ ____/ |
| 4 | + ___/ / / / ___/ / / __/ _/ / / / / |
| 5 | + _/ _/ _/ _/ / _/ / _/ / _/ _____/ / _/ _/ _/ |
6 | 6 | ______/ _____/ ______/ _/ _/ _/ _____/ _/ _/ _/ _/ _____/ ____/ |
7 | 7 |
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8 | 8 | SKpico.c |
@@ -98,15 +98,15 @@ uint8_t sidDACMode = SID_DAC_OFF; |
98 | 98 | #define VERSION_STR_SIZE 36 |
99 | 99 | static const __not_in_flash( "mydata" ) unsigned char VERSION_STR[ VERSION_STR_SIZE ] = { |
100 | 100 | #if defined( USE_SPDIF ) |
101 | | - 0x53, 0x4b, 0x10, 0x09, 0x03, 0x0f, '0', '.', '2', '0', '/', 0x53, 0x50, 0x44, 0x49, 0x46, 0, 0, 0, 0, // version string to show |
| 101 | + 0x53, 0x4b, 0x10, 0x09, 0x03, 0x0f, '0', '.', '2', '1', '/', 0x53, 0x50, 0x44, 0x49, 0x46, 0, 0, 0, 0, // version string to show |
102 | 102 | #endif |
103 | 103 | #if defined( USE_DAC ) |
104 | | - 0x53, 0x4b, 0x10, 0x09, 0x03, 0x0f, '0', '.', '2', '0', '/', 0x44, 0x41, 0x43, '6', '4', 0, 0, 0, 0, // version string to show |
| 104 | + 0x53, 0x4b, 0x10, 0x09, 0x03, 0x0f, '0', '.', '2', '1', '/', 0x44, 0x41, 0x43, '6', '4', 0, 0, 0, 0, // version string to show |
105 | 105 | #elif defined( OUTPUT_VIA_PWM ) |
106 | | - 0x53, 0x4b, 0x10, 0x09, 0x03, 0x0f, '0', '.', '2', '0', '/', 0x50, 0x57, 0x4d, '6', '4', 0, 0, 0, 0, // version string to show |
| 106 | + 0x53, 0x4b, 0x10, 0x09, 0x03, 0x0f, '0', '.', '2', '1', '/', 0x50, 0x57, 0x4d, '6', '4', 0, 0, 0, 0, // version string to show |
107 | 107 | #endif |
108 | 108 | 0x53, 0x4b, 0x10, 0x09, 0x03, 0x0f, 0x00, 0x00, // signature + extension version 0 |
109 | | - 0, 14, // firmware version with stepping = 0.12 |
| 109 | + 0, 21, // firmware version with stepping = 0.12 |
110 | 110 | #ifdef SID_DAC_MODE_SUPPORT // support DAC modes? which? |
111 | 111 | SID_DAC_MONO8 | SID_DAC_STEREO8, |
112 | 112 | #else |
@@ -135,9 +135,11 @@ extern void readRegs( uint8_t *p1, uint8_t *p2 ); |
135 | 135 | #define PHI 12 |
136 | 136 | #define AUDIO_PIN 13 |
137 | 137 | #define SID 21 |
| 138 | +#define RESET 22 |
138 | 139 | #define LED_BUILTIN 25 |
139 | 140 | #define POTX ( 10 ) |
140 | 141 | #define POTY ( 11 ) |
| 142 | +#define bRESET ( 1 << RESET ) |
141 | 143 | #define bSID ( 1 << SID ) |
142 | 144 | #define bPHI ( 1 << PHI ) |
143 | 145 | #define bRW ( 1 << RW ) |
@@ -293,6 +295,11 @@ uint32_t ringTime[ RING_SIZE ]; |
293 | 295 | uint8_t ringWrite = 0; |
294 | 296 | uint8_t ringRead = 0; |
295 | 297 |
|
| 298 | +void resetEverything() |
| 299 | +{ |
| 300 | + ringRead = ringWrite = 0; |
| 301 | +} |
| 302 | + |
296 | 303 | uint8_t stateGoingTowardsTransferMode = 0; |
297 | 304 |
|
298 | 305 | typedef enum { |
@@ -597,8 +604,6 @@ void runEmulation() |
597 | 604 | { |
598 | 605 | writeReSID2( ( cmd >> 8 ) & 0x1f, cmd & 255 ); |
599 | 606 | } |
600 | | - //pio_sm_put_blocking( pio0, 1, 0xffffff ); |
601 | | - //while ( 1 ) {} |
602 | 607 | } else |
603 | 608 | { |
604 | 609 | uint8_t reg = cmd >> 8; |
@@ -1293,6 +1298,33 @@ void handleBus() |
1293 | 1298 | { |
1294 | 1299 | skipSmoothing = 0; |
1295 | 1300 |
|
| 1301 | + #define max( a, b ) ( (a)>(b)?(a):(b) ) |
| 1302 | + #define min( a, b ) ( (a)<(b)?(a):(b) ) |
| 1303 | + #ifdef DIAGROM_HACK |
| 1304 | + if ( DIAGROM_THRESHOLD >= 80 ) |
| 1305 | + { |
| 1306 | + if ( abs( newPotXCandidate - newPotYCandidate ) < 10 && newPotXCandidate >= 50 && newPotXCandidate < DIAGROM_THRESHOLD ) |
| 1307 | + { |
| 1308 | + if ( presumablyFixedResistor < 40000 ) |
| 1309 | + presumablyFixedResistor ++; |
| 1310 | + } else |
| 1311 | + { |
| 1312 | + if ( presumablyFixedResistor ) |
| 1313 | + presumablyFixedResistor --; |
| 1314 | + } |
| 1315 | + if ( presumablyFixedResistor > 1000 ) |
| 1316 | + diagROM_PaddleOffset = min( DIAGROM_THRESHOLD - newPotXCandidate, ( presumablyFixedResistor - 1000 ) / 1000 ); else |
| 1317 | + diagROM_PaddleOffset = 0; |
| 1318 | + newPotXCandidate = min( 255, (int)newPotXCandidate + (int)diagROM_PaddleOffset ); |
| 1319 | + newPotYCandidate = min( 255, (int)newPotYCandidate + (int)diagROM_PaddleOffset ); |
| 1320 | + } else |
| 1321 | + if ( DIAGROM_THRESHOLD > 1 ) |
| 1322 | + { |
| 1323 | + newPotXCandidate = min( 255, (int)newPotXCandidate + (int)DIAGROM_THRESHOLD ); |
| 1324 | + newPotYCandidate = min( 255, (int)newPotYCandidate + (int)DIAGROM_THRESHOLD ); |
| 1325 | + } |
| 1326 | + #endif |
| 1327 | + |
1296 | 1328 | if ( !paddleFilterMode ) |
1297 | 1329 | { |
1298 | 1330 | outRegisters[ 25 ] = newPotXCandidate; |
@@ -1446,6 +1478,7 @@ void handleBus() |
1446 | 1478 | \__, \__/ | \| | | \__> |__) \__/ .__/ | | /~~\ | \| |__/ |___ | | \| \__> |
1447 | 1479 | */ |
1448 | 1480 | uint8_t busTimingTestValue = 0; |
| 1481 | + uint8_t transferPRGSlot = 0; |
1449 | 1482 | while ( true ) |
1450 | 1483 | { |
1451 | 1484 | // |
@@ -1574,6 +1607,97 @@ void handleBus() |
1574 | 1607 | prgLaunch = 1; |
1575 | 1608 | stateInConfigMode = 0; |
1576 | 1609 | } else |
| 1610 | + if ( A == 0x14 || A == 0x15 ) // start bus timing banging: value #1 and #2 |
| 1611 | + { |
| 1612 | + transferPRGSlot = 254 - 0x14 + A; |
| 1613 | + transferPayload = prgCode; |
| 1614 | + stateInConfigMode = CONFIG_MODE_CYCLES; |
| 1615 | + } else |
| 1616 | + if ( A == 0x1a ) // start PRG upload |
| 1617 | + { |
| 1618 | + transferPRGSlot = D; |
| 1619 | + transferPayload = prgCode; |
| 1620 | + stateInConfigMode = CONFIG_MODE_CYCLES; |
| 1621 | + } else |
| 1622 | + if ( A == 0x19 ) // set PRG upload page |
| 1623 | + { |
| 1624 | + transferPayload = prgCode + D * 256; |
| 1625 | + stateInConfigMode = CONFIG_MODE_CYCLES; |
| 1626 | + } else |
| 1627 | + if ( A == 0x16 ) // upload one PRG byte |
| 1628 | + { |
| 1629 | + *transferPayload = D; |
| 1630 | + transferPayload ++; |
| 1631 | + stateInConfigMode = CONFIG_MODE_CYCLES; |
| 1632 | + } else |
| 1633 | + if ( A == 0x17 ) // end PRG upload, or end of bus timing banging! |
| 1634 | + { |
| 1635 | + SET_CLOCK_125MHZ |
| 1636 | + DELAY_Nx3p2_CYCLES( 85000 ); |
| 1637 | + |
| 1638 | + if ( transferPRGSlot >= 254 ) |
| 1639 | + { |
| 1640 | + int *histo = (int*)&prgCode[ 16384 ]; |
| 1641 | + memset( histo, 0, 256 * sizeof( int ) ); |
| 1642 | + int sz = transferPayload - prgCode; |
| 1643 | + for ( int i = 0; i < sz; i++ ) |
| 1644 | + histo[ prgCode[ i ] ] ++; |
| 1645 | + int maxV = histo[ 0 ], maxIdx = 0; |
| 1646 | + for ( int i = 1; i < sz; i++ ) |
| 1647 | + if ( histo[ i ] > maxV ) |
| 1648 | + { |
| 1649 | + maxV = histo[ i ]; |
| 1650 | + maxIdx = i; |
| 1651 | + } |
| 1652 | + |
| 1653 | + if ( transferPRGSlot == 254 ) |
| 1654 | + { |
| 1655 | + DELAY_READ_BUS = maxIdx; |
| 1656 | + }else |
| 1657 | + { |
| 1658 | + DELAY_PHI2 = maxIdx; |
| 1659 | + |
| 1660 | + unsigned char *tmp = &prgCode[ 16384 + 1024 ]; |
| 1661 | + { |
| 1662 | + #define FLASH_BUSTIMING_OFFSET ((uint32_t)&busTimings[ 0 ] - XIP_BASE) |
| 1663 | + memcpy( tmp, (void*)FLASH_BUSTIMING_OFFSET, FLASH_SECTOR_SIZE ); |
| 1664 | + DELAY_READ_BUS_local = tmp[ 0 ] = DELAY_READ_BUS; |
| 1665 | + DELAY_PHI2_local = tmp[ 1 ] = DELAY_PHI2; |
| 1666 | + |
| 1667 | + flash_range_erase ( FLASH_BUSTIMING_OFFSET, FLASH_SECTOR_SIZE ); |
| 1668 | + flash_range_program( FLASH_BUSTIMING_OFFSET, tmp, FLASH_SECTOR_SIZE ); |
| 1669 | + } |
| 1670 | + } |
| 1671 | + } else |
| 1672 | + { |
| 1673 | + int sz = transferPayload - prgCode - 18; // -18 because menu entry is 18 byte (string null-terminated) |
| 1674 | + |
| 1675 | + uint8_t *dirEntry = &prgDirectory[ transferPRGSlot * 24 ]; |
| 1676 | + |
| 1677 | + memcpy( dirEntry, prgCode + sz, 18 ); |
| 1678 | + dirEntry[ 18 ] = 0; |
| 1679 | + dirEntry[ 19 ] = 0; |
| 1680 | + dirEntry[ 20 ] = transferPRGSlot; |
| 1681 | + dirEntry[ 21 ] = 0; |
| 1682 | + dirEntry[ 22 ] = sz & 255; |
| 1683 | + dirEntry[ 23 ] = sz >> 8; |
| 1684 | + |
| 1685 | + #define FLASH_DIR_OFFSET ((uint32_t)&prgDirectory_Flash[ 0 ] - XIP_BASE) |
| 1686 | + flash_range_erase ( FLASH_DIR_OFFSET, FLASH_SECTOR_SIZE ); |
| 1687 | + flash_range_program( FLASH_DIR_OFFSET, prgDirectory, FLASH_SECTOR_SIZE ); |
| 1688 | + |
| 1689 | + prgCode[ 0 ] = 1; |
| 1690 | + prgCode[ 1 ] = 8; |
| 1691 | + |
| 1692 | + #define FLASH_PRG_OFFSET ((uint32_t)&prgRepository[ transferPRGSlot * 65536 ] - XIP_BASE) |
| 1693 | + flash_range_erase ( FLASH_PRG_OFFSET, 65536 ); |
| 1694 | + flash_range_program( FLASH_PRG_OFFSET, prgCode, 65536 ); |
| 1695 | + } |
| 1696 | + SET_CLOCK_FAST |
| 1697 | + prgLaunch = 0; |
| 1698 | + currentPRG = 254; |
| 1699 | + stateInConfigMode = 0; |
| 1700 | + } else |
1577 | 1701 | if ( A == 0x10 ) |
1578 | 1702 | { |
1579 | 1703 | SET_CLOCK_125MHZ |
@@ -1646,7 +1770,6 @@ void writeConfiguration() |
1646 | 1770 | config[ 63 ] = c >> 8; |
1647 | 1771 |
|
1648 | 1772 | flash_range_program( FLASH_CONFIG_OFFSET, config, FLASH_PAGE_SIZE ); |
1649 | | - SET_CLOCK_FAST |
1650 | 1773 |
|
1651 | 1774 | SET_CLOCK_125MHZ |
1652 | 1775 | DELAY_Nx3p2_CYCLES( 85000 ); |
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