award-winning_wishbone_wb_intercon_1.4.2.core

CAPI=2: null
name: award-winning:wishbone:wb_intercon:1.4.2
description: Wishbone Bus Interconnect utilities
license: ISC
filesets:
  rtl:
    files:
      - rtl/verilog/wb_cdc.v
      - rtl/verilog/wb_arbiter.v
      - rtl/verilog/wb_data_resize.v
      - rtl/verilog/wb_mux.v
    file_type: verilogSource
    depend:
      - bmartini::verilog-arbiter
      - award-winning:utils:cdc_utils
      - award-winning:wishbone:wb_common
  tb:
    files:
      - bench/wb_cdc_tb.v
      - bench/wb_mux_tb.v
      - bench/wb_arbiter_tb.v
      - bench/wb_intercon_tb.v
    file_type: verilogSource
    depend:
      - '>=fusesoc:utils:vlog_tb_utils:1.1.0'
      - '>=award-winning:wishbone:wb_bfm:1.1.0'
  constraints:
    files:
      - data/wb_intercon.sdc:
          file_type: SDC
generators:
  wb_intercon_gen:
    interpreter: python3
    command: sw/wb_intercon_gen2.py
    description: Create a wishbone crossbar interconnect from a memory map
    usage: |
      The Wishbone interconnect generator generates a verilog core from a
      description of host and connected device ports.

      Parameters:
        hosts (dict): A named list of host ports. Each host has a list of
                        connected device ports

                        Example

                        hosts:
                          cpu_ibus:
                            devices: [mem, bootrom]
                          cpu_dbus: [mem, uart, spi1, spi2]
        devices (dict): A named list of device ports. Each device defines the
                       and space they occupy in the memory map

                       Example

                       devices:
                         bootrom:
                           offset : 0xf0000000
                           size   : 512
                          uart:
                            offset : 0x90000000
                            size   : 16
                          mem:
                            offset : 0x00000000
                            size   : 0x100000
targets:
  default:
    filesets:
      - rtl
      - tool_quartus? (constraints)
    tools:
      isim:
        fuse_options:
          - '-d'
          - BROKEN_CLOG2
  sim:
    default_tool: icarus
    description: wb_intercon regression tests
    filesets:
      - rtl
      - tb
    parameters:
      - transactions
    tools:
      isim:
        fuse_options:
          - '-d'
          - BROKEN_CLOG2
    toplevel: wb_intercon_tb
parameters:
  transactions:
    datatype: int
    description: Number of wishbone transactions to run in test bench
    paramtype: plusarg
provider:
  name: github
  user: olofk
  repo: wb_intercon
  version: 2f5f06481719c81616c7916b34ad9eb81eb9fa2b