-
Notifications
You must be signed in to change notification settings - Fork 2
Expand file tree
/
Copy pathbespoke-silicon-group_basejump_stl_hard_0.0.1.core
More file actions
216 lines (216 loc) · 10.8 KB
/
bespoke-silicon-group_basejump_stl_hard_0.0.1.core
File metadata and controls
216 lines (216 loc) · 10.8 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
CAPI=2: ''
###############################################################
# WARNING-AUTOGENERATED: DO NOT MODIFY #
# Auto-generated by: #
# https://github.com/dpetrisko/basejump_stl_cores #
# #
# Please submit issues / PRs to the generator repo instead! #
###############################################################
name: bespoke-silicon-group:basejump_stl:hard:0.0.1
description: 'BaseJump STL: A Standard Template Library for SystemVerilog (Hardened)'
filesets:
rtl:
files:
- hard/fakeram/bsg_mem_1rw_sync_macros.svh:
is_include_file: true
- hard/fakeram/bsg_mem_1rw_sync_mask_write_bit_macros.svh:
is_include_file: true
- hard/fakeram/bsg_mem_1rw_sync_mask_write_byte_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_1r1w_sync_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_1r1w_sync_mask_write_byte_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_1rw_sync_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_2r1w_sync_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_2rw_sync_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_2rw_sync_mask_write_bit_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_2rw_sync_mask_write_byte_macros.svh:
is_include_file: true
- hard/generic/bsg_mem/bsg_mem_3r1w_sync_macros.svh:
is_include_file: true
- hard/gf_14/bsg_mem/bsg_mem_1r1w_sync_macros.svh:
is_include_file: true
- hard/gf_14/bsg_mem/bsg_mem_1rw_sync_macros.svh:
is_include_file: true
- hard/gf_14/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_macros.svh:
is_include_file: true
- hard/gf_14/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_macros.svh:
is_include_file: true
- hard/gf_14/bsg_mem/bsg_mem_2r1w_sync_macros.svh:
is_include_file: true
- hard/gf_14/bsg_mem/bsg_mem_3r1w_sync_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_1r1w_sync_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_1r1w_sync_mask_write_byte_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_1rw_sync_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_2r1w_sync_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_2rw_sync_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_2rw_sync_mask_write_bit_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_2rw_sync_mask_write_byte_macros.svh:
is_include_file: true
- hard/tsmc_28/bsg_mem/bsg_mem_3r1w_sync_macros.svh:
is_include_file: true
- hard/gf_14/bsg_async/bsg_launch_sync_sync.sv
- hard/gf_14/bsg_async/bsg_sync_sync.sv
- hard/gf_14/bsg_clk_gen/bsg_clk_gen_osc.sv
- hard/gf_14/bsg_clk_gen/bsg_rp_clk_gen_atomic_delay_tuner.sv
- hard/gf_14/bsg_clk_gen/bsg_rp_clk_gen_coarse_delay_tuner.sv
- hard/gf_14/bsg_clk_gen/bsg_rp_clk_gen_fine_delay_tuner.sv
- hard/gf_14/bsg_link/bsg_link_isdr_phy.sv
- hard/gf_14/bsg_link/bsg_link_osdr_phy.sv
- hard/gf_14/bsg_misc/bsg_mux.sv
- hard/gf_14/bsg_misc/bsg_tiehi.sv
- hard/gf_14/bsg_misc/bsg_tielo.sv
- hard/pickle_40/bsg_mem/bsg_mem_1rw_sync.sv
- hard/pickle_40/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv
- hard/pickle_40/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv
- hard/pickle_40/bsg_mem/bsg_mem_2r1w_sync.sv
- hard/saed_90/bsg_mem/bsg_mem_1r1w.sv
- hard/saed_90/bsg_mem/bsg_mem_1r1w_sync.sv
- hard/saed_90/bsg_mem/bsg_mem_1rw_sync.sv
- hard/saed_90/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv
- hard/saed_90/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv
- hard/saed_90/bsg_misc/bsg_clkgate_optional.sv
- hard/saed_90/bsg_misc/bsg_dff_gatestack.sv
- hard/saed_90/bsg_misc/bsg_mux2_gatestack.sv
- hard/saed_90/bsg_misc/bsg_muxi2_gatestack.sv
- hard/tsmc_16/bsg_async/bsg_launch_sync_sync.sv
- hard/tsmc_16/bsg_async/bsg_sync_sync.sv
- hard/tsmc_16/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.sv
- hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync.sv
- hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv
- hard/tsmc_16/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv
- hard/tsmc_16/bsg_mem/bsg_mem_2r1w_sync.sv
- hard/tsmc_16/bsg_misc/bsg_level_shift_up_down_sink.sv
- hard/tsmc_16/bsg_misc/bsg_level_shift_up_down_source.sv
- hard/tsmc_16/bsg_misc/bsg_mux.sv
- hard/tsmc_28/bsg_async/bsg_launch_sync_sync.sv
- hard/tsmc_28/bsg_async/bsg_sync_sync.sv
- hard/tsmc_28/bsg_async/bsg_sync_sync_async_reset_unit.sv
- hard/tsmc_28/bsg_async/bsg_sync_sync_unit.sv
- hard/tsmc_28/bsg_clk_gen/bsg_clk_gen_osc_v3.sv
- hard/tsmc_28/bsg_clk_gen/bsg_rp_clk_gen_osc_unit_v3.sv
- hard/tsmc_28/bsg_clk_gen/bsg_rp_clk_gen_osc_v3.sv
- hard/tsmc_28/bsg_dmc/bsg_dmc_dly_line_v3.sv
- hard/tsmc_28/bsg_dmc/bsg_rp_dly_line_v3.sv
- hard/tsmc_28/bsg_link/bsg_link_isdr_phy.sv
- hard/tsmc_28/bsg_link/bsg_link_osdr_phy.sv
- hard/tsmc_28/bsg_misc/bsg_buf.sv
- hard/tsmc_28/bsg_misc/bsg_dff.sv
- hard/tsmc_28/bsg_misc/bsg_mux.sv
- hard/tsmc_28/bsg_misc/bsg_nand.sv
- hard/tsmc_28/bsg_misc/bsg_nor3.sv
- hard/tsmc_28/bsg_misc/bsg_tiehi.sv
- hard/tsmc_28/bsg_misc/bsg_tielo.sv
- hard/tsmc_28/bsg_misc/bsg_xnor.sv
- hard/tsmc_40/bsg_clk_gen/bsg_clk_gen_osc.sv
- hard/tsmc_40/bsg_clk_gen/bsg_dly_line.sv
- hard/tsmc_40/bsg_clk_gen/bsg_rp_clk_gen_atomic_delay_tuner.sv
- hard/tsmc_40/bsg_clk_gen/bsg_rp_clk_gen_coarse_delay_tuner.sv
- hard/tsmc_40/bsg_clk_gen/bsg_rp_clk_gen_fine_delay_tuner.sv
- hard/tsmc_40/bsg_mem/bsg_mem_1r1w.sv
- hard/tsmc_40/bsg_mem/bsg_mem_1r1w_sync.sv
- hard/tsmc_40/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.sv
- hard/tsmc_40/bsg_mem/bsg_mem_1rw_sync.sv
- hard/tsmc_40/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv
- hard/tsmc_40/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv
- hard/tsmc_40/bsg_mem/bsg_mem_2r1w.sv
- hard/tsmc_40/bsg_mem/bsg_mem_2r1w_sync.sv
- hard/tsmc_40/bsg_misc/bsg_and.sv
- hard/tsmc_40/bsg_misc/bsg_buf.sv
- hard/tsmc_40/bsg_misc/bsg_clkbuf.sv
- hard/tsmc_40/bsg_misc/bsg_dff.sv
- hard/tsmc_40/bsg_misc/bsg_dff_en.sv
- hard/tsmc_40/bsg_misc/bsg_dff_reset.sv
- hard/tsmc_40/bsg_misc/bsg_dff_reset_en.sv
- hard/tsmc_40/bsg_misc/bsg_inv.sv
- hard/tsmc_40/bsg_misc/bsg_mux.sv
- hard/tsmc_40/bsg_misc/bsg_mux_bitwise.sv
- hard/tsmc_40/bsg_misc/bsg_mux_one_hot.sv
- hard/tsmc_40/bsg_misc/bsg_nand.sv
- hard/tsmc_40/bsg_misc/bsg_nor3.sv
- hard/tsmc_40/bsg_misc/bsg_reduce.sv
- hard/tsmc_40/bsg_misc/bsg_tiehi.sv
- hard/tsmc_40/bsg_misc/bsg_tielo.sv
- hard/tsmc_40/bsg_misc/bsg_xnor.sv
- hard/tsmc_40/bsg_misc/bsg_xor.sv
- hard/tsmc_40/bsg_misc/bsg_mul/bsg_mul_and_csa_block_hard.sv
- hard/tsmc_40/bsg_misc/bsg_mul/bsg_mul_booth_4_block_rep.sv
- hard/tsmc_40/bsg_misc/bsg_mul/bsg_mul_comp42_rep.sv
- hard/tsmc_180_250/bsg_clk_gen/bsg_clk_gen_osc.sv
- hard/tsmc_180_250/bsg_clk_gen/bsg_rp_clk_gen_atomic_delay_tuner.sv
- hard/tsmc_180_250/bsg_clk_gen/bsg_rp_clk_gen_coarse_delay_tuner.sv
- hard/tsmc_180_250/bsg_clk_gen/bsg_rp_clk_gen_fine_delay_tuner.sv
- hard/tsmc_180_250/bsg_dataflow/bsg_fifo_shift_datapath.sv
- hard/tsmc_180_250/bsg_mem/bsg_mem_1r1w.sv
- hard/tsmc_180_250/bsg_mem/bsg_mem_1r1w_sync_mask_write_bit.sv
- hard/tsmc_180_250/bsg_mem/bsg_mem_1rw_sync.sv
- hard/tsmc_180_250/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv
- hard/tsmc_180_250/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv
- hard/tsmc_180_250/bsg_mem/bsg_mem_2r1w.sv
- hard/tsmc_180_250/bsg_mem/bsg_mem_2r1w_sync.sv
- hard/tsmc_180_250/bsg_misc/bsg_and.sv
- hard/tsmc_180_250/bsg_misc/bsg_buf.sv
- hard/tsmc_180_250/bsg_misc/bsg_clkbuf.sv
- hard/tsmc_180_250/bsg_misc/bsg_dff.sv
- hard/tsmc_180_250/bsg_misc/bsg_dff_en.sv
- hard/tsmc_180_250/bsg_misc/bsg_dff_reset.sv
- hard/tsmc_180_250/bsg_misc/bsg_dff_reset_en.sv
- hard/tsmc_180_250/bsg_misc/bsg_inv.sv
- hard/tsmc_180_250/bsg_misc/bsg_mux.sv
- hard/tsmc_180_250/bsg_misc/bsg_mux_one_hot.sv
- hard/tsmc_180_250/bsg_misc/bsg_nand.sv
- hard/tsmc_180_250/bsg_misc/bsg_nor3.sv
- hard/tsmc_180_250/bsg_misc/bsg_reduce.sv
- hard/tsmc_180_250/bsg_misc/bsg_tiehi.sv
- hard/tsmc_180_250/bsg_misc/bsg_tielo.sv
- hard/tsmc_180_250/bsg_misc/bsg_xnor.sv
- hard/tsmc_180_250/bsg_misc/bsg_xor.sv
- hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_mul_and_csa_block_hard.sv
- hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_mul_booth_4_block_rep.sv
- hard/tsmc_180_250/bsg_misc/bsg_mul/bsg_mul_comp42_rep.sv
- hard/ultrascale_plus/2019.1/bsg_mem_1r1w_sync_mask_write_byte.sv
- hard/ultrascale_plus/2019.1/bsg_mem_1rw_sync_mask_write_bit.sv
- hard/ultrascale_plus/2019.1/bsg_mem_1rw_sync_mask_write_byte.sv
- hard/ultrascale_plus/bsg_async/bsg_launch_sync_sync.sv
- hard/ultrascale_plus/bsg_link/bsg_link_ddr_upstream.sv
- hard/ultrascale_plus/bsg_link/bsg_link_iddr_phy.sv
- hard/ultrascale_plus/bsg_link/bsg_link_oddr_phy.sv
- hard/ultrascale_plus/bsg_mem/bsg_mem_1r1w_sync.sv
- hard/ultrascale_plus/bsg_mem/bsg_mem_1r1w_sync_mask_write_byte.sv
- hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync.sv
- hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.sv
- hard/ultrascale_plus/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.sv
- hard/ultrascale_plus/bsg_misc/bsg_clkgate_optional.sv
- hard/ultrascale_plus/bsg_misc/bsg_mul_add_unsigned.sv
- hard/ultrascale_plus/bsg_misc/bsg_mux.sv
file_type: systemVerilogSource
nonsynth: {}
provider:
name: github
user: bespoke-silicon-group
repo: basejump_stl
version: v0.0.1