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HalfSweetHalfSweet
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fix: add DBG uart define
1 parent ae16881 commit ca3851d

3 files changed

Lines changed: 130 additions & 96 deletions

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‎src/fw/board/board_sf32lb.h‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,17 @@ typedef enum {
3636
// This is generated in order to faciliate the check within the IRQ_MAP macro below
3737
#include "bf0_hal.h"
3838

39+
// This is generated in order to faciliate the check within the IRQ_MAP macro below
40+
enum {
41+
#define IRQ_DEF(num, irq) IS_VALID_IRQ__##irq,
42+
#if defined(MICRO_FAMILY_SF32LB)
43+
# include "irq_sf32lb.def"
44+
#else
45+
# error need IRQ table for new micro family
46+
#endif
47+
#undef IRQ_DEF
48+
};
49+
3950
//! Creates a trampoline to the interrupt handler defined within the driver
4051
#define IRQ_MAP(irq, handler, device) \
4152
void irq##_IRQHandler(void) { \

‎src/fw/board/boards/board_em_lb525.c‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,4 +15,27 @@
1515
*/
1616

1717
#include "board/board.h"
18+
#include "drivers/sf32lb/uart_definitions.h"
1819

20+
static UARTDeviceState s_dbg_uart_state;
21+
static UART_HandleTypeDef s_dbg_uart_handle = {.Instance = USART3,
22+
.Init = {
23+
.WordLength = UART_WORDLENGTH_8B,
24+
.StopBits = UART_STOPBITS_1,
25+
.Parity = UART_PARITY_NONE,
26+
.HwFlowCtl = UART_HWCONTROL_NONE,
27+
.OverSampling = UART_OVERSAMPLING_16,
28+
}};
29+
static DMA_HandleTypeDef s_dbg_uart_rx_dma_handle = {
30+
.Instance = DMA1_Channel1,
31+
};
32+
static UARTDevice DBG_UART_DEVICE = {.state = &s_dbg_uart_state,
33+
.tx_gpio = PAD_PA20,
34+
.rx_gpio = PAD_PA27, // TODO: Setting GPIOs to actual values
35+
.periph = &s_dbg_uart_handle,
36+
.rx_dma = &s_dbg_uart_rx_dma_handle,
37+
.irq_priority = 1};
38+
UARTDevice *const DBG_UART = &DBG_UART_DEVICE;
39+
IRQ_MAP(USART3, uart_irq_handler, DBG_UART);
40+
41+
void DMAC1_CH1_IRQHandler(void) { HAL_DMA_IRQHandler(&s_dbg_uart_rx_dma_handle); }

‎src/fw/irq_sf32lb.def‎

Lines changed: 96 additions & 96 deletions
Original file line numberDiff line numberDiff line change
@@ -1,99 +1,99 @@
1-
IRQ_DEF(0, AON_IRQHandler) // Interrupt 0
1+
IRQ_DEF(0, AON) // Interrupt 0
22
IRQ_DEF(1, ble_isr) // Interrupt 1
3-
IRQ_DEF(2, DMAC2_CH1_IRQHandler) // Interrupt 2
4-
IRQ_DEF(3, DMAC2_CH2_IRQHandler) // Interrupt 3
5-
IRQ_DEF(4, DMAC2_CH3_IRQHandler) // Interrupt 4
6-
IRQ_DEF(5, DMAC2_CH4_IRQHandler) // Interrupt 5
7-
IRQ_DEF(6, DMAC2_CH5_IRQHandler) // Interrupt 6
8-
IRQ_DEF(7, DMAC2_CH6_IRQHandler) // Interrupt 7
9-
IRQ_DEF(8, DMAC2_CH7_IRQHandler) // Interrupt 8
10-
IRQ_DEF(9, DMAC2_CH8_IRQHandler) // Interrupt 9
11-
IRQ_DEF(10, PATCH_IRQHandler) // Interrupt 10
3+
IRQ_DEF(2, DMAC2_CH1) // Interrupt 2
4+
IRQ_DEF(3, DMAC2_CH2) // Interrupt 3
5+
IRQ_DEF(4, DMAC2_CH3) // Interrupt 4
6+
IRQ_DEF(5, DMAC2_CH4) // Interrupt 5
7+
IRQ_DEF(6, DMAC2_CH5) // Interrupt 6
8+
IRQ_DEF(7, DMAC2_CH6) // Interrupt 7
9+
IRQ_DEF(8, DMAC2_CH7) // Interrupt 8
10+
IRQ_DEF(9, DMAC2_CH8) // Interrupt 9
11+
IRQ_DEF(10, PATCH) // Interrupt 10
1212
IRQ_DEF(11, dm_isr) // Interrupt 11
13-
IRQ_DEF(12, USART4_IRQHandler) // Interrupt 12
14-
IRQ_DEF(13, USART5_IRQHandler) // Interrupt 13
15-
IRQ_DEF(14, SECU2_IRQHandler) // Interrupt 14
13+
IRQ_DEF(12, USART4) // Interrupt 12
14+
IRQ_DEF(13, USART5) // Interrupt 13
15+
IRQ_DEF(14, SECU2) // Interrupt 14
1616
IRQ_DEF(15, bt_isr) // Interrupt 15
17-
IRQ_DEF(16, BTIM3_IRQHandler) // Interrupt 16
18-
IRQ_DEF(17, BTIM4_IRQHandler) // Interrupt 17
19-
IRQ_DEF(18, PTC2_IRQHandler) // Interrupt 18
20-
IRQ_DEF(19, LPTIM3_IRQHandler) // Interrupt 19
21-
IRQ_DEF(20, GPIO2_IRQHandler) // Interrupt 20
22-
IRQ_DEF(21, HPSYS0_IRQHandler) // Interrupt 21
23-
IRQ_DEF(22, HPSYS1_IRQHandler) // Interrupt 22
24-
IRQ_DEF(23, Interrupt23_IRQHandler) // Interrupt 23
25-
IRQ_DEF(24, Interrupt24_IRQHandler) // Interrupt 24
26-
IRQ_DEF(25, Interrupt25_IRQHandler) // Interrupt 25
27-
IRQ_DEF(26, Interrupt26_IRQHandler) // Interrupt 26
28-
IRQ_DEF(27, Interrupt27_IRQHandler) // Interrupt 27
29-
IRQ_DEF(28, Interrupt28_IRQHandler) // Interrupt 28
30-
IRQ_DEF(29, Interrupt29_IRQHandler) // Interrupt 29
31-
IRQ_DEF(30, Interrupt30_IRQHandler) // Interrupt 30
32-
IRQ_DEF(31, Interrupt31_IRQHandler) // Interrupt 31
33-
IRQ_DEF(32, Interrupt32_IRQHandler) // Interrupt 32
34-
IRQ_DEF(33, Interrupt33_IRQHandler) // Interrupt 33
35-
IRQ_DEF(34, Interrupt34_IRQHandler) // Interrupt 34
36-
IRQ_DEF(35, Interrupt35_IRQHandler) // Interrupt 35
37-
IRQ_DEF(36, Interrupt36_IRQHandler) // Interrupt 36
38-
IRQ_DEF(37, Interrupt37_IRQHandler) // Interrupt 37
39-
IRQ_DEF(38, Interrupt38_IRQHandler) // Interrupt 38
40-
IRQ_DEF(39, Interrupt39_IRQHandler) // Interrupt 39
41-
IRQ_DEF(40, Interrupt40_IRQHandler) // Interrupt 40
42-
IRQ_DEF(41, Interrupt41_IRQHandler) // Interrupt 41
43-
IRQ_DEF(42, Interrupt42_IRQHandler) // Interrupt 42
44-
IRQ_DEF(43, Interrupt43_IRQHandler) // Interrupt 43
45-
IRQ_DEF(44, Interrupt44_IRQHandler) // Interrupt 44
46-
IRQ_DEF(45, Interrupt45_IRQHandler) // Interrupt 45
47-
IRQ_DEF(46, LPTIM1_IRQHandler) // Interrupt 46
48-
IRQ_DEF(47, LPTIM2_IRQHandler) // Interrupt 47
49-
IRQ_DEF(48, PMUC_IRQHandler) // Interrupt 48
50-
IRQ_DEF(49, RTC_IRQHandler) // Interrupt 49
51-
IRQ_DEF(50, DMAC1_CH1_IRQHandler) // Interrupt 50
52-
IRQ_DEF(51, DMAC1_CH2_IRQHandler) // Interrupt 51
53-
IRQ_DEF(52, DMAC1_CH3_IRQHandler) // Interrupt 52
54-
IRQ_DEF(53, DMAC1_CH4_IRQHandler) // Interrupt 53
55-
IRQ_DEF(54, DMAC1_CH5_IRQHandler) // Interrupt 54
56-
IRQ_DEF(55, DMAC1_CH6_IRQHandler) // Interrupt 55
57-
IRQ_DEF(56, DMAC1_CH7_IRQHandler) // Interrupt 56
58-
IRQ_DEF(57, DMAC1_CH8_IRQHandler) // Interrupt 57
59-
IRQ_DEF(58, LCPU2HCPU_IRQHandler) // Interrupt 58
60-
IRQ_DEF(59, USART1_IRQHandler) // Interrupt 59
61-
IRQ_DEF(60, SPI1_IRQHandler) // Interrupt 60
62-
IRQ_DEF(61, I2C1_IRQHandler) // Interrupt 61
63-
IRQ_DEF(62, EPIC_IRQHandler) // Interrupt 62
64-
IRQ_DEF(63, LCDC1_IRQHandler) // Interrupt 63
65-
IRQ_DEF(64, I2S1_IRQHandler) // Interrupt 64
66-
IRQ_DEF(65, GPADC_IRQHandler) // Interrupt 65
67-
IRQ_DEF(66, EFUSEC_IRQHandler) // Interrupt 66
68-
IRQ_DEF(67, AES_IRQHandler) // Interrupt 67
69-
IRQ_DEF(68, PTC1_IRQHandler) // Interrupt 68
70-
IRQ_DEF(69, TRNG_IRQHandler) // Interrupt 69
71-
IRQ_DEF(70, GPTIM1_IRQHandler) // Interrupt 70
72-
IRQ_DEF(71, GPTIM2_IRQHandler) // Interrupt 71
73-
IRQ_DEF(72, BTIM1_IRQHandler) // Interrupt 72
74-
IRQ_DEF(73, BTIM2_IRQHandler) // Interrupt 73
75-
IRQ_DEF(74, USART2_IRQHandler) // Interrupt 74
76-
IRQ_DEF(75, SPI2_IRQHandler) // Interrupt 75
77-
IRQ_DEF(76, I2C2_IRQHandler) // Interrupt 76
78-
IRQ_DEF(77, EXTDMA_IRQHandler) // Interrupt 77
79-
IRQ_DEF(78, I2C4_IRQHandler) // Interrupt 78
80-
IRQ_DEF(79, SDMMC1_IRQHandler) // Interrupt 79
81-
IRQ_DEF(80, Interrupt80_IRQHandler) // Interrupt 80
82-
IRQ_DEF(81, Interrupt81_IRQHandler) // Interrupt 81
83-
IRQ_DEF(82, PDM1_IRQHandler) // Interrupt 82
84-
IRQ_DEF(83, Interrupt83_IRQHandler) // Interrupt 83
85-
IRQ_DEF(84, GPIO1_IRQHandler) // Interrupt 84
86-
IRQ_DEF(85, QSPI1_IRQHandler) // Interrupt 85
87-
IRQ_DEF(86, QSPI2_IRQHandler) // Interrupt 86
88-
IRQ_DEF(87, Interrupt87_IRQHandler) // Interrupt 87
89-
IRQ_DEF(88, Interrupt88_IRQHandler) // Interrupt 88
90-
IRQ_DEF(89, EZIP_IRQHandler) // Interrupt 89
91-
IRQ_DEF(90, AUDPRC_IRQHandler) // Interrupt 90
92-
IRQ_DEF(91, TSEN_IRQHandler) // Interrupt 91
93-
IRQ_DEF(92, USBC_IRQHandler) // Interrupt 92
94-
IRQ_DEF(93, I2C3_IRQHandler) // Interrupt 93
95-
IRQ_DEF(94, ATIM1_IRQHandler) // Interrupt 94
96-
IRQ_DEF(95, USART3_IRQHandler) // Interrupt 95
97-
IRQ_DEF(96, AUD_HP_IRQHandler) // Interrupt 96
98-
IRQ_DEF(97, Interrupt97_IRQHandler) // Interrupt 97
99-
IRQ_DEF(98, SECU1_IRQHandler) // Interrupt 98
17+
IRQ_DEF(16, BTIM3) // Interrupt 16
18+
IRQ_DEF(17, BTIM4) // Interrupt 17
19+
IRQ_DEF(18, PTC2) // Interrupt 18
20+
IRQ_DEF(19, LPTIM3) // Interrupt 19
21+
IRQ_DEF(20, GPIO2) // Interrupt 20
22+
IRQ_DEF(21, HPSYS0) // Interrupt 21
23+
IRQ_DEF(22, HPSYS1) // Interrupt 22
24+
IRQ_DEF(23, Interrupt23) // Interrupt 23
25+
IRQ_DEF(24, Interrupt24) // Interrupt 24
26+
IRQ_DEF(25, Interrupt25) // Interrupt 25
27+
IRQ_DEF(26, Interrupt26) // Interrupt 26
28+
IRQ_DEF(27, Interrupt27) // Interrupt 27
29+
IRQ_DEF(28, Interrupt28) // Interrupt 28
30+
IRQ_DEF(29, Interrupt29) // Interrupt 29
31+
IRQ_DEF(30, Interrupt30) // Interrupt 30
32+
IRQ_DEF(31, Interrupt31) // Interrupt 31
33+
IRQ_DEF(32, Interrupt32) // Interrupt 32
34+
IRQ_DEF(33, Interrupt33) // Interrupt 33
35+
IRQ_DEF(34, Interrupt34) // Interrupt 34
36+
IRQ_DEF(35, Interrupt35) // Interrupt 35
37+
IRQ_DEF(36, Interrupt36) // Interrupt 36
38+
IRQ_DEF(37, Interrupt37) // Interrupt 37
39+
IRQ_DEF(38, Interrupt38) // Interrupt 38
40+
IRQ_DEF(39, Interrupt39) // Interrupt 39
41+
IRQ_DEF(40, Interrupt40) // Interrupt 40
42+
IRQ_DEF(41, Interrupt41) // Interrupt 41
43+
IRQ_DEF(42, Interrupt42) // Interrupt 42
44+
IRQ_DEF(43, Interrupt43) // Interrupt 43
45+
IRQ_DEF(44, Interrupt44) // Interrupt 44
46+
IRQ_DEF(45, Interrupt45) // Interrupt 45
47+
IRQ_DEF(46, LPTIM1) // Interrupt 46
48+
IRQ_DEF(47, LPTIM2) // Interrupt 47
49+
IRQ_DEF(48, PMUC) // Interrupt 48
50+
IRQ_DEF(49, RTC) // Interrupt 49
51+
IRQ_DEF(50, DMAC1_CH1) // Interrupt 50
52+
IRQ_DEF(51, DMAC1_CH2) // Interrupt 51
53+
IRQ_DEF(52, DMAC1_CH3) // Interrupt 52
54+
IRQ_DEF(53, DMAC1_CH4) // Interrupt 53
55+
IRQ_DEF(54, DMAC1_CH5) // Interrupt 54
56+
IRQ_DEF(55, DMAC1_CH6) // Interrupt 55
57+
IRQ_DEF(56, DMAC1_CH7) // Interrupt 56
58+
IRQ_DEF(57, DMAC1_CH8) // Interrupt 57
59+
IRQ_DEF(58, LCPU2HCPU) // Interrupt 58
60+
IRQ_DEF(59, USART1) // Interrupt 59
61+
IRQ_DEF(60, SPI1) // Interrupt 60
62+
IRQ_DEF(61, I2C1) // Interrupt 61
63+
IRQ_DEF(62, EPIC) // Interrupt 62
64+
IRQ_DEF(63, LCDC1) // Interrupt 63
65+
IRQ_DEF(64, I2S1) // Interrupt 64
66+
IRQ_DEF(65, GPADC) // Interrupt 65
67+
IRQ_DEF(66, EFUSEC) // Interrupt 66
68+
IRQ_DEF(67, AES) // Interrupt 67
69+
IRQ_DEF(68, PTC1) // Interrupt 68
70+
IRQ_DEF(69, TRNG) // Interrupt 69
71+
IRQ_DEF(70, GPTIM1) // Interrupt 70
72+
IRQ_DEF(71, GPTIM2) // Interrupt 71
73+
IRQ_DEF(72, BTIM1) // Interrupt 72
74+
IRQ_DEF(73, BTIM2) // Interrupt 73
75+
IRQ_DEF(74, USART2) // Interrupt 74
76+
IRQ_DEF(75, SPI2) // Interrupt 75
77+
IRQ_DEF(76, I2C2) // Interrupt 76
78+
IRQ_DEF(77, EXTDMA) // Interrupt 77
79+
IRQ_DEF(78, I2C4) // Interrupt 78
80+
IRQ_DEF(79, SDMMC1) // Interrupt 79
81+
IRQ_DEF(80, Interrupt80) // Interrupt 80
82+
IRQ_DEF(81, Interrupt81) // Interrupt 81
83+
IRQ_DEF(82, PDM1) // Interrupt 82
84+
IRQ_DEF(83, Interrupt83) // Interrupt 83
85+
IRQ_DEF(84, GPIO1) // Interrupt 84
86+
IRQ_DEF(85, QSPI1) // Interrupt 85
87+
IRQ_DEF(86, QSPI2) // Interrupt 86
88+
IRQ_DEF(87, Interrupt87) // Interrupt 87
89+
IRQ_DEF(88, Interrupt88) // Interrupt 88
90+
IRQ_DEF(89, EZIP) // Interrupt 89
91+
IRQ_DEF(90, AUDPRC) // Interrupt 90
92+
IRQ_DEF(91, TSEN) // Interrupt 91
93+
IRQ_DEF(92, USBC) // Interrupt 92
94+
IRQ_DEF(93, I2C3) // Interrupt 93
95+
IRQ_DEF(94, ATIM1) // Interrupt 94
96+
IRQ_DEF(95, USART3) // Interrupt 95
97+
IRQ_DEF(96, AUD_HP) // Interrupt 96
98+
IRQ_DEF(97, Interrupt97) // Interrupt 97
99+
IRQ_DEF(98, SECU1) // Interrupt 98

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