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Merge pull request #66 from ThomasPluck/main
Feature: VLSIR-based Netlisting Support
2 parents 736f5f1 + fe0e02b commit 9338990

211 files changed

Lines changed: 13762 additions & 148 deletions

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.gitignore

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@@ -16,7 +16,7 @@ tests/gds_ref/*.oas
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docs/components.rst
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docs/components_plot.rst
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.vscode/
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.claude/
2020

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# C extensions
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*.so

.pre-commit-config.yaml

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@@ -5,7 +5,9 @@ repos:
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- id: check-yaml
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exclude: ^(conda\.recipe/meta\.yaml|conda_build/templates/.*\.yaml|docs/click/meta\.yaml|conda/meta\.yaml|conda/construct.yaml|.*\.pic\.yml|conda/constructor/Miniforge3/construct.yaml)
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- id: end-of-file-fixer
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exclude: ^(.*\.lib|.spiceinit)$
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- id: trailing-whitespace
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exclude: ^(.*\.lib|.spiceinit)$
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- repo: https://github.com/kynan/nbstripout
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rev: 0.8.1
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hooks:
@@ -17,7 +19,8 @@ repos:
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- id: codespell
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additional_dependencies:
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- tomli
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exclude: ^(pyproject\.toml|ihp/layers\.yaml|ihp/cells2/ihp_pycell/.*|cni/.*)$
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args: [--ignore-words-list=te, fpr, nd, donot, schem, contnet, Contnet, rady, INOUT]
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exclude: ^(pyproject\.toml|ihp/models/.*|ihp/layers\.yaml|ihp/cells2/ihp_pycell/.*|cni/.*)$
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- repo: https://github.com/astral-sh/ruff-pre-commit
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rev: "v0.12.11"
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hooks:

docs/_config.yml

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@@ -4,6 +4,7 @@ title: IHP
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author: IHP
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logo: logo.png
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# Force re-execution of notebooks on each build.
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# See https://jupyterbook.org/content/execute.html
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execute:
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execute_notebooks: cache
@@ -13,18 +14,21 @@ latex:
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latex_engine: pdflatex # one of 'pdflatex', 'xelatex' (recommended for unicode), 'luatex', 'platex', 'uplatex'
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use_jupyterbook_latex: true # use sphinx-jupyterbook-latex for pdf builds as default
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# Add a bibtex file so that we can create citations
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html:
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home_page_in_navbar: true
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use_edit_page_button: true
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use_repository_button: true
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use_issues_button: true
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baseurl: https://github.com/gdsfactory/ihp
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# Information about where the book exists on the web
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repository:
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url: https://github.com/gdsfactory/ihp
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path_to_book: docs # Optional path to your book, relative to the repository root
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branch: main # Which branch of the repository should be used when creating links (optional)
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# launch_buttons:
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# notebook_interface: jupyterlab
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# colab_url: "https://colab.research.google.com"
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sphinx:

ihp/cells/__init__.py

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@@ -7,6 +7,7 @@
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from .fixed import *
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from .inductors import *
99
from .passives import *
10+
from .primitives import *
1011
from .resistors import *
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from .text import *
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from .transistors import *

ihp/cells/antennas.py

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Original file line numberDiff line numberDiff line change
@@ -232,6 +232,16 @@ def dantenna(
232232
)
233233
).move((-diods_over, -diods_over))
234234

235+
# VLSIR Simulation Metadata
236+
c.info["vlsir"] = {
237+
"model": "dantenna",
238+
"spice_type": "SUBCKT",
239+
"spice_lib": "diodes.lib",
240+
"port_order": ["1", "2"],
241+
"port_map": {}, # No physical ports defined on component
242+
"params": {"w": width * 1e-6, "l": length * 1e-6},
243+
}
244+
235245
return c
236246

237247

@@ -342,6 +352,16 @@ def dpantenna(
342352
)
343353
).move((-NW_c, -NW_c))
344354

355+
# VLSIR Simulation Metadata
356+
c.info["vlsir"] = {
357+
"model": "dpantenna",
358+
"spice_type": "SUBCKT",
359+
"spice_lib": "diodes.lib",
360+
"port_order": ["1", "2"],
361+
"port_map": {}, # No physical ports defined on component
362+
"params": {"w": width * 1e-6, "l": length * 1e-6},
363+
}
364+
345365
return c
346366

347367

ihp/cells/bipolar.py

Lines changed: 22 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -266,14 +266,24 @@ def npn13G2(
266266
c.info["m"] = m
267267
c.info["type"] = "npn"
268268

269+
# VLSIR Simulation Metadata
270+
c.info["vlsir"] = {
271+
"model": model,
272+
"spice_type": "SUBCKT",
273+
"spice_lib": "sg13g2_hbt_mod.lib",
274+
"port_order": ["c", "b", "e"],
275+
"port_map": {"C": "c", "B": "b", "E": "e"},
276+
"params": {"we": emitter_width * 1e-6, "le": emitter_length * 1e-6, "m": m},
277+
}
278+
269279
return c
270280

271281

272282
@gf.cell
273283
def npn13G2L(
274284
emitter_width: float = 0.07,
275285
emitter_length: float = 1.26,
276-
model: str = "npn13G2L",
286+
model: str = "npn13G2l", # Lowercase l to match SPICE
277287
m: int = 1,
278288
layer_nwell: LayerSpec = "NWelldrawing",
279289
layer_pwell: LayerSpec = "PWelldrawing",
@@ -323,7 +333,7 @@ def npn13G2L(
323333
def npn13G2V(
324334
emitter_width: float = 0.12,
325335
emitter_length: float = 0.9,
326-
model: str = "npn13G2V",
336+
model: str = "npn13G2v", # lower-case v to match SPICE
327337
m: int = 1,
328338
layer_nwell: LayerSpec = "NWelldrawing",
329339
layer_pwell: LayerSpec = "PWelldrawing",
@@ -575,6 +585,16 @@ def pnpMPA(
575585
c.info["m"] = m
576586
c.info["type"] = "pnp"
577587

588+
# VLSIR Simulation Metadata
589+
c.info["vlsir"] = {
590+
"model": model,
591+
"spice_type": "SUBCKT",
592+
"spice_lib": "sg13g2_hbt_mod.lib",
593+
"port_order": ["c", "b", "e"],
594+
"port_map": {"C": "c", "B": "b", "E": "e"},
595+
"params": {"we": emitter_width * 1e-6, "le": emitter_length * 1e-6, "m": m},
596+
}
597+
578598
return c
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580600

ihp/cells/bjt_transistors.py

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Original file line numberDiff line numberDiff line change
@@ -715,6 +715,22 @@ def npn13G2(
715715
port_type="electrical",
716716
)
717717

718+
# VLSIR Simulation Metadata
719+
c.info["vlsir"] = {
720+
"model": "npn13G2",
721+
"spice_type": "SUBCKT",
722+
"spice_lib": "sg13g2_hbt_mod.lib",
723+
"port_order": ["c", "b", "e", "bn"],
724+
"params": {
725+
"Nx": Nx,
726+
"Ny": Ny,
727+
"we": emitter_width * 1e-6,
728+
"le": emitter_length * 1e-6,
729+
},
730+
}
731+
732+
# TODO: Extend to handle empoly, bipwin, cmet
733+
718734
return c
719735

720736

@@ -1265,6 +1281,18 @@ def npn13G2L(
12651281
),
12661282
)
12671283

1284+
# VLSIR Simulation Metadata
1285+
c.info["vlsir"] = {
1286+
"model": "npn13G2l",
1287+
"spice_type": "SUBCKT",
1288+
"spice_lib": "sg13g2_hbt_mod.lib",
1289+
"port_order": ["c", "b", "e", "bn"],
1290+
"params": {
1291+
"we": emitter_width * 1e-6,
1292+
"le": emitter_length * 1e-6,
1293+
},
1294+
}
1295+
12681296
return c
12691297

12701298

@@ -1836,6 +1864,18 @@ def npn13G2V(
18361864
),
18371865
)
18381866

1867+
# VLSIR Simulation Metadata
1868+
c.info["vlsir"] = {
1869+
"model": "npn13G2v",
1870+
"spice_type": "SUBCKT",
1871+
"spice_lib": "sg13g2_hbt_mod.lib",
1872+
"port_order": ["c", "b", "e", "bn"],
1873+
"params": {
1874+
"we": emitter_width * 1e-6,
1875+
"le": emitter_length * 1e-6,
1876+
},
1877+
}
1878+
18391879
return c
18401880

18411881

@@ -2371,6 +2411,14 @@ def pnpMPA(length: float = 2, width: float = 0.7) -> gf.Component:
23712411
port_type="electrical",
23722412
)
23732413

2414+
c.info["vlsir"] = {
2415+
"model": "pnpMPA",
2416+
"spice_type": "SUBCKT",
2417+
"spice_lib": "sg13g2_hbt_mod.lib",
2418+
"port_order": ["c", "b", "e"],
2419+
# TODO: Understand meaning of pnpMPA params
2420+
}
2421+
23742422
return c
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ihp/cells/bondpads.py

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@@ -100,6 +100,21 @@ def bondpad(
100100
c.info["shape"] = shape
101101
c.info["diameter"] = diameter
102102
c.info["top_metal"] = layer_top_metal
103+
104+
# VLSIR Simulation Metadata
105+
c.info["vlsir"] = {
106+
"model": "bondpad",
107+
"spice_type": "SUBCKT",
108+
"spice_lib": "sg13g2_bondpad.lib",
109+
"port_order": ["PAD"],
110+
"port_map": {"pad": "PAD"},
111+
"params": {
112+
"size": diameter * 1e-6,
113+
"shape": {"octagon": 0, "square": 1, "circle": 2}[shape],
114+
"padtype": 0, # TODO
115+
},
116+
}
117+
103118
return c
104119

105120

@@ -157,6 +172,8 @@ def bondpad_array(
157172
c.info["pad_pitch"] = pad_pitch
158173
c.info["pad_diameter"] = pad_diameter
159174

175+
# TODO: Bondpad array VLSIR Metadata
176+
160177
return c
161178

162179

ihp/cells/capacitors.py

Lines changed: 19 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -510,6 +510,16 @@ def cmim(
510510
c.info["length"] = length
511511
c.info["capacitance_fF"] = capacitance
512512
c.info["area_um2"] = width * length
513+
514+
# VLSIR simulation metadata
515+
c.info["vlsir"] = {
516+
"model": "cap_cmim",
517+
"spice_type": "SUBCKT",
518+
"spice_lib": "capacitors_mod.lib",
519+
"port_order": ["PLUS", "MINUS"],
520+
"params": {"w": width * 1e-6, "l": length * 1e-6},
521+
}
522+
513523
return c
514524

515525

@@ -681,7 +691,15 @@ def rfcmim(
681691
c.add_label(text="TIE_LOW", position=(tie.x, tie.y), layer=layer_metal1label)
682692
c.add_label(text="TIE_LOW", position=(tie.x, tie.y), layer=layer_text)
683693

684-
c.info["model"] = model
694+
# VLSIR simulation metadata
695+
c.info["vlsir"] = {
696+
"model": "cap_rfcmim",
697+
"spice_type": "SUBCKT",
698+
"spice_lib": "capacitors_mod.lib",
699+
"port_order": ["PLUS", "MINUS", "bn"],
700+
"port_map": {"PLUS": "PLUS", "MINUS": "MINUS"},
701+
"params": {"l": length * 1e-6, "w": width * 1e-6},
702+
}
685703

686704
return c
687705

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