Summary
The mim layer in the LayerStack (tech.py) lumps the MIM dielectric and the MIM top-plate metal into a single 0.19 µm LayerLevel made of sio2. This is fine for layout/DRC/3D-visualization, but it makes the MIM capacitor unusable for EM/electrostatic capacitance extraction — it under-predicts the cap density by ~7–8×.
Current definition
ihp/tech.py (v0.2.8):
# MIM capacitor - dielectric 40nm (TISMIM) + top plate 150nm (TMIMTOP)
# Sits on top of Metal5
mim=LayerLevel(
layer=LAYER.MIMdrawing,
thickness=0.04 + 0.15, # = 0.19 µm
material="sio2",
info={"mesh_order": 23},
),
The comment itself documents that this single block is really two physically distinct things:
- a 40 nm MIM dielectric (TISMIM) — the actual capacitor dielectric, a high-k nitride (≈ SiN, εᵣ ≈ 6.8–7.5), not SiO₂, and
- a 150 nm MIM top-plate metal (TMIMTOP) — a conductor, here modeled as dielectric.
What the official IHP-Open-PDK does
The authoritative EM cross-section sg13g2_for_EM.xs models these as two separate layers grown from the same MIM mask:
t_mimdiel = 0.04 # 40 nm MIM dielectric
mimdiel = mask(mask_MIM).grow(t_mimdiel)
t_mim = 0.15 # 150 nm MIM top-plate metal
mim = mask(mask_MIM).grow(t_mim)
t_vmim = t_topvia1 - t_mim - t_mimdiel
vmim = mask(mask_VMIM).grow(t_vmim)
So the canonical stack is: Metal5 → 40 nm dielectric → 150 nm top-plate metal → Vmim → TopMetal1. The single lumped sio2 block is what diverges from IHP's own EM reference.
Suggested fix
Split the single mim level into two LayerLevels (both can reference LAYER.MIMdrawing):
mim_diel=LayerLevel(
layer=LAYER.MIMdrawing,
thickness=0.04, # 40 nm MIM dielectric
zmin=z_m5_top,
material="sin", # high-k nitride, εᵣ ≈ 7.5
info={"mesh_order": 23},
),
mim_top=LayerLevel(
layer=LAYER.MIMdrawing,
thickness=0.15, # 150 nm MIM top-plate metal
zmin=z_m5_top + 0.04,
material="aluminum", # conductor (top electrode)
info={"mesh_order": 23},
),
This matches sg13g2_for_EM.xs, leaves the GDS/DRC footprint unchanged, and reproduces the 1.5 fF/µm² spec capacitance. The Vmim zmin/thickness already account for the 0.19 µm offset, so they remain consistent.
Summary
The
mimlayer in the LayerStack (tech.py) lumps the MIM dielectric and the MIM top-plate metal into a single 0.19 µmLayerLevelmade ofsio2. This is fine for layout/DRC/3D-visualization, but it makes the MIM capacitor unusable for EM/electrostatic capacitance extraction — it under-predicts the cap density by ~7–8×.Current definition
ihp/tech.py(v0.2.8):The comment itself documents that this single block is really two physically distinct things:
What the official IHP-Open-PDK does
The authoritative EM cross-section
sg13g2_for_EM.xsmodels these as two separate layers grown from the same MIM mask:So the canonical stack is: Metal5 → 40 nm dielectric → 150 nm top-plate metal → Vmim → TopMetal1. The single lumped
sio2block is what diverges from IHP's own EM reference.Suggested fix
Split the single
mimlevel into twoLayerLevels (both can referenceLAYER.MIMdrawing):This matches
sg13g2_for_EM.xs, leaves the GDS/DRC footprint unchanged, and reproduces the 1.5 fF/µm² spec capacitance. The Vmimzmin/thickness already account for the 0.19 µm offset, so they remain consistent.