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Things to do #8

@joamatab

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@joamatab

gdsfactory/gdsfactory#176

TODO

  • make PCells (see below)
  • add pyspice demos fir models and simulations
  • add notebooks with documentation
  • LVS. In LVS, the software will extract the fundamental components (e.g. diodes, transistors) based on the layout and compare it to the netlist
  • QRC extraction, or more accurately, RLCK parasitic elements. This is essential for RF circuits, otherwise, the simulation results are useless.
  • Customize main parametric components such as transistors, capacitors, diodes resistors, etc. Remember, those ready-made blocks you show in your video from Skywater are not very useful in this context as they are for automatic digital place and route. Once this is completed, a spice-compatible netlist is generated, and we can use ngspice and EEsim to display results etc.

Pcells to make

  • NMOS
  • transistors
  • capacitors
  • diodes
  • resistors

Maybe

  • openroad plugin. Invoke Yosis from gdsfactory

@proppy
@mithro
@danchitnis
@SkandanC

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