Skip to content

Commit aa87b3e

Browse files
Re-indent combine_assign
1 parent 7211045 commit aa87b3e

File tree

1 file changed

+8
-8
lines changed

1 file changed

+8
-8
lines changed

src/analyses/region.ml

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -143,14 +143,14 @@ struct
143143
match au with
144144
| `Lifted reg -> begin
145145
let old_regpart = man.global () in
146-
let regpart, reg = match lval with
147-
| None -> (old_regpart, reg)
148-
| Some lval -> Reg.assign lval (AddrOf (ReturnUtil.return_lval ())) (old_regpart, reg)
149-
in
150-
let regpart, reg = Reg.remove_vars [ReturnUtil.return_varinfo ()] (regpart, reg) in
151-
if not (RegPart.leq regpart old_regpart) then
152-
man.sideg () regpart;
153-
`Lifted reg
146+
let regpart, reg = match lval with
147+
| None -> (old_regpart, reg)
148+
| Some lval -> Reg.assign lval (AddrOf (ReturnUtil.return_lval ())) (old_regpart, reg)
149+
in
150+
let regpart, reg = Reg.remove_vars [ReturnUtil.return_varinfo ()] (regpart, reg) in
151+
if not (RegPart.leq regpart old_regpart) then
152+
man.sideg () regpart;
153+
`Lifted reg
154154
end
155155
| _ -> au
156156

0 commit comments

Comments
 (0)