cpu.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2021  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# Date created = 14:22:48 October 29, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEBA4F23C7
set_global_assignment -name TOP_LEVEL_ENTITY board
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13
set_global_assignment -name PROJECT_CREATION_TIME_DATE "MON MAY  5 11:54:18 2014"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1"
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCS64
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
set_global_assignment -name BOARD "DE0-CV Development Board"
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"

set_global_assignment -name VHDL_FILE rtl/attrs.vhdl 
set_global_assignment -name VHDL_FILE rtl/asm.vhdl
set_global_assignment -name VHDL_FILE rtl/alu/adder.vhdl
set_global_assignment -name VHDL_FILE rtl/alu/alu.vhdl
set_global_assignment -name VHDL_FILE rtl/reg/reg.vhdl
set_global_assignment -name VHDL_FILE rtl/reg/file.vhdl
set_global_assignment -name VHDL_FILE rtl/control.vhdl
set_global_assignment -name VHDL_FILE rtl/mem.vhdl
set_global_assignment -name VHDL_FILE rtl/cpu.vhdl
set_global_assignment -name VHDL_FILE rtl/hex.vhdl
set_global_assignment -name VHDL_FILE rtl/board.vhdl

set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

set_location_assignment PIN_U7 -to int

# set_location_assignment PIN_W9 -to KEY[1]
# set_location_assignment PIN_M7 -to KEY[2]
# set_location_assignment PIN_M6 -to KEY[3]

set_location_assignment PIN_P22 -to rst

set_location_assignment PIN_U13 -to input[0]
set_location_assignment PIN_V13 -to input[1]
set_location_assignment PIN_T13 -to input[2]
set_location_assignment PIN_T12 -to input[3]
set_location_assignment PIN_AA15 -to input[4]
set_location_assignment PIN_AB15 -to input[5]
set_location_assignment PIN_AA14 -to input[6]
set_location_assignment PIN_AA13 -to input[7]

# set_location_assignment PIN_AB13 -to SW[8]
# set_location_assignment PIN_AB12 -to SW[9]

set_location_assignment PIN_AA2 -to output[0]
set_location_assignment PIN_AA1 -to output[1]
set_location_assignment PIN_W2 -to output[2]
set_location_assignment PIN_Y3 -to output[3]
set_location_assignment PIN_N2 -to output[4]
set_location_assignment PIN_N1 -to output[5]
set_location_assignment PIN_U2 -to output[6]
set_location_assignment PIN_U1 -to output[7]

# set_location_assignment PIN_L2 -to LEDR[8]
# set_location_assignment PIN_L1 -to LEDR[9]

set_location_assignment PIN_U21 -to hex_out[0][0]
set_location_assignment PIN_V21 -to hex_out[0][1]
set_location_assignment PIN_W22 -to hex_out[0][2]
set_location_assignment PIN_W21 -to hex_out[0][3]
set_location_assignment PIN_Y22 -to hex_out[0][4]
set_location_assignment PIN_Y21 -to hex_out[0][5]
set_location_assignment PIN_AA22 -to hex_out[0][6]

set_location_assignment PIN_AA20 -to hex_out[1][0]
set_location_assignment PIN_AB20 -to hex_out[1][1]
set_location_assignment PIN_AA19 -to hex_out[1][2]
set_location_assignment PIN_AA18 -to hex_out[1][3]
set_location_assignment PIN_AB18 -to hex_out[1][4]
set_location_assignment PIN_AA17 -to hex_out[1][5]
set_location_assignment PIN_U22 -to hex_out[1][6]

set_location_assignment PIN_Y19 -to hex_in[0][0]
set_location_assignment PIN_AB17 -to hex_in[0][1]
set_location_assignment PIN_AA10 -to hex_in[0][2]
set_location_assignment PIN_Y14 -to hex_in[0][3]
set_location_assignment PIN_V14 -to hex_in[0][4]
set_location_assignment PIN_AB22 -to hex_in[0][5]
set_location_assignment PIN_AB21 -to hex_in[0][6]

set_location_assignment PIN_Y16 -to hex_in[1][0]
set_location_assignment PIN_W16 -to hex_in[1][1]
set_location_assignment PIN_Y17 -to hex_in[1][2]
set_location_assignment PIN_V16 -to hex_in[1][3]
set_location_assignment PIN_U17 -to hex_in[1][4]
set_location_assignment PIN_V18 -to hex_in[1][5]
set_location_assignment PIN_V19 -to hex_in[1][6]

# set_location_assignment PIN_U20 -to HEX[4][0]
# set_location_assignment PIN_Y20 -to HEX[4][1]
# set_location_assignment PIN_V20 -to HEX[4][2]
# set_location_assignment PIN_U16 -to HEX[4][3]
# set_location_assignment PIN_U15 -to HEX[4][4]
# set_location_assignment PIN_Y15 -to HEX[4][5]
# set_location_assignment PIN_P9 -to HEX[4][6]
# set_location_assignment PIN_N9 -to HEX[5][0]
# set_location_assignment PIN_M8 -to HEX[5][1]
# set_location_assignment PIN_T14 -to HEX[5][2]
# set_location_assignment PIN_P14 -to HEX[5][3]
# set_location_assignment PIN_C1 -to HEX[5][4]
# set_location_assignment PIN_C2 -to HEX[5][5]
# set_location_assignment PIN_W19 -to HEX[5][6]

set_location_assignment PIN_M9 -to clk

# set_location_assignment PIN_H13 -to CLOCK[1]
# set_location_assignment PIN_E10 -to CLOCK[2]
# set_location_assignment PIN_V15 -to CLOCK[3]

set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top