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Incorrect Address width in descriptions for 3 SRAM modules #10

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@shaos

Description

@shaos

Expected Behavior

gf180mcu_fd_ip_sram__sram256x8m8wm1 should have A[7:0]
gf180mcu_fd_ip_sram__sram512x8m8wm1 should have A[8:0]
gf180mcu_fd_ip_sram__sram64x8m8wm1 should have A[5:0]

Actual Behavior

in documentation all sram modules have A[6:0] as address description so it's correct only for sram128x8 (this is only documentation issue - in verilog everything looks ok)

Steps to Reproduce the Problem

Look into these 3 CSV files:
cells/gf180mcu_fd_ip_sram__sram256x8m8wm1/specs/1_pins_desc.csv:A[6:0],Input,"Address Input. This Address input port is used to
cells/gf180mcu_fd_ip_sram__sram512x8m8wm1/specs/1_pins_desc.csv:A[6:0],Input,"Address Input. This Address input port is used to
cells/gf180mcu_fd_ip_sram__sram64x8m8wm1/specs/1_pins_desc.csv:A[6:0],Input,"Address Input. This Address input port is used to

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  • Platform:

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