This repository was archived by the owner on Jan 10, 2023. It is now read-only.
This repository was archived by the owner on Jan 10, 2023. It is now read-only.
Check the verilog simulation files work #11
Description
- Check with
USE_POWER_PINSenabled. - Check with
USE_POWER_PINSdisable. - Functional vs Behavioral models?
- Run the XXX.tb.v files?
- Check for syntax errors using iverilog (-Wall)