diff --git a/pkg/compiler/types.go b/pkg/compiler/types.go index 86876b69d809..063b9f06f090 100644 --- a/pkg/compiler/types.go +++ b/pkg/compiler/types.go @@ -661,7 +661,7 @@ func genTextType(t *ast.Type) prog.TextKind { case "ppc64": return prog.TextPpc64 case "riscv64": - return prog.TextTarget + return prog.TextRiscv64 default: panic(fmt.Sprintf("unknown text type %q", t.Ident)) } diff --git a/pkg/ifuzz/ifuzz.go b/pkg/ifuzz/ifuzz.go index d33717d5d572..9d37d140ff9c 100644 --- a/pkg/ifuzz/ifuzz.go +++ b/pkg/ifuzz/ifuzz.go @@ -9,6 +9,7 @@ import ( _ "github.com/google/syzkaller/pkg/ifuzz/arm64/generated" // pull in generated instruction descriptions "github.com/google/syzkaller/pkg/ifuzz/iset" _ "github.com/google/syzkaller/pkg/ifuzz/powerpc/generated" // pull in generated instruction descriptions + _ "github.com/google/syzkaller/pkg/ifuzz/riscv64/generated" // pull in generated instruction descriptions _ "github.com/google/syzkaller/pkg/ifuzz/x86/generated" // pull in generated instruction descriptions ) @@ -22,6 +23,7 @@ const ( ArchX86 = iset.ArchX86 ArchPowerPC = iset.ArchPowerPC ArchArm64 = iset.ArchArm64 + ArchRiscv64 = iset.ArchRiscv64 ModeLong64 = iset.ModeLong64 ModeProt32 = iset.ModeProt32 ModeProt16 = iset.ModeProt16 diff --git a/pkg/ifuzz/ifuzz_test.go b/pkg/ifuzz/ifuzz_test.go index cd87b7355c73..5ee1da4c7a84 100644 --- a/pkg/ifuzz/ifuzz_test.go +++ b/pkg/ifuzz/ifuzz_test.go @@ -12,7 +12,7 @@ import ( "github.com/google/syzkaller/pkg/testutil" ) -var allArches = []string{ArchX86, ArchPowerPC, ArchArm64} +var allArches = []string{ArchX86, ArchPowerPC, ArchArm64, ArchRiscv64} func TestMode(t *testing.T) { for _, arch := range allArches { @@ -139,6 +139,10 @@ func testGenerate(t *testing.T, arch string) { Exec: true, Len: repeat, } + if arch == ArchRiscv64 { + cfg.Priv = false + cfg.Exec = false + } text := Generate(cfg, r) for len(text) != 0 { size, err := insnset.Decode(mode, text) diff --git a/pkg/ifuzz/iset/iset.go b/pkg/ifuzz/iset/iset.go index 83afe67c1927..753aa9a6cc01 100644 --- a/pkg/ifuzz/iset/iset.go +++ b/pkg/ifuzz/iset/iset.go @@ -12,6 +12,7 @@ const ( ArchX86 = "x86" ArchPowerPC = "powerpc" ArchArm64 = "arm64" + ArchRiscv64 = "riscv64" ) var Arches = make(map[string]InsnSet) diff --git a/pkg/ifuzz/riscv64/gen/gen.go b/pkg/ifuzz/riscv64/gen/gen.go new file mode 100644 index 000000000000..6de49072e515 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/gen.go @@ -0,0 +1,199 @@ +// Copyright 2026 syzkaller project authors. All rights reserved. +// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file. + +// gen generates riscv64 instruction tables from riscv-unified-db YAML. +// https://github.com/riscv-software-src/riscv-unified-db/tree/main/spec/std/isa/inst +package main + +import ( + "bytes" + "fmt" + "io/fs" + "os" + "path/filepath" + "strings" + + "gopkg.in/yaml.v3" + + "github.com/google/syzkaller/pkg/ifuzz/riscv64" + "github.com/google/syzkaller/pkg/osutil" + "github.com/google/syzkaller/pkg/serializer" + "github.com/google/syzkaller/pkg/tool" +) + +type instYAML struct { + Kind string `yaml:"kind"` + Name string `yaml:"name"` + Encoding struct { + Match string `yaml:"match"` + Variables []struct { + Name string `yaml:"name"` + Location string `yaml:"location"` // e.g. "24-20" + } `yaml:"variables"` + } `yaml:"encoding"` + Access struct { + U string `yaml:"u"` + VU string `yaml:"vu"` + } `yaml:"access"` +} + +func main() { + if len(os.Args) != 3 { + tool.Failf("usage: go run gen.go ") + } + root := os.Args[1] + outFile := os.Args[2] + + insns := []*riscv64.Insn{} + + err := filepath.WalkDir(root, func(path string, d fs.DirEntry, err error) error { + if err != nil { + return err + } + if d.IsDir() || !strings.HasSuffix(path, ".yaml") { + return nil + } + + data, err := os.ReadFile(path) + if err != nil { + return nil + } + + var inst instYAML + if err := yaml.Unmarshal(data, &inst); err != nil { + return nil + } + if inst.Kind != "instruction" { + return nil + } + + match := inst.Encoding.Match + if len(match) != 32 { + return nil + } + + insn, ok := buildInsn(inst) + if ok { + insns = append(insns, insn) + } + return nil + }) + if err != nil { + tool.Fail(err) + } + + var out bytes.Buffer + fmt.Fprintf(&out, `// Code generated by pkg/ifuzz/riscv64/gen. DO NOT EDIT. + +// go:build !codeanalysis + +package generated + +import ( + . "github.com/google/syzkaller/pkg/ifuzz/riscv64" +) + +func init() { + Register(insns_riscv64) +} + +var insns_riscv64 = +`) + serializer.Write(&out, insns) + + if err := osutil.WriteFileAtomically(outFile, out.Bytes()); err != nil { + tool.Fail(err) + } + + fmt.Fprintf(os.Stderr, "generated %d instructions\n", len(insns)) +} + +func buildInsn(inst instYAML) (*riscv64.Insn, bool) { + match := inst.Encoding.Match + + var opcode uint32 + var mask uint32 + + for i, ch := range match { + bit := uint(31 - i) + switch ch { + case '0': + mask |= 1 << bit + case '1': + mask |= 1 << bit + opcode |= 1 << bit + case '-': + default: + return nil, false + } + } + + fields := []riscv64.InsnField{} + for _, v := range inst.Encoding.Variables { + subFields, ok := parseLocations(v.Name, v.Location) + if !ok { + return nil, false + } + fields = append(fields, subFields...) + } + + priv := inst.Access.U == "never" || inst.Access.VU == "never" + + return &riscv64.Insn{ + Name: inst.Name, + OpcodeMask: mask, + Opcode: opcode, + Fields: fields, + AsUInt32: opcode, + Generator: nil, + Priv: priv, + }, true +} + +func parseLocations(name, loc string) ([]riscv64.InsnField, bool) { + // Support multiple ranges separated by '|', e.g.: + // "31-25|11-7" + ranges := strings.Split(loc, "|") + fields := make([]riscv64.InsnField, 0, len(ranges)) + + for _, r := range ranges { + start, length, hi, lo, ok := parseRange(r) + if !ok { + return nil, false + } + + fieldName := name + if len(ranges) > 1 { + fieldName = fmt.Sprintf("%s_%d_%d", name, hi, lo) + } + + fields = append(fields, riscv64.InsnField{ + Name: fieldName, + Start: start, + Length: length, + }) + } + + return fields, true +} + +func parseRange(r string) (start, length, hi, lo uint, ok bool) { + parts := strings.Split(r, "-") + if len(parts) != 2 { + return 0, 0, 0, 0, false + } + + if _, err := fmt.Sscanf(parts[0], "%d", &hi); err != nil { + return 0, 0, 0, 0, false + } + if _, err := fmt.Sscanf(parts[1], "%d", &lo); err != nil { + return 0, 0, 0, 0, false + } + if hi < lo { + return 0, 0, 0, 0, false + } + + start = hi + length = hi - lo + 1 + return start, length, hi, lo, true +} diff --git a/pkg/ifuzz/riscv64/gen/inst/B/andn.yaml b/pkg/ifuzz/riscv64/gen/inst/B/andn.yaml new file mode 100644 index 000000000000..4967944ea6e3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/andn.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: andn +long_name: AND with inverted operand +description: | + Performs the bitwise logical AND operation between `xs1` and the + bitwise inversion of `xs2`. +definedBy: + extension: + anyOf: + - name: Zbb + - name: Zbkb +assembly: xd, xs1, xs2 +format: + $inherits: + - inst_subtype/R/R-x.yaml#/data + opcodes: + funct7: + display_name: ANDN + value: 0b0100000 + funct3: + display_name: ANDN + value: 0b111 + opcode: { $inherits: inst_opcode/OP.yaml#/data } +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs2] & ~X[xs1]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let result : xlenbits = match op { + RISCV_ANDN => rs1_val & ~(rs2_val), + RISCV_ORN => rs1_val | ~(rs2_val), + RISCV_XNOR => ~(rs1_val ^ rs2_val), + RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), + RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), + RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_ROL => if sizeof(xlen) == 32 + then rs1_val <<< rs2_val[4..0] + else rs1_val <<< rs2_val[5..0], + RISCV_ROR => if sizeof(xlen) == 32 + then rs1_val >>> rs2_val[4..0] + else rs1_val >>> rs2_val[5..0] + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/clmul.yaml b/pkg/ifuzz/riscv64/gen/inst/B/clmul.yaml new file mode 100644 index 000000000000..f7edfc3b7863 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/clmul.yaml @@ -0,0 +1,66 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: clmul +long_name: Carry-less multiply (low-part) +description: | + `clmul` produces the lower half of the 2*XLEN carry-less product +definedBy: + extension: + anyOf: + - name: Zbc + - name: Zbkc +assembly: xd, xs1, xs2 +format: + $inherits: + - inst_subtype/R/R-x.yaml#/data + opcodes: + funct7: + display_name: CLMUL + value: 0b0000101 + funct3: + display_name: CLMUL + value: 0b001 + opcode: { $inherits: inst_opcode/OP.yaml#/data } +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg xs1_val = X[xs1]; + XReg xs2_val = X[xs2]; + XReg output = 0; + + for (U32 i=0; i < xlen(); i++) { + output = (((xs2_val >> i) & 1) == 1) + ? output ^ (xs1_val << i) + : output; + } + + X[xd] = output; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + result : xlenbits = zeros(); + foreach (i from 0 to (xlen_val - 1)) + if rs2_val[i] == bitone then result = result ^ (rs1_val << i); + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/clmulh.yaml b/pkg/ifuzz/riscv64/gen/inst/B/clmulh.yaml new file mode 100644 index 000000000000..dc43c59aa31f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/clmulh.yaml @@ -0,0 +1,66 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: clmulh +long_name: Carry-less multiply (high-part) +description: | + `clmulh` produces the upper half of the 2*XLEN carry-less product +definedBy: + extension: + anyOf: + - name: Zbc + - name: Zbkc +assembly: xd, xs1, xs2 +format: + $inherits: + - inst_subtype/R/R-x.yaml#/data + opcodes: + funct7: + display_name: CLMUL + value: 0b0000101 + funct3: + display_name: CLMULH + value: 0b011 + opcode: { $inherits: inst_opcode/OP.yaml#/data } +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg xs1_val = X[xs1]; + XReg xs2_val = X[xs2]; + XReg output = 0; + + for (U32 i=1; i <= xlen(); i++) { + output = (((xs2_val >> i) & 1) == 1) + ? output ^ (xs1_val >> (xlen() - i)) + : output; + } + + X[xd] = output; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + result : xlenbits = zeros(); + foreach (i from 0 to (xlen_val - 1)) + if rs2_val[i] == bitone then result = result ^ (rs1_val >> (xlen_val - i)); + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/orn.yaml b/pkg/ifuzz/riscv64/gen/inst/B/orn.yaml new file mode 100644 index 000000000000..805fb8eb7d3b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/orn.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: orn +long_name: OR with inverted operand +description: | + Performs the bitwise logical OR operation between xs1 and the bitwise inversion of xs2. +definedBy: + extension: + anyOf: + - name: Zbb + - name: Zbkb +assembly: xd, xs1, xs2 +format: + $inherits: + - inst_subtype/R/R-x.yaml#/data + opcodes: + funct7: + display_name: ORN + value: 0b0100000 + funct3: + display_name: ORN + value: 0b110 + opcode: { $inherits: inst_opcode/OP.yaml#/data } +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs1] | ~X[xs2]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let result : xlenbits = match op { + RISCV_ANDN => rs1_val & ~(rs2_val), + RISCV_ORN => rs1_val | ~(rs2_val), + RISCV_XNOR => ~(rs1_val ^ rs2_val), + RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), + RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), + RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_ROL => if sizeof(xlen) == 32 + then rs1_val <<< rs2_val[4..0] + else rs1_val <<< rs2_val[5..0], + RISCV_ROR => if sizeof(xlen) == 32 + then rs1_val >>> rs2_val[4..0] + else rs1_val >>> rs2_val[5..0] + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/rev8.yaml b/pkg/ifuzz/riscv64/gen/inst/B/rev8.yaml new file mode 100644 index 000000000000..277811b99543 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/rev8.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: rev8 +long_name: Byte-reverse register (RV64 encoding) +description: | + Reverses the order of the bytes in rs1. + + [NOTE] + The rev8 mnemonic corresponds to different instruction encodings in RV32 and RV64. + + [NOTE] + The byte-reverse operation is only available for the full register width. To emulate word-sized + and halfword-sized byte-reversal, perform a `rev8 xd,xs1` followed by a `srai xd,xd,K`, where K + is XLEN-32 and XLEN-16, respectively. +definedBy: + extension: + anyOf: + - name: Zbb + - name: Zbkb +assembly: xd, xs1 +encoding: + RV32: + match: 011010011000-----101-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + RV64: + match: 011010111000-----101-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg input = X[xs1]; + XReg output = 0; + + XReg j = xlen() - 1; + + for (U32 i=0; i<(xlen()-8); i = i+8) { + output[(i+7):i] = input[j:(j-7)]; + j = j - 8; + } + + X[xd] = output; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + result : xlenbits = zeros(); + foreach (i from 0 to (sizeof(xlen) - 8) by 8) + result[(i + 7) .. i] = rs1_val[(sizeof(xlen) - i - 1) .. (sizeof(xlen) - i - 8)]; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/rol.yaml b/pkg/ifuzz/riscv64/gen/inst/B/rol.yaml new file mode 100644 index 000000000000..854159bc1302 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/rol.yaml @@ -0,0 +1,70 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: rol +long_name: Rotate left (Register) +description: | + Performs a rotate left of xs1 by the amount in least-significant `log2(XLEN)` bits of xs2. +definedBy: + extension: + anyOf: + - name: Zbb + - name: Zbkb +assembly: xd, xs1, xs2 +format: + $inherits: + - inst_subtype/R/R-x.yaml#/data + opcodes: + funct7: + display_name: ROL + value: 0b0110000 + funct3: + display_name: ROL + value: 0b001 + opcode: { $inherits: inst_opcode/OP.yaml#/data } +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg shamt = (xlen() == 32) ? X[xs2][4:0] : X[xs2][5:0]; + + X[xd] = (X[xs1] << shamt) | (X[xs1] >> (xlen() - shamt)); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let result : xlenbits = match op { + RISCV_ANDN => rs1_val & ~(rs2_val), + RISCV_ORN => rs1_val | ~(rs2_val), + RISCV_XNOR => ~(rs1_val ^ rs2_val), + RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), + RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), + RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_ROL => if sizeof(xlen) == 32 + then rs1_val <<< rs2_val[4..0] + else rs1_val <<< rs2_val[5..0], + RISCV_ROR => if sizeof(xlen) == 32 + then rs1_val >>> rs2_val[4..0] + else rs1_val >>> rs2_val[5..0] + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/rolw.yaml b/pkg/ifuzz/riscv64/gen/inst/B/rolw.yaml new file mode 100644 index 000000000000..0d3ab986f912 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/rolw.yaml @@ -0,0 +1,65 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: rolw +long_name: Rotate left word (Register) +description: | + Performs a rotate left of the least-significant word of xs1 by the amount in least-significant 5 bits of xs2. + The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits. +definedBy: + allOf: + - xlen: 64 + - extension: + anyOf: + - name: Zbb + - name: Zbkb +assembly: xd, xs1, xs2 +format: + $inherits: + - inst_subtype/R/R-x.yaml#/data + opcodes: + funct7: + display_name: ROLW + value: 0b0110000 + funct3: + display_name: ROLW + value: 0b001 + opcode: { $inherits: inst_opcode/OP-32.yaml#/data } +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg xs1_word = X[xs1][31:0]; + XReg shamt = X[xs2][4:0]; + + XReg unextended_result = (xs1_word << shamt) | (xs1_word >> (32 - shamt)); + + X[xd] = {{32{unextended_result[31]}}, unextended_result}; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = (X(rs1))[31..0]; + let shamt = (X(rs2))[4..0]; + let result : bits(32) = match op { + RISCV_ROLW => rs1_val <<< shamt, + RISCV_RORW => rs1_val >>> shamt + }; + X(rd) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/ror.yaml b/pkg/ifuzz/riscv64/gen/inst/B/ror.yaml new file mode 100644 index 000000000000..3385b41f8117 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/ror.yaml @@ -0,0 +1,70 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: ror +long_name: Rotate right (Register) +description: | + Performs a rotate right of xs1 by the amount in least-significant `log2(XLEN)` bits of xs2. +definedBy: + extension: + anyOf: + - name: Zbb + - name: Zbkb +assembly: xd, xs1, xs2 +format: + $inherits: + - inst_subtype/R/R-x.yaml#/data + opcodes: + funct7: + display_name: ROR + value: 0b0110000 + funct3: + display_name: ROR + value: 0b101 + opcode: { $inherits: inst_opcode/OP.yaml#/data } +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg shamt = (xlen() == 32) ? X[xs2][4:0] : X[xs2][5:0]; + + X[xd] = (X[xs1] >> shamt) | (X[xs1] << (xlen() - shamt)); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let result : xlenbits = match op { + RISCV_ANDN => rs1_val & ~(rs2_val), + RISCV_ORN => rs1_val | ~(rs2_val), + RISCV_XNOR => ~(rs1_val ^ rs2_val), + RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), + RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), + RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_ROL => if sizeof(xlen) == 32 + then rs1_val <<< rs2_val[4..0] + else rs1_val <<< rs2_val[5..0], + RISCV_ROR => if sizeof(xlen) == 32 + then rs1_val >>> rs2_val[4..0] + else rs1_val >>> rs2_val[5..0] + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/rori.yaml b/pkg/ifuzz/riscv64/gen/inst/B/rori.yaml new file mode 100644 index 000000000000..d2deeebc562a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/rori.yaml @@ -0,0 +1,66 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: rori +long_name: Rotate right (Immediate) +description: | + Performs a rotate right of xs1 by the amount in the least-significant log2(XLEN) bits of shamt. + For RV32, the encodings corresponding to shamt[5]=1 are reserved. +definedBy: + extension: + anyOf: + - name: Zbb + - name: Zbkb +assembly: xd, xs1, shamt +encoding: + RV32: + match: 0110000----------101-----0010011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + RV64: + match: 011000-----------101-----0010011 + variables: + - name: shamt + location: 25-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg shamt = (xlen() == 32) ? shamt[4:0] : shamt[5:0]; + + X[xd] = (X[xs1] >> shamt) | (X[xs1] << (xlen() - shamt)); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let result : xlenbits = if sizeof(xlen) == 32 + then rs1_val >>> shamt[4..0] + else rs1_val >>> shamt; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/roriw.yaml b/pkg/ifuzz/riscv64/gen/inst/B/roriw.yaml new file mode 100644 index 000000000000..0055705f49c8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/roriw.yaml @@ -0,0 +1,58 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: roriw +long_name: Rotate right word (Immediate) +description: | + Performs a rotate right on the least-significant word of xs1 by the amount in + the least-significant log2(XLEN) bits of shamt. The resulting word value is sign-extended by + copying bit 31 to all of the more-significant bits. +definedBy: + allOf: + - xlen: 64 + - extension: + anyOf: + - name: Zbb + - name: Zbkb +assembly: xd, xs1, shamt +encoding: + match: 0110000----------101-----0011011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg xs1_word = X[xs1][31:0]; + + XReg unextended_result = (X[xs1] >> shamt) | (X[xs1] << (32 - shamt)); + X[xd] = {{32{unextended_result[31]}}, unextended_result}; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = (X(rs1))[31..0]; + let result : xlenbits = sign_extend(rs1_val >>> shamt); + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/rorw.yaml b/pkg/ifuzz/riscv64/gen/inst/B/rorw.yaml new file mode 100644 index 000000000000..3de03dd968cf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/rorw.yaml @@ -0,0 +1,65 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: rorw +long_name: Rotate right word (Register) +description: | + Performs a rotate right on the least-significant word of xs1 by the amount in + least-significant 5 bits of xs2. The resultant word is sign-extended by copying bit 31 to all + of the more-significant bits. +definedBy: + allOf: + - xlen: 64 + - extension: + anyOf: + - name: Zbb + - name: Zbkb +assembly: xd, xs1, xs2 +format: + $inherits: + - inst_subtype/R/R-x.yaml#/data + opcodes: + funct7: + display_name: RORW + value: 0b0110000 + funct3: + display_name: RORW + value: 0b101 + opcode: { $inherits: inst_opcode/OP-32.yaml#/data } +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg xs1_word = X[xs1][31:0]; + XReg shamt = X[xs2][4:0]; + + XReg unextended_result = (X[xs1] >> shamt) | (X[xs1] << (32 - shamt)); + X[xd] = {{32{unextended_result[31]}}, unextended_result}; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = (X(rs1))[31..0]; + let shamt = (X(rs2))[4..0]; + let result : bits(32) = match op { + RISCV_ROLW => rs1_val <<< shamt, + RISCV_RORW => rs1_val >>> shamt + }; + X(rd) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/B/xnor.yaml b/pkg/ifuzz/riscv64/gen/inst/B/xnor.yaml new file mode 100644 index 000000000000..6ebd5bd9aeb1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/B/xnor.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: xnor +long_name: Exclusive NOR +description: | + Performs the bit-wise exclusive-NOR operation on xs1 and xs2. +definedBy: + extension: + anyOf: + - name: Zbb + - name: Zbkb +assembly: xd, xs1, xs2 +format: + $inherits: + - inst_subtype/R/R-x.yaml#/data + opcodes: + funct7: + display_name: XNOR + value: 0b0100000 + funct3: + display_name: XNOR + value: 0b100 + opcode: { $inherits: inst_opcode/OP.yaml#/data } +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = ~(X[xs1] ^ X[xs2]); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let result : xlenbits = match op { + RISCV_ANDN => rs1_val & ~(rs2_val), + RISCV_ORN => rs1_val | ~(rs2_val), + RISCV_XNOR => ~(rs1_val ^ rs2_val), + RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), + RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), + RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_ROL => if sizeof(xlen) == 32 + then rs1_val <<< rs2_val[4..0] + else rs1_val <<< rs2_val[5..0], + RISCV_ROR => if sizeof(xlen) == 32 + then rs1_val >>> rs2_val[4..0] + else rs1_val >>> rs2_val[5..0] + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.add.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.add.yaml new file mode 100644 index 000000000000..92d0e9e56fb8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.add.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.add +long_name: Add +description: | + Add the value in xs2 to xd, and store the result in xd. + C.ADD expands into `add xd, xd, xs2`. +definedBy: + extension: + name: Zca +assembly: xd, xs2 +encoding: + match: 1001----------10 + variables: + - name: xs2 + location: 6-2 + not: 0 + - name: xd + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +hints: + - { $ref: inst/Zihintntl/c.ntl.p1.yaml# } + - { $ref: inst/Zihintntl/c.ntl.pall.yaml# } + - { $ref: inst/Zihintntl/c.ntl.s1.yaml# } + - { $ref: inst/Zihintntl/c.ntl.all.yaml# } +operation(): | + XReg t0 = X[xd]; + XReg t1 = X[xs2]; + X[xd] = t0 + t1; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rd); + let rs2_val = X(rs2); + X(rd) = rs1_val + rs2_val; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.addi.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.addi.yaml new file mode 100644 index 000000000000..7e0a57c26c41 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.addi.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.addi +long_name: Add a sign-extended non-zero immediate +description: | + C.ADDI adds the non-zero sign-extended 6-bit immediate to the value in register xd then writes the result to xd. + C.ADDI expands into `addi xd, xd, imm`. + C.ADDI is only valid when xd ≠ x0 and imm ≠ 0. + The code points with xd=x0 encode the C.NOP instruction; the remaining code points with imm=0 encode HINTs. +definedBy: + extension: + name: Zca +assembly: xd, imm +encoding: + match: 000-----------01 + variables: + - name: imm + location: 12|6-2 + not: 0 + - name: xd + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xd] + $signed(imm); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.addi16sp.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.addi16sp.yaml new file mode 100644 index 000000000000..f35ac762955e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.addi16sp.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.addi16sp +long_name: Add a sign-extended non-zero immediate +description: | + C.ADDI16SP adds the non-zero sign-extended 6-bit immediate to the value in the stack pointer (sp=x2), where the immediate is scaled to represent multiples of 16 in the range (-512,496). + C.ADDI16SP is used to adjust the stack pointer in procedure prologues and epilogues. + It expands into `addi x2, x2, nzimm[9:4]`. + C.ADDI16SP is only valid when nzimm ≠ 0; the code point with nzimm=0 is reserved. +definedBy: + extension: + name: Zca +assembly: sp, imm +encoding: + match: 011-00010-----01 + variables: + - name: imm + location: 12|4-3|5|2|6 + left_shift: 4 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[2] = X[2] + $signed(imm); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.addi4spn.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.addi4spn.yaml new file mode 100644 index 000000000000..2accae4b3aaa --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.addi4spn.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.addi4spn +long_name: Add a zero-extended non-zero immediate, scaled by 4, to the stack pointer +description: | + Adds a zero-extended non-zero immediate, scaled by 4, to the stack pointer, x2, and writes the result to rd'. + This instruction is used to generate pointers to stack-allocated variables. + It expands to `addi rd', x2, nzuimm[9:2]`. + C.ADDI4SPN is only valid when nzuimm ≠ 0; the code points with nzuimm=0 are reserved. +definedBy: + extension: + name: Zca +assembly: xd, sp, imm +encoding: + match: 000-----------00 + variables: + - name: imm + location: 10-7|12-11|5|6 + left_shift: 2 + not: 0 + - name: xd + location: 4-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[creg2reg(xd)] = X[2] + imm; diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.addiw.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.addiw.yaml new file mode 100644 index 000000000000..ca2d9b2e336e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.addiw.yaml @@ -0,0 +1,39 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.addiw +long_name: Add a sign-extended non-zero immediate +description: | + C.ADDIW is an RV64C/RV128C-only instruction that performs the same computation as C.ADDI but produces a 32-bit result, then sign-extends result to 64 bits. + C.ADDIW expands into `addiw xd, xd, imm`. + The immediate can be zero for C.ADDIW, where this corresponds to `sext.w xd`. + C.ADDIW is only valid when xd ≠ x0; the code points with xd=x0 are reserved. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zca +assembly: xd, imm +encoding: + match: 001-----------01 + variables: + - name: imm + location: 12|6-2 + - name: xd + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = sext((X[xd] + sext(imm, 6)), 32); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.addw.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.addw.yaml new file mode 100644 index 000000000000..557989090a0b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.addw.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.addw +long_name: Add word +description: | + Add the 32-bit values in xs2 from xd, and store the result in xd. + The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15). + C.ADDW expands into `addw xd, xd, xs2`. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zca +assembly: xd, xs2 +encoding: + match: 100111---01---01 + variables: + - name: xs2 + location: 4-2 + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<32> t0 = X[creg2reg(xd)][31:0]; + Bits<32> t1 = X[creg2reg(xs2)][31:0]; + X[creg2reg(xd)] = $signed(t0 + t1); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = (X(rd+8))[31..0]; + let rs2_val = (X(rs2+8))[31..0]; + let result : bits(32) = match op { + RISCV_ADDW => rs1_val + rs2_val, + RISCV_SUBW => rs1_val - rs2_val, + RISCV_SLLW => rs1_val << (rs2_val[4..0]), + RISCV_SRLW => rs1_val >> (rs2_val[4..0]), + RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0]) + }; + X(rd+8) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.and.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.and.yaml new file mode 100644 index 000000000000..fe944cdd57b9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.and.yaml @@ -0,0 +1,64 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.and +long_name: And +description: | + And xd with xs2, and store the result in xd + The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15). + C.AND expands into `and xd, xd, xs2`. +definedBy: + extension: + name: Zca +assembly: xd, xs2 +encoding: + match: 100011---11---01 + variables: + - name: xs2 + location: 4-2 + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg t0 = X[creg2reg(xd)]; + XReg t1 = X[creg2reg(xs2)]; + X[creg2reg(xd)] = t0 & t1; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rd+8); + let rs2_val = X(rs2+8); + let result : xlenbits = match op { + RISCV_ADD => rs1_val + rs2_val, + RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), + RISCV_AND => rs1_val & rs2_val, + RISCV_OR => rs1_val | rs2_val, + RISCV_XOR => rs1_val ^ rs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then rs1_val << (rs2_val[4..0]) + else rs1_val << (rs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then rs1_val >> (rs2_val[4..0]) + else rs1_val >> (rs2_val[5..0]), + RISCV_SUB => rs1_val - rs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(rs1_val, rs2_val[4..0]) + else shift_right_arith64(rs1_val, rs2_val[5..0]) + }; + X(rd+8) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.andi.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.andi.yaml new file mode 100644 index 000000000000..2294c1ab4633 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.andi.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.andi +long_name: And immediate +description: | + And an immediate to the value in xd, and store the result in xd. + The xd register index should be used as xd+8 (registers x8-x15). + C.ANDI expands into `andi xd, xd, imm`. +definedBy: + extension: + name: Zca +assembly: xd, imm +encoding: + match: 100-10--------01 + variables: + - name: imm + location: 12|6-2 + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + # shamt is between 0-63 + X[creg2reg(xd)] = X[creg2reg(xd)] & $signed(imm); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rd_val = X(rd+8); + let immext : xlenbits = sign_extend(imm); + let result : xlenbits = match op { + RISCV_ADDI => rd_val + immext, + RISCV_SLTI => zero_extend(bool_to_bits(rd_val <_s immext)), + RISCV_SLTIU => zero_extend(bool_to_bits(rd_val <_u immext)), + RISCV_ANDI => rd_val & immext, + RISCV_ORI => rd_val | immext, + RISCV_XORI => rd_val ^ immext + }; + X(rd+8) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.beqz.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.beqz.yaml new file mode 100644 index 000000000000..98df50b52316 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.beqz.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.beqz +long_name: Branch if Equal Zero +description: | + C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register xs1' is zero. + It expands to `beq` `xs1, x0, offset`. +definedBy: + extension: + name: Zca +assembly: xs1, imm +encoding: + match: 110-----------01 + variables: + - name: imm + location: 12|6-5|2|11-10|4-3 + left_shift: 1 + sign_extend: true + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + if (X[creg2reg(xs1)] == 0) { + jump($pc + $signed(imm)); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(0); + let taken : bool = match op { + RISCV_BEQ => rs1_val == rs2_val, + RISCV_BNE => rs1_val != rs2_val, + RISCV_BLT => rs1_val <_s rs2_val, + RISCV_BGE => rs1_val >=_s rs2_val, + RISCV_BLTU => rs1_val <_u rs2_val, + RISCV_BGEU => rs1_val >=_u rs2_val + }; + let t : xlenbits = PC + sign_extend(imm); + if taken then { + /* Extensions get the first checks on the prospective target address. */ + match ext_control_check_pc(t) { + Ext_ControlAddr_Error(e) => { + ext_handle_control_check_error(e); + RETIRE_FAIL + }, + Ext_ControlAddr_OK(target) => { + if bit_to_bool(target[1]) & not(extension("C")) then { + handle_mem_exception(target, E_Fetch_Addr_Align()); + RETIRE_FAIL; + } else { + set_next_pc(target); + RETIRE_SUCCESS + } + } + } + } else RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.bnez.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.bnez.yaml new file mode 100644 index 000000000000..930ac3c7ba6c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.bnez.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.bnez +long_name: Branch if NOT Equal Zero +description: | + C.BEQZ performs conditional control transfers. The offset is sign-extended and added to the pc to form the branch target address. It can therefore target a ±256 B range. C.BEQZ takes the branch if the value in register xs1' is NOT zero. + It expands to `beq` `xs1, x0, offset`. +definedBy: + extension: + name: Zca +assembly: xs1, imm +encoding: + match: 111-----------01 + variables: + - name: imm + location: 12|6-5|2|11-10|4-3 + left_shift: 1 + sign_extend: true + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + if (X[creg2reg(xs1)] != 0) { + jump($pc + $signed(imm)); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(0); + let taken : bool = match op { + RISCV_BEQ => rs1_val == rs2_val, + RISCV_BNE => rs1_val != rs2_val, + RISCV_BLT => rs1_val <_s rs2_val, + RISCV_BGE => rs1_val >=_s rs2_val, + RISCV_BLTU => rs1_val <_u rs2_val, + RISCV_BGEU => rs1_val >=_u rs2_val + }; + let t : xlenbits = PC + sign_extend(imm); + if taken then { + /* Extensions get the first checks on the prospective target address. */ + match ext_control_check_pc(t) { + Ext_ControlAddr_Error(e) => { + ext_handle_control_check_error(e); + RETIRE_FAIL + }, + Ext_ControlAddr_OK(target) => { + if bit_to_bool(target[1]) & not(extension("C")) then { + handle_mem_exception(target, E_Fetch_Addr_Align()); + RETIRE_FAIL; + } else { + set_next_pc(target); + RETIRE_SUCCESS + } + } + } + } else RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.ebreak.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.ebreak.yaml new file mode 100644 index 000000000000..c600d2a72560 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.ebreak.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.ebreak +long_name: Breakpoint exception +description: | + The C.EBREAK instruction is used by debuggers to cause control to be transferred back to + a debugging environment. Unless overridden by an external debug environment, + C.EBREAK raises a breakpoint exception and performs no other operation. + + [NOTE] + As described in the `C` Standard Extension for Compressed Instructions, the `c.ebreak` + instruction performs the same operation as the EBREAK instruction. + + EBREAK causes the receiving privilege mode's epc register to be set to the address of + the EBREAK instruction itself, not the address of the following instruction. + As EBREAK causes a synchronous exception, it is not considered to retire, + and should not increment the `minstret` CSR. +definedBy: + extension: + name: Zca +assembly: "" +encoding: + match: "1001000000000010" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + if (TRAP_ON_EBREAK) { + raise_precise(ExceptionCode::Breakpoint, mode(), $pc); + } else { + eei_ebreak(); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + handle_mem_exception(PC, E_Breakpoint()); + RETIRE_FAIL + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.j.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.j.yaml new file mode 100644 index 000000000000..e3008c22ccf1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.j.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.j +long_name: Jump +description: | + C.J performs an unconditional control transfer. The offset is sign-extended and added to the pc to form the jump target address. C.J can therefore target a ±2 KiB range. + It expands to `jal` `x0, offset`. +definedBy: + extension: + name: Zca +assembly: imm +encoding: + match: 101-----------01 + variables: + - name: imm + location: 12|8|10-9|6|7|2|11|5-3 + left_shift: 1 + sign_extend: true +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + jump($pc + $signed(imm)); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.jal.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.jal.yaml new file mode 100644 index 000000000000..6726c9458742 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.jal.yaml @@ -0,0 +1,39 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.jal +long_name: Jump and Link +description: | + C.JAL is an RV32C-only instruction that performs the same operation as C.J, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. + It expands to `jal` `x1, offset`. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zca +assembly: imm +encoding: + match: 001-----------01 + variables: + - name: imm + location: 12|8|10-9|6|7|2|11|5-3 + left_shift: 1 + sign_extend: true +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg return_addr = $pc + 2; + + X[1] = return_addr; + jump_halfword($pc + $signed(imm)); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.jalr.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.jalr.yaml new file mode 100644 index 000000000000..a1b96f05f2f9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.jalr.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.jalr +long_name: Jump and Link Register +description: | + C.JALR (jump and link register) performs the same operation as C.JR, but additionally writes the address of the instruction following the jump (pc+2) to the link register, x1. + C.JALR expands to jalr x1, 0(xs1). +definedBy: + extension: + name: Zca +assembly: xs1 +encoding: + match: 1001-----0000010 + variables: + - name: xs1 + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + XReg addr = X[xs1]; + XReg returnaddr; + returnaddr = $pc + 2; + + X[1] = returnaddr; + jump(addr); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.jr.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.jr.yaml new file mode 100644 index 000000000000..4f9f5cb6b941 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.jr.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.jr +long_name: Jump Register +description: | + C.JR (jump register) performs an unconditional control transfer to the address in register xs1. + C.JR expands to jalr x0, 0(xs1). +definedBy: + extension: + name: Zca +assembly: xs1 +encoding: + match: 1000-----0000010 + variables: + - name: xs1 + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + jump(X[xs1]); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.ld.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.ld.yaml new file mode 100644 index 000000000000..4bcb7fc4267a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.ld.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.ld +long_name: Load double +description: | + Loads a 64-bit value from memory into register xd. + It computes an effective address by adding the zero-extended offset, scaled by 8, + to the base address in register xs1. + It expands to `ld` `xd, offset(xs1)`. + For RV32, if the Zclsd extension is enabled, this instruction loads a 64-bit value into registers xd and xd+1. It computes an effective address by adding the zero-extended imm, scaled by 8, to the base address in register xs1. +definedBy: + anyOf: + - allOf: + - xlen: 64 + - extension: + name: Zca + - extension: + name: Zclsd +assembly: xd, imm(xs1) +encoding: + RV32: + match: 011-----------00 + variables: + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: xd + location: 4-2 + not: [1, 3, 5, 7] + - name: xs1 + location: 9-7 + RV64: + match: 011-----------00 + variables: + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: xd + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (xlen() == 32) { + if (implemented?(ExtensionName::Zclsd)) { + Bits<64> val = read_memory<64>(X[creg2reg(xs1)] + imm, $encoding); + X[creg2reg(xd)] = val[31:0]; + X[creg2reg(xd + 1)] = val[63:32]; + } else { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + } else { + XReg virtual_address = X[creg2reg(xs1)] + imm; + X[creg2reg(xd)] = sext(read_memory<64>(virtual_address, $encoding), 64); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WOxD => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.ldsp.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.ldsp.yaml new file mode 100644 index 000000000000..46b60b3547b4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.ldsp.yaml @@ -0,0 +1,64 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.ldsp +long_name: Load doubleword from stack pointer +description: | + C.LDSP is an RV64C/RV128C-only instruction that loads a 64-bit value from memory + into register xd. + It computes its effective address by adding the zero-extended offset, scaled by 8, + to the stack pointer, x2. + It expands to `ld xd, offset(x2)`. + C.LDSP is only valid when xd ≠ x0; code points with xd=x0 are reserved. +definedBy: + anyOf: + - allOf: + - xlen: 32 + - extension: + name: Zclsd + - allOf: + - xlen: 64 + - extension: + name: Zca +assembly: xd, imm(sp) +encoding: + RV32: + match: 011-----------10 + variables: + - name: imm + location: 4-2|12|6-5 + left_shift: 3 + - name: xd + location: 11-7 + not: [0, 1, 3, 5, 7] + RV64: + match: 011-----------10 + variables: + - name: imm + location: 4-2|12|6-5 + left_shift: 3 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[2] + imm; + Bits<64> value = read_memory<64>(virtual_address, $encoding); + + if (xlen()== 64) { + X[creg2reg(xd)] = value; + } else if (xlen() == 32) { + X[creg2reg(xd)] = value[31:0]; + X[creg2reg(xd) + 1] = value[63:32]; + } diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.li.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.li.yaml new file mode 100644 index 000000000000..dc23d1b37050 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.li.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.li +long_name: Load the sign-extended 6-bit immediate +description: | + C.LI loads the sign-extended 6-bit immediate, imm, into register xd. + C.LI expands into `addi xd, x0, imm`. + C.LI is only valid when xd ≠ x0; the code points with xd=x0 encode HINTs. +definedBy: + extension: + name: Zca +assembly: xd, imm +encoding: + match: 010-----------01 + variables: + - name: imm + location: 12|6-2 + - name: xd + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = $signed(imm); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.lui.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.lui.yaml new file mode 100644 index 000000000000..20e30b35875d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.lui.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.lui +long_name: Load Upper Immediate +description: | + C.LUI loads the non-zero 6-bit immediate field into bits 17-12 of the destination register, clears the bottom 12 bits, and sign-extends bit 17 into all higher bits of the destination. + C.LUI expands into `lui xd, imm`. + C.LUI is only valid when xd≠x0 and xd≠x2, and when the immediate is not equal to zero. + The code points with imm=0 are reserved; the remaining code points with xd=x0 are HINTs; and the remaining code points with xd=x2 correspond to the C.ADDI16SP instruction +definedBy: + extension: + name: Zca +assembly: xd, imm +encoding: + match: 011-----------01 + variables: + - name: imm + location: 12|6-2 + left_shift: 12 + - name: xd + location: 11-7 + not: [0, 2] +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = $signed(imm); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.lw.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.lw.yaml new file mode 100644 index 000000000000..5724b096d023 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.lw.yaml @@ -0,0 +1,74 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.lw +long_name: Load word +description: | + Loads a 32-bit value from memory into register xd. + It computes an effective address by adding the zero-extended offset, scaled by 4, + to the base address in register xs1. + It expands to `lw` `xd, offset(xs1)`. +definedBy: + extension: + name: Zca +assembly: xd, imm(xs1) +encoding: + match: 010-----------00 + variables: + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: xd + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + X[creg2reg(xd)] = sext(read_memory<32>(virtual_address, $encoding), 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.lwsp.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.lwsp.yaml new file mode 100644 index 000000000000..0c7d0df483e0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.lwsp.yaml @@ -0,0 +1,41 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.lwsp +long_name: Load word from stack pointer +description: | + Loads a 32-bit value from memory into register xd. + It computes an effective address by adding the zero-extended offset, scaled by 4, + to the stack pointer, x2. + It expands to `lw` `xd, offset(x2)`. + C.LWSP is only valid when xd ≠ x0. The code points with xd=x0 are reserved. +definedBy: + extension: + name: Zca +assembly: xd, imm(sp) +encoding: + match: 010-----------10 + variables: + - name: imm + location: 3-2|12|6-4 + left_shift: 2 + - name: xd + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[2] + imm; + + X[xd] = sext(read_memory<32>(virtual_address, $encoding), 32); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.mv.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.mv.yaml new file mode 100644 index 000000000000..15c2a5353213 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.mv.yaml @@ -0,0 +1,48 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.mv +long_name: Move Register +description: | + C.MV (move register) performs copy of the data in register xs2 to register xd + C.MV expands to addi xd, x0, xs2. +definedBy: + extension: + name: Zca +assembly: xd, xs2 +encoding: + match: 1000----------10 + variables: + - name: xd + location: 11-7 + not: 0 + - name: xs2 + location: 6-2 + not: 0 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs2]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs2_val = X(xs2); + X(rs) = xs2_val + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.nop.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.nop.yaml new file mode 100644 index 000000000000..c433e31ab4d0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.nop.yaml @@ -0,0 +1,26 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.nop +long_name: Non-operation +description: | + C.NOP expands into `addi x0, x0, 0`. +definedBy: + extension: + name: Zca +assembly: "" +encoding: + match: "0000000000000001" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.or.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.or.yaml new file mode 100644 index 000000000000..cceba63d7907 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.or.yaml @@ -0,0 +1,64 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.or +long_name: Or +description: | + Or xd with xs2, and store the result in xd + The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15). + C.OR expands into `or xd, xd, xs2`. +definedBy: + extension: + name: Zca +assembly: xd, xs2 +encoding: + match: 100011---10---01 + variables: + - name: xs2 + location: 4-2 + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg t0 = X[creg2reg(xd)]; + XReg t1 = X[creg2reg(xs2)]; + X[creg2reg(xd)] = t0 | t1; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rd+8); + let rs2_val = X(rs2+8); + let result : xlenbits = match op { + RISCV_ADD => rs1_val + rs2_val, + RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), + RISCV_AND => rs1_val & rs2_val, + RISCV_OR => rs1_val | rs2_val, + RISCV_XOR => rs1_val ^ rs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then rs1_val << (rs2_val[4..0]) + else rs1_val << (rs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then rs1_val >> (rs2_val[4..0]) + else rs1_val >> (rs2_val[5..0]), + RISCV_SUB => rs1_val - rs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(rs1_val, rs2_val[4..0]) + else shift_right_arith64(rs1_val, rs2_val[5..0]) + }; + X(rd+8) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.sd.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.sd.yaml new file mode 100644 index 000000000000..acd58f04c8ed --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.sd.yaml @@ -0,0 +1,67 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sd +long_name: Store double +description: | + For RV64, store a 64-bit value in register xs2 to memory. For RV32 with Zclsd extension, store a 64-bit value from the combined values in register pair [xs2, xs2+1] to memory. + It computes an effective address by adding the zero-extended offset, scaled by 8, + to the base address in register xs1. + It expands to `sd` `xs2, offset(xs1)`. +definedBy: + anyOf: + - allOf: + - xlen: 64 + - extension: + name: Zca + - extension: + name: Zclsd +assembly: xs2, imm(xs1) +encoding: + RV32: + match: 111-----------00 + variables: + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: xs2 + location: 4-2 + not: [1, 3, 5, 7] + - name: xs1 + location: 9-7 + RV64: + match: 111-----------00 + variables: + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: xs2 + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + if (xlen() == 32) { + if (implemented?(ExtensionName::Zclsd)) { + Bits<64> data = {X[creg2reg(xs2) + 1], X[creg2reg(xs2)]}; + write_memory<64>(virtual_address, data, $encoding); + } else { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + } else { + write_memory<64>(virtual_address, X[creg2reg(xs2)], $encoding); + } diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.sdsp.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.sdsp.yaml new file mode 100644 index 000000000000..42ddefc58db4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.sdsp.yaml @@ -0,0 +1,63 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sdsp +long_name: Store doubleword to stack +description: | + Stores a 64-bit value in register rs2 to memory. + It computes an effective address by adding the zero-extended offset, scaled by 8, + to the stack pointer, x2. + It expands to `sd` `xs2, offset(x2)`. +definedBy: + anyOf: + - allOf: + - xlen: 64 + - extension: + name: Zca + - extension: + name: Zclsd +assembly: xs2, imm(sp) +encoding: + RV32: + match: 111-----------10 + variables: + - name: xs2 + location: 6-2 + not: [1, 3, 5, 7] + - name: imm + location: 9-7|12-10 + left_shift: 3 + RV64: + match: 111-----------10 + variables: + - name: xs2 + location: 6-2 + - name: imm + location: 9-7|12-10 + left_shift: 3 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[2] + imm; + + if (xlen() == 32) { + if (implemented?(ExtensionName::Zclsd)) { + Bits<64> data = {X[creg2reg(xs2) + 1], X[creg2reg(xs2)]}; + write_memory<64>(virtual_address, data, $encoding); + } else { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + } else { + write_memory<64>(virtual_address, X[creg2reg(xs2)], $encoding); + } diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.slli.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.slli.yaml new file mode 100644 index 000000000000..31e045a57a9a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.slli.yaml @@ -0,0 +1,65 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.slli +long_name: Shift left logical immediate +description: | + Shift the value in xd left by shamt, and store the result back in xd. + C.SLLI expands into `slli xd, xd, shamt`. +definedBy: + extension: + name: Zca +assembly: xd, shamt +encoding: + RV32: + match: 0000----------10 + variables: + - name: shamt + location: 6-2 + not: 0 + - name: xd + location: 11-7 + RV64: + match: 000-----------10 + variables: + - name: shamt + location: 12|6-2 + not: 0 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + # shamt is between 0-63 + X[xd] = X[xd] << shamt; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rd_val = X(rd); + /* the decoder guard should ensure that shamt[5] = 0 for RV32 */ + let result : xlenbits = match op { + RISCV_SLLI => if sizeof(xlen) == 32 + then rd_val << shamt[4..0] + else rd_val << shamt, + RISCV_SRLI => if sizeof(xlen) == 32 + then rd_val >> shamt[4..0] + else rd_val >> shamt, + RISCV_SRAI => if sizeof(xlen) == 32 + then shift_right_arith32(rd_val, shamt[4..0]) + else shift_right_arith64(rd_val, shamt) + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.srai.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.srai.yaml new file mode 100644 index 000000000000..58691bc37ca7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.srai.yaml @@ -0,0 +1,66 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.srai +long_name: Shift right arithmetical immediate +description: | + Arithmetic shift (the original sign bit is copied into the vacated upper bits) the value in xd right by shamt, and store the result in xd. + The xd register index should be used as xd+8 (registers x8-x15). + C.SRAI expands into `srai xd, xd, shamt`. +definedBy: + extension: + name: Zca +assembly: xd, shamt +encoding: + RV32: + match: 100001--------01 + variables: + - name: shamt + location: 6-2 + not: 0 + - name: xd + location: 9-7 + RV64: + match: 100-01--------01 + variables: + - name: shamt + location: 12|6-2 + not: 0 + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + # shamt is between 0-63 + X[creg2reg(xd)] = X[creg2reg(xd)] >>> shamt; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rd_val = X(rd+8); + /* the decoder guard should ensure that shamt[5] = 0 for RV32 */ + let result : xlenbits = match op { + RISCV_SLLI => if sizeof(xlen) == 32 + then rd_val << shamt[4..0] + else rd_val << shamt, + RISCV_SRLI => if sizeof(xlen) == 32 + then rd_val >> shamt[4..0] + else rd_val >> shamt, + RISCV_SRAI => if sizeof(xlen) == 32 + then shift_right_arith32(rd_val, shamt[4..0]) + else shift_right_arith64(rd_val, shamt) + }; + X(rd+8) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.srli.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.srli.yaml new file mode 100644 index 000000000000..ed9e648d986d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.srli.yaml @@ -0,0 +1,66 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.srli +long_name: Shift right logical immediate +description: | + Shift the value in xd right by shamt, and store the result back in xd. + The xd register index should be used as xd+8 (registers x8-x15). + C.SRLI expands into `srli xd, xd, shamt`. +definedBy: + extension: + name: Zca +assembly: xd, shamt +encoding: + RV32: + match: 100000--------01 + variables: + - name: shamt + location: 6-2 + not: 0 + - name: xd + location: 9-7 + RV64: + match: 100-00--------01 + variables: + - name: shamt + location: 12|6-2 + not: 0 + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + # shamt is between 0-63 + X[creg2reg(xd)] = X[creg2reg(xd)] >> shamt; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rd_val = X(rd+8); + /* the decoder guard should ensure that shamt[5] = 0 for RV32 */ + let result : xlenbits = match op { + RISCV_SLLI => if sizeof(xlen) == 32 + then rd_val << shamt[4..0] + else rd_val << shamt, + RISCV_SRLI => if sizeof(xlen) == 32 + then rd_val >> shamt[4..0] + else rd_val >> shamt, + RISCV_SRAI => if sizeof(xlen) == 32 + then shift_right_arith32(rd_val, shamt[4..0]) + else shift_right_arith64(rd_val, shamt) + }; + X(rd+8) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.sub.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.sub.yaml new file mode 100644 index 000000000000..f6b23590f839 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.sub.yaml @@ -0,0 +1,64 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sub +long_name: Subtract +description: | + Subtract the value in xs2 from xd, and store the result in xd. + The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15). + C.SUB expands into `sub xd, xd, xs2`. +definedBy: + extension: + name: Zca +assembly: xd, xs2 +encoding: + match: 100011---00---01 + variables: + - name: xs2 + location: 4-2 + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg t0 = X[creg2reg(xd)]; + XReg t1 = X[creg2reg(xs2)]; + X[creg2reg(xd)] = t0 - t1; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rd+8); + let rs2_val = X(rs2+8); + let result : xlenbits = match op { + RISCV_ADD => rs1_val + rs2_val, + RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), + RISCV_AND => rs1_val & rs2_val, + RISCV_OR => rs1_val | rs2_val, + RISCV_XOR => rs1_val ^ rs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then rs1_val << (rs2_val[4..0]) + else rs1_val << (rs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then rs1_val >> (rs2_val[4..0]) + else rs1_val >> (rs2_val[5..0]), + RISCV_SUB => rs1_val - rs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(rs1_val, rs2_val[4..0]) + else shift_right_arith64(rs1_val, rs2_val[5..0]) + }; + X(rd+8) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.subw.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.subw.yaml new file mode 100644 index 000000000000..69e8c96b4dda --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.subw.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.subw +long_name: Subtract word +description: | + Subtract the 32-bit values in xs2 from xd, and store the result in xd. + The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15). + C.SUBW expands into `subw xd, xd, xs2`. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zca +assembly: xd, xs2 +encoding: + match: 100111---00---01 + variables: + - name: xs2 + location: 4-2 + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<32> t0 = X[creg2reg(xd)][31:0]; + Bits<32> t1 = X[creg2reg(xs2)][31:0]; + X[creg2reg(xd)] = sext(t0 - t1, 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = (X(rd+8))[31..0]; + let rs2_val = (X(rs2+8))[31..0]; + let result : bits(32) = match op { + RISCV_ADDW => rs1_val + rs2_val, + RISCV_SUBW => rs1_val - rs2_val, + RISCV_SLLW => rs1_val << (rs2_val[4..0]), + RISCV_SRLW => rs1_val >> (rs2_val[4..0]), + RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0]) + }; + X(rd+8) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.sw.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.sw.yaml new file mode 100644 index 000000000000..e859aab1f8ac --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.sw.yaml @@ -0,0 +1,41 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sw +long_name: Store word +description: | + Stores a 32-bit value in register xs2 to memory. + It computes an effective address by adding the zero-extended offset, scaled by 4, + to the base address in register xs1. + It expands to `sw` `rs2, offset(xs1)`. +definedBy: + extension: + name: Zca +assembly: xs2, imm(xs1) +encoding: + match: 110-----------00 + variables: + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: xs2 + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + write_memory<32>(virtual_address, X[creg2reg(xs2)][31:0], $encoding); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.swsp.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.swsp.yaml new file mode 100644 index 000000000000..505ec133e2db --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.swsp.yaml @@ -0,0 +1,39 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.swsp +long_name: Store word to stack +description: | + Stores a 32-bit value in register xs2 to memory. + It computes an effective address by adding the zero-extended offset, scaled by 4, + to the stack pointer, x2. + It expands to `sw` `xs2, offset(x2)`. +definedBy: + extension: + name: Zca +assembly: xs2, imm(sp) +encoding: + match: 110-----------10 + variables: + - name: imm + location: 8-7|12-9 + left_shift: 2 + - name: xs2 + location: 6-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[2] + imm; + + write_memory<32>(virtual_address, X[xs2][31:0], $encoding); diff --git a/pkg/ifuzz/riscv64/gen/inst/C/c.xor.yaml b/pkg/ifuzz/riscv64/gen/inst/C/c.xor.yaml new file mode 100644 index 000000000000..b80de2995327 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/C/c.xor.yaml @@ -0,0 +1,64 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.xor +long_name: Exclusive Or +description: | + Exclusive or xd with xs2, and store the result in xd + The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15). + C.XOR expands into `xor xd, xd, xs2`. +definedBy: + extension: + name: Zca +assembly: xd, xs2 +encoding: + match: 100011---01---01 + variables: + - name: xs2 + location: 4-2 + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg t0 = X[creg2reg(xd)]; + XReg t1 = X[creg2reg(xs2)]; + X[creg2reg(xd)] = t0 ^ t1; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rd+8); + let rs2_val = X(rs2+8); + let result : xlenbits = match op { + RISCV_ADD => rs1_val + rs2_val, + RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)), + RISCV_AND => rs1_val & rs2_val, + RISCV_OR => rs1_val | rs2_val, + RISCV_XOR => rs1_val ^ rs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then rs1_val << (rs2_val[4..0]) + else rs1_val << (rs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then rs1_val >> (rs2_val[4..0]) + else rs1_val >> (rs2_val[5..0]), + RISCV_SUB => rs1_val - rs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(rs1_val, rs2_val[4..0]) + else shift_right_arith64(rs1_val, rs2_val[5..0]) + }; + X(rd+8) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fadd.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fadd.d.yaml new file mode 100644 index 000000000000..356768fbd018 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fadd.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fadd.d +long_name: Floating-Point Add Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fadd.d` instruction is analogous to `fadd.s` and performs double-precision floating-point addition of + `fs1` and `fs2` and writes the final result to `fd`. +assembly: fd, fs1, fs2, rm +encoding: + match: 0000001------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fclass.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fclass.d.yaml new file mode 100644 index 000000000000..dd5f9e8cebd9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fclass.d.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fclass.d +long_name: Floating-Point Classify Double-Precision +description: | + The `fclass.d` instruction is defined analogously to its single-precision counterpart, but operates on double-precision + operands. It examines the value in floating-point register `fs1` and writes to integer register `xd` a 10-bit mask that + indicates the class of the floating point number. + + The format of the mask is described in the table below. The corresponding bit in `xd` will be set if the property + is true and clear otherwise. All other bits in `xd` are cleared. Note that exactly one bit in `xd` will be set. + + .Format of result of `fclass` instruction. + [%autowidth,float="center",align="center",cols="^,<",options="header",] + |=== + |_xd_ bit |Meaning + |0 |_fs1_ is latexmath:[$-\infty$]. + |1 |_fs1_ is a negative normal number. + |2 |_fs1_ is a negative subnormal number. + |3 |_fs1_ is latexmath:[$-0$]. + |4 |_fs1_ is latexmath:[$+0$]. + |5 |_fs1_ is a positive subnormal number. + |6 |_fs1_ is a positive normal number. + |7 |_fs1_ is latexmath:[$+\infty$]. + |8 |_fs1_ is a signaling NaN. + |9 |_fs1_ is a quiet NaN. + |=== + +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +assembly: xd, fs1 +encoding: + match: 111000100000-----001-----1010011 + variables: + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.l.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.l.yaml new file mode 100644 index 000000000000..1e7b1fc40972 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.l.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.d.l +long_name: Floating-Point Convert Long to Double-Precision +definedBy: + allOf: + - xlen: 64 + - extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fcvt.d.l` instruction converts a 64-bit signed integer, in integer register `xs1` into a double-precision + floating-point number in floating-point register `fd`. +assembly: fd, xs1, rm +encoding: + match: 110100100010-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.lu.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.lu.yaml new file mode 100644 index 000000000000..cf41aa46ab46 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.lu.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.d.lu +long_name: Floating-Point Convert Unsigned Long to Double-Precision +definedBy: + allOf: + - xlen: 64 + - extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fcvt.d.lu` instruction converts to or from a 64-bit unsigned integer, `xs1` into a double-precision + floating-point number in floating-point register `fd`. +assembly: fd, xs1, rm +encoding: + match: 110100100011-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.s.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.s.yaml new file mode 100644 index 000000000000..5a4563d659f4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.s.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.d.s +long_name: Floating-Point Convert Single-Precision to Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The single-precision to double-precision conversion instruction, `fcvt.d.s` is encoded in the OP-FP + major opcode space and both the source and destination are floating-point registers. The `xs2` field + encodes the datatype of the source, and the `fmt` field encodes the datatype of the destination. + `fcvt.d.s` will never round. +assembly: fd, fs1, rm +encoding: + match: 010000100000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.w.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.w.yaml new file mode 100644 index 000000000000..29a67e94b3b4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.w.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.d.w +long_name: Floating-Point Convert Word to Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fcvt.d.w` instruction converts a 32-bit signed integer, in integer register `xs1` into a double-precision + floating-point number in floating-point register `fd`. Note `fcvt.d.w` always produces an exact result and is + unaffected by rounding mode. +assembly: fd, xs1, rm +encoding: + match: 110100100000-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.wu.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.wu.yaml new file mode 100644 index 000000000000..3033f3f71bd9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.d.wu.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.d.wu +long_name: Floating-Point Convert Unsigned Word to Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fcvt.d.wu` instruction converts a 32-bit unsigned integer in integer register `xs1` into a double-precision + floating-point number in floating-point register `fd`. Note `fcvt.d.wu` always produces an exact result and is + unaffected by rounding mode. +assembly: fd, xs1, rm +encoding: + match: 110100100001-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvt.l.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.l.d.yaml new file mode 100644 index 000000000000..9cb72635652b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.l.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.l.d +long_name: Floating-Point Convert Double-Precision to Long +definedBy: + allOf: + - xlen: 64 + - extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fcvt.l.d` instruction converts a double-precision floating-point number in floating-point register `fs1` + to a signed 64-bit integer, in integer register `xd`. +assembly: xd, fs1, rm +encoding: + match: 110000100010-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvt.lu.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.lu.d.yaml new file mode 100644 index 000000000000..3fdd08c2a6bf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.lu.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.lu.d +long_name: Floating-Point Convert Double-Precision to Unsigned Long +definedBy: + allOf: + - xlen: 64 + - extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fcvt.lu.d` instruction converts a double-precision floating-point number in floating-point register `fs1` + to an unsigned 64-bit integer, in integer register `xd`. +assembly: xd, fs1, rm +encoding: + match: 110000100011-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvt.s.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.s.d.yaml new file mode 100644 index 000000000000..51a21c9cbba5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.s.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.s.d +long_name: Floating-Point Convert Double-Precision to Single-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fcvt.s.d` instruction converts a double-precision floating-point number to a single-precision floating-point + number. This is encoded in the OP-FP major opcode space and both the source and destination are floating-point + registers. The `xs2` field encodes the datatype of the source, and the `fmt` field encodes the datatype of the + destination. `fcvt.s.d` rounds according to the `rm` field. +assembly: fd, fs1, rm +encoding: + match: 010000000001-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvt.w.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.w.d.yaml new file mode 100644 index 000000000000..cb5e6749d554 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.w.d.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.w.d +long_name: Floating-Point Convert Double-Precision to Word +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fcvt.w.d` instruction converts a double-precision floating-point number in floating-point register `fs1` to a + signed 32-bit integer, in integer register `xd`. +assembly: xd, fs1, rm +encoding: + match: 110000100000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvt.wu.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.wu.d.yaml new file mode 100644 index 000000000000..6666b5eea703 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvt.wu.d.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.wu.d +long_name: Floating-Point Convert Double-Precision to Unsigned Word +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fcvt.wu.d` instruction converts a double-precision floating-point number in floating-point register `fs1` to an + unsigned 32-bit integer, in integer register `xd`. +assembly: xd, fs1, rm +encoding: + match: 110000100001-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fcvtmod.w.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fcvtmod.w.d.yaml new file mode 100644 index 000000000000..14346f3aa7ee --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fcvtmod.w.d.yaml @@ -0,0 +1,42 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvtmod.w.d +long_name: Floating-Point Convert Double-Precision to Word with Modulo +description: | + The `fcvtmod.w.d` instruction always rounds towards zero. Bits 31:0 are taken from the rounded, unbounded + two's complement result, then sign-extended to XLEN bits and written to integer register `xd`. ±∞ and + NaN are converted to zero. + + Floating-point exception flags are raised the same as they would be for `fcvt.w.d` with the same input + operand. + + This instruction is only provided if the D extension is implemented. It is encoded like `fcvt.w.d`, but + with the `xs2` field set to 8 and the `rm` field set to 1 (RTZ). Other `rm` values are reserved. +definedBy: + extension: + allOf: + - name: D + - name: Zfa +assembly: xd, fs1, rm +encoding: + match: 110000101000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + not: [0, 2, 3, 4, 5, 6, 7] + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fdiv.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fdiv.d.yaml new file mode 100644 index 000000000000..ebf84d909fb8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fdiv.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fdiv.d +long_name: Floating-Point Divide Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fdiv.d` instruction performs the double-precision floating-point division of `fs1` by `fs2`. It is defined analogously + to its single-precision counterpart, but operates on double-precision operands and produces double-precision results. +assembly: fd, fs1, fs2, rm +encoding: + match: 0001101------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/feq.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/feq.d.yaml new file mode 100644 index 000000000000..6ba2c11df664 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/feq.d.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: feq.d +long_name: Floating-Point Equal Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `feq.d` instruction writes 1 to `xd` if `fs1` and `fs2` are equal, and 0 otherwise. It is defined analogously to its + single-precision counterpart, but operates on double-precision operands. +assembly: xd, fs1, fs2 +encoding: + match: 1010001----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fld.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fld.yaml new file mode 100644 index 000000000000..38bb2e354e90 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fld.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fld +long_name: Floating-Point Load Double-Precision +definedBy: + extension: + name: D +description: | + The `fld` instruction loads a double-precision floating-point value from memory into floating-point + register `fd`. It is guaranteed to execute atomically if the effective address is naturally aligned + and XLEN≥64. It doesn't modify the bits being transferred; in particular, the payloads of non-canonical + NaNs are preserved. +assembly: fd, imm(xs1) +encoding: + match: "-----------------011-----0000111" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fle.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fle.d.yaml new file mode 100644 index 000000000000..9e1bb8060861 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fle.d.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fle.d +long_name: Floating-Point Less Than or Equal Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fle.d` instruction writes 1 to `xd` if `fs1` is less than or equal to `fs2`, and 0 otherwise. It is defined + analogously to its single-precision counterpart, but operates on double-precision operands. +assembly: xd, fs1, fs2 +encoding: + match: 1010001----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fleq.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fleq.d.yaml new file mode 100644 index 000000000000..23e45d15ead2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fleq.d.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fleq.d +long_name: Floating-Point Less Than or Equal Quiet Double-Precision +description: | + The `fleq.d` instruction is defined like the `fle.d` instruction, except that quiet NaN inputs do not cause + the invalid operation exception flag to be set. +definedBy: + extension: + allOf: + - name: D + - name: Zfa +assembly: xd, fs1, fs2 +encoding: + match: 1010001----------100-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fli.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fli.d.yaml new file mode 100644 index 000000000000..619e33d3ccd2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fli.d.yaml @@ -0,0 +1,32 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fli.d +long_name: Floating-Point Load Immediate Double-Precision +description: | + The `fli.d` instruction instruction loads one of 32 double-precision floating-point constants, encoded in the `xs1` + field, into floating-point register `fd`. `fli.d` is encoded like `fli.s`, but with `fmt` set to D. +definedBy: + extension: + allOf: + - name: D + - name: Zfa +assembly: fd, xs1 +encoding: + match: 111100100001-----000-----1010011 + variables: + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/flt.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/flt.d.yaml new file mode 100644 index 000000000000..67ac560254aa --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/flt.d.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: flt.d +long_name: Floating-Point Less Than Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `flt.d` instruction writes 1 to `xd` if `fs1` is less than `fs2`, and 0 otherwise. It is defined analogously to its + single-precision counterpart, but operates on double-precision operands. +assembly: xd, fs1, fs2 +encoding: + match: 1010001----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fltq.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fltq.d.yaml new file mode 100644 index 000000000000..7441599806c0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fltq.d.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fltq.d +long_name: Floating-Point Less Than Quiet Double-Precision +description: | + The `fltq.d` instruction is defined like the `flt.d` instruction, except that quiet NaN inputs do not cause + the invalid operation exception flag to be set. +definedBy: + extension: + allOf: + - name: D + - name: Zfa +assembly: xd, fs1, fs2 +encoding: + match: 1010001----------101-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fmadd.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fmadd.d.yaml new file mode 100644 index 000000000000..c514693016c3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fmadd.d.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmadd.d +long_name: Floating-Point Multiply-Add Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fmadd.d` instruction multiplies the values in `fs1` and `fs2`, adds the value in `fs3`, and writes the final result to `fd`. +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----01------------------1000011" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fmax.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fmax.d.yaml new file mode 100644 index 000000000000..4ac06c2a1b14 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fmax.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmax.d +long_name: Floating-Point Maximum-Number Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fmax.d` instruction writes larger of `fs1` and `fs2` to `fd`. For the purposes of this instruction, + the value `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is + the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs + set the invalid operation exception flag, even when the result is not NaN. +assembly: fd, fs1, fs2 +encoding: + match: 0010101----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fmaxm.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fmaxm.d.yaml new file mode 100644 index 000000000000..cef292bb4e14 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fmaxm.d.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmaxm.d +long_name: Floating-Point Maximum-Number NaN Double-Precision +description: | + The `fmaxm.d` instruction writes larger of `fs1` and `fs2` to `fd`. It is defined like `fmax.d` instruction, except + that if either input is NaN, the result is the canonical NaN. +definedBy: + extension: + allOf: + - name: D + - name: Zfa +assembly: fd, fs1, fs2 +encoding: + match: 0010101----------011-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fmin.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fmin.d.yaml new file mode 100644 index 000000000000..82c344704d53 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fmin.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmin.d +long_name: Floating-Point Minimum-Number Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fmin.d` instruction writes smaller of `fs1` and `fs2` to `fd`. For the purposes of this instruction, + the value `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is + the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs + set the invalid operation exception flag, even when the result is not NaN. +assembly: fd, fs1, fs2 +encoding: + match: 0010101----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fminm.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fminm.d.yaml new file mode 100644 index 000000000000..79788da35013 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fminm.d.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fminm.d +long_name: Floating-Point Minimum-Number NaN Double-Precision +description: | + The `fminm.d` instruction writes smaller of `fs1` and `fs2` to `fd`. It is defined like `fmin.d` instruction, except + that if either input is NaN, the result is the canonical NaN. +definedBy: + extension: + allOf: + - name: D + - name: Zfa +assembly: fd, fs1, fs2 +encoding: + match: 0010101----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fmsub.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fmsub.d.yaml new file mode 100644 index 000000000000..0e3b5bd18981 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fmsub.d.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmsub.d +long_name: Floating-Point Multiply-Subtract Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fmsub.d` instruction multiplies the values in `fs1` and `fs2`, subtracts the value in `fs3`, and writes the final result to `fd`. +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----01------------------1000111" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fmul.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fmul.d.yaml new file mode 100644 index 000000000000..309c029c1afe --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fmul.d.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmul.d +long_name: Floating-Point Multiply Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fmul.d` instruction performs the double-precision floating-point multiplication between `fs1` and `fs2`. + It is defined analogously to its single-precision counterpart, but operates on double-precision operands and + produces double-precision results. +assembly: fd, fs1, fs2, rm +encoding: + match: 0001001------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fmv.d.x.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fmv.d.x.yaml new file mode 100644 index 000000000000..fc5f255c1df4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fmv.d.x.yaml @@ -0,0 +1,32 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmv.d.x +definedBy: + allOf: + - xlen: 64 + - extension: + name: D +long_name: Floating-Point Move Double-Precision from Integer Register +description: | + The `fmv.d.x` instruction moves the double-precision value encoded in `IEEE 754-2008` standard encoding from the integer + register `xs1` to the floating-point register `fd`. +assembly: fd, xs1 +encoding: + match: 111100100000-----000-----1010011 + variables: + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fmv.x.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fmv.x.d.yaml new file mode 100644 index 000000000000..96d521fd9e0b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fmv.x.d.yaml @@ -0,0 +1,32 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmv.x.d +definedBy: + allOf: + - xlen: 64 + - extension: + name: D +long_name: Floating-Point Move Double-Precision to Integer Register +description: | + The `fmv.x.d` instruction moves the double-precision value in floating-point register `fs1` to a representation in + `IEEE 754-2008` standard encoding in integer register `xd`. +assembly: xd, fs1 +encoding: + match: 111000100000-----000-----1010011 + variables: + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fmvh.x.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fmvh.x.d.yaml new file mode 100644 index 000000000000..5db36aa56938 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fmvh.x.d.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmvh.x.d +long_name: Floating-Point Move High Half from Double-Precision Register to Integer Register +description: | + The `fmvh.x.d` instruction moves bits 63:32 of floating-point register `fs1` into integer register `xd`. `fmvh.x.d` + is used in conjunction with the existing `fmv.x.w` instruction to move a double-precision floating-point number to a + pair of integer-registers. +definedBy: + allOf: + - xlen: 32 + - extension: + allOf: + - name: D + - name: Zfa +assembly: xd, fs1 +encoding: + match: 111000100001-----000-----1010011 + variables: + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fmvp.d.x.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fmvp.d.x.yaml new file mode 100644 index 000000000000..51ce0c7f2521 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fmvp.d.x.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmvp.d.x +long_name: Floating-Point Move Pair from Integer Registers to Double-Precision Register +description: | + The `fmvp.d.x` instruction moves a double-precision number from a pair of integer registers into a floating-point + register. Integer registers `xs1` and `xs2` supply bits 31:0 and 63:32, respectively; the result is written to + floating-point register `fd`. +definedBy: + allOf: + - xlen: 32 + - extension: + allOf: + - name: D + - name: Zfa +assembly: fd, xs1, xs2 +encoding: + match: 1011001----------000-----1010011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fnmadd.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fnmadd.d.yaml new file mode 100644 index 000000000000..0f4aa35c6325 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fnmadd.d.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fnmadd.d +long_name: Floating-Point Negate-Multiply-Add Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fnmadd.d` instruction multiplies the values in `fs1` and `fs2`, negates the product, subtracts the value in `fs3`, and + writes the final result to `fd`. +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----01------------------1001111" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fnmsub.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fnmsub.d.yaml new file mode 100644 index 000000000000..1b545be8141e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fnmsub.d.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fnmsub.d +long_name: Floating-Point Negate-Multiply-Subtract Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fnmsub.d` instruction multiplies the values in `fs1` and `fs2`, negates the product, adds the value in `fs3`, and + writes the final result to `fd`. +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----01------------------1001011" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fround.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fround.d.yaml new file mode 100644 index 000000000000..ff586ecc6c71 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fround.d.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fround.d +long_name: Floating-Point Round Double-Precision +description: | + The `fround.d` instruction rounds the double-precision floating-point number in floating-point register + `fs1` to an integer, according to the rounding mode specified in the instruction's `rm` field. It then writes + that integer, represented as a double-precision floating-point number, to floating-point register `fd`. Zero + and infinite inputs are copied to `fd` unmodified. Signaling NaN inputs cause the invalid operation + exception flag to be set; no other exception flags are set. `fround.d` is encoded like `fcvt.d.s`, but with + `xs2` set to 4. +definedBy: + extension: + allOf: + - name: D + - name: Zfa +assembly: fd, fs1, rm +encoding: + match: 010000100100-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/froundnx.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/froundnx.d.yaml new file mode 100644 index 000000000000..0fddc100c6ce --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/froundnx.d.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: froundnx.d +long_name: Floating-Point Round-to-Integer Inexact Double-Precision +description: | + The `froundnx.d` instruction is defined in the same way as `fround.d`, but it also sets the inexact exception flag if the input + differs from the rounded result and is not NaN. `froundnx.d` is encoded like `fcvt.d.s`, but with `xs2` set to 5. +definedBy: + extension: + allOf: + - name: D + - name: Zfa +assembly: fd, fs1, rm +encoding: + match: 010000100101-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fsd.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fsd.yaml new file mode 100644 index 000000000000..8870dd2b0901 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fsd.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsd +long_name: Floating-Point Store Double-Precision +definedBy: + extension: + name: D +description: | + The `fsd` instruction stores a double-precision value from the floating-point registers to memory. It is guaranteed to execute + atomically if the effective address is naturally aligned and XLEN≥64. It doesn't modify the bits being transferred; in particular, + the payloads of non-canonical NaNs are preserved. +assembly: fs2, imm(xs1) +encoding: + match: "-----------------011-----0100111" + variables: + - name: imm + location: 31-25|11-7 + - name: fs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fsgnj.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fsgnj.d.yaml new file mode 100644 index 000000000000..29f4d2e22d60 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fsgnj.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsgnj.d +long_name: Floating-Point Sign-Inject Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fsgnj.d` instruction produces a result that takes all bits except the sign bit from `fs1`. + The result's sign bit is taken from `fs2`'s sign bit, and the result is written to the destination + register `fd`. Sign-injection instructions do not set floating-point exception flags, nor do they + canonicalize NaNs. +assembly: fd, fs1, fs2 +encoding: + match: 0010001----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fsgnjn.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fsgnjn.d.yaml new file mode 100644 index 000000000000..5cac029b437b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fsgnjn.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsgnjn.d +long_name: Floating-Point Sign-Inject Negate Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fsgnjn.d` instruction produces a result that takes all bits except the sign bit from `fs1`. + The result's sign bit is opposite of `fs2`'s sign bit, and the result is written to the destination + register `fd`. Sign-injection instructions do not set floating-point exception flags, nor do they + canonicalize NaNs. +assembly: fd, fs1, fs2 +encoding: + match: 0010001----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fsgnjx.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fsgnjx.d.yaml new file mode 100644 index 000000000000..b52432a14355 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fsgnjx.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsgnjx.d +long_name: Floating-Point Sign-Inject XOR Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fsgnjx.d` instruction produces a result that takes all bits except the sign bit from `fs1`. + The result's sign bit is the XOR of sign bits of `fs1` and `fs2`, and the result is written to + the destination register `fd`. Sign-injection instructions do not set floating-point exception + flags, nor do they canonicalize NaNs. +assembly: fd, fs1, fs2 +encoding: + match: 0010001----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fsqrt.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fsqrt.d.yaml new file mode 100644 index 000000000000..38485029683e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fsqrt.d.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsqrt.d +long_name: Floating-Point Square Root Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fsqrt.d` instruction computes the square root of `fs1` and result is written in `fd`. It is defined + analogously to its single-precision counterpart, but operates on double-precision operands and produces + double-precision results. +assembly: fd, fs1, rm +encoding: + match: 010110100000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/D/fsub.d.yaml b/pkg/ifuzz/riscv64/gen/inst/D/fsub.d.yaml new file mode 100644 index 000000000000..8210d4728224 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/D/fsub.d.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsub.d +long_name: Floating-Point Subtract Double-Precision +definedBy: + extension: + oneOf: + - name: D + - name: Zdinx +description: | + The `fsub.d` instruction is analogous to `fsub.s` and performs double-precision floating-point subtraction between + `fs1` and `fs2` and writes the final result to `fd`. +assembly: fd, fs1, fs2, rm +encoding: + match: 0000101------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fadd.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fadd.s.yaml new file mode 100644 index 000000000000..02f8c3ad7247 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fadd.s.yaml @@ -0,0 +1,63 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fadd.s +long_name: Floating-Point Add Single-Precision +description: | + The `fadd.s` instruction performs single-precision floating-point addition of `fs1` and `fs2` + and writes the final result to `fd`. +definedBy: + extension: + name: F +assembly: fd, fs1, fs2, rm +encoding: + match: 0000000------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + RoundingMode mode = rm_to_mode(rm, $encoding); + f[fd] = f32_add(f[fs1], f[fs2], mode); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_32b = F_or_X_S(rs1); + let rs2_val_32b = F_or_X_S(rs2); + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op { + FADD_S => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b), + FSUB_S => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b), + FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b), + FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b) + }; + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_32b; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fclass.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fclass.s.yaml new file mode 100644 index 000000000000..6ee4f7a8363b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fclass.s.yaml @@ -0,0 +1,90 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fclass.s +long_name: Floating-Point Classify Single-Precision +description: | + The `fclass.s` instruction examines the value in floating-point register `fs1` and writes to integer register `xd` + a 10-bit mask that indicates the class of the floating-point number. + + The format of the mask is described in the table below. The corresponding bit in `xd` will be set if the property + is true and clear otherwise. All other bits in `xd` are cleared. Note that exactly one bit in `xd` will be set. + `fclass.s` does not set the floating-point exception flags. + + .Format of result of `fclass` instruction. + [%autowidth,float="center",align="center",cols="^,<",options="header",] + |=== + |_xd_ bit |Meaning + |0 |_fs1_ is latexmath:[$-\infty$]. + |1 |_fs1_ is a negative normal number. + |2 |_fs1_ is a negative subnormal number. + |3 |_fs1_ is latexmath:[$-0$]. + |4 |_fs1_ is latexmath:[$+0$]. + |5 |_fs1_ is a positive subnormal number. + |6 |_fs1_ is a positive normal number. + |7 |_fs1_ is latexmath:[$+\infty$]. + |8 |_fs1_ is a signaling NaN. + |9 |_fs1_ is a quiet NaN. + |=== + +definedBy: + extension: + name: F +assembly: xd, fs1 +encoding: + match: 111000000000-----001-----1010011 + variables: + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + check_f_ok($encoding); + + Bits<32> sp_value = f[fs1][31:0]; + + if (is_sp_neg_inf?(sp_value)) { + X[xd] = 1 << 0; + } else if (is_sp_neg_norm?(sp_value)) { + X[xd] = 1 `<< 1; + } else if (is_sp_neg_subnorm?(sp_value)) { + X[xd] = 1 `<< 2; + } else if (is_sp_neg_zero?(sp_value)) { + X[xd] = 1 `<< 3; + } else if (is_sp_pos_zero?(sp_value)) { + X[xd] = 1 `<< 4; + } else if (is_sp_pos_subnorm?(sp_value)) { + X[xd] = 1 `<< 5; + } else if (is_sp_pos_norm?(sp_value)) { + X[xd] = 1 `<< 6; + } else if (is_sp_pos_inf?(sp_value)) { + X[xd] = 1 `<< 7; + } else if (is_sp_signaling_nan?(sp_value)) { + X[xd] = 1 `<< 8; + } else { + assert(is_sp_quiet_nan?(sp_value), "Unexpected SP value"); + X[xd] = 1 `<< 9; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_X = X(rs1); + let rd_val_S = rs1_val_X [31..0]; + F(rd) = nan_box (rd_val_S); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fcvt.l.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.l.s.yaml new file mode 100644 index 000000000000..a627108db4a7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.l.s.yaml @@ -0,0 +1,56 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.l.s +long_name: Floating-Point Convert Single-Precision to Long +description: | + The `fcvt.l.s` instruction converts a floating-point number in floating-point register `fs1` to a signed + 64-bit integer, in integer register `xd`. +definedBy: + allOf: + - xlen: 64 + - extension: + name: F +assembly: xd, fs1, rm +encoding: + match: 110000000010-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fcvt.lu.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.lu.s.yaml new file mode 100644 index 000000000000..219793f14194 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.lu.s.yaml @@ -0,0 +1,56 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.lu.s +long_name: Floating-Point Convert Single-Precision to Unsigned Long +description: | + The `fcvt.lu.s` instruction converts a floating-point number in floating-point register `fs1` to a unsigned + 64-bit integer, in integer register `xd`. +definedBy: + allOf: + - xlen: 64 + - extension: + name: F +assembly: xd, fs1, rm +encoding: + match: 110000000011-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.l.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.l.yaml new file mode 100644 index 000000000000..d60ba2782977 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.l.yaml @@ -0,0 +1,56 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.s.l +long_name: Floating-Point Convert Long to Single-Precision +description: | + The `fcvt.s.l` instruction converts a 64-bit signed integer in integer register `xs1` into a floating-point + number in floating-point register `fd`. +definedBy: + allOf: + - xlen: 64 + - extension: + name: F +assembly: fd, xs1, rm +encoding: + match: 110100000010-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.lu.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.lu.yaml new file mode 100644 index 000000000000..253628d7d28e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.lu.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.s.lu +long_name: Floating-Point Convert Unsigned Long to Single-Precision +description: | + The `fcvt.s.lu` instruction converts a 64-bit unsigned integer into a single-precision floating-point number. +definedBy: + allOf: + - xlen: 64 + - extension: + name: F +assembly: fd, xs1, rm +encoding: + match: 110100000011-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.w.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.w.yaml new file mode 100644 index 000000000000..8f8df21c7b94 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.w.yaml @@ -0,0 +1,67 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.s.w +long_name: Floating-Point Convert Word to Single-Precision +description: | + The `fcvt.s.w` instruction converts a 32-bit signed integer in integer register `xs1` into + a floating-point number in floating-point register `fd`. + + All floating-point to integer and integer to floating-point conversion instructions round + according to the `rm` field. + + A floating-point register can be initialized to floating-point positive zero using + `fcvt.s.w fd, x0`, which will never set any exception flags. + + All floating-point conversion instructions set the Inexact exception flag if the rounded + result differs from the operand value and the Invalid exception flag is not set. +definedBy: + extension: + name: F +assembly: fd, xs1, rm +encoding: + match: 110100000000-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + check_f_ok($encoding); + RoundingMode rounding_mode = rm_to_mode(rm, $encoding); + f[fd] = i32_to_f32(X[xs1], rounding_mode); + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.wu.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.wu.yaml new file mode 100644 index 000000000000..e1c9002a8b10 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.s.wu.yaml @@ -0,0 +1,66 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.s.wu +long_name: Floating-Point Convert Unsigned Word to Single-Precision +description: | + The `fcvt.s.wu` instruction converts a 32-bit unsigned integer in integer register `xs1` into + a floating-point number in floating-point register `fd`. + + All floating-point to integer and integer to floating-point conversion instructions round + according to the `rm` field. + + A floating-point register can be initialized to floating-point positive zero using + `fcvt.s.w rd, x0`, which will never set any exception flags. + + All floating-point conversion instructions set the Inexact exception flag if the rounded + result differs from the operand value and the Invalid exception flag is not set. +definedBy: + extension: + name: F +assembly: fd, xs1, rm +encoding: + match: 110100000001-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + RoundingMode rounding_mode = rm_to_mode(rm, $encoding); + f[fd] = ui32_to_f32(X[xs1], rounding_mode); + mark_f_state_dirty(); +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fcvt.w.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.w.s.yaml new file mode 100644 index 000000000000..352a83b7e972 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.w.s.yaml @@ -0,0 +1,85 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.w.s +long_name: Floating-Point Convert Single-Precision to Word +description: | + The `fcvt.w.s` instruction converts a floating-point number in floating-point register `fs1` to a + signed 32-bit integer in integer register `xd`. For XLEN >32, `fcvt.w.s` sign-extends the 32-bit + result to the destination register width. + + If the rounded result is not representable as a 32-bit signed integer, it is clipped to the + nearest value and the invalid flag is set. + + The range of valid inputs and behavior for invalid inputs are: + + [separator="!"] + !=== + ! ! Value + + h! Minimum valid input (after rounding) ! `-2^31` + h! Maximum valid input (after rounding) ! `2^31 - 1` + h! Output for out-of-range negative input ! `-2^31` + h! Output for `-∞` ! `-2^31` + h! Output for out-of-range positive input ! `2^31 - 1` + h! Output for `+∞` for `NaN` ! `2^31 - 1` + !=== + + All floating-point to integer and integer to floating-point conversion instructions round + according to the `rm` field. + + A floating-point register can be initialized to floating-point positive zero using + `fcvt.s.w xd, x0`, which will never set any exception flags. + + All floating-point conversion instructions set the Inexact exception flag if the rounded + result differs from the operand value and the Invalid exception flag is not set. + +definedBy: + extension: + name: F +assembly: xd, fs1, rm +encoding: + match: 110000000000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + RoundingMode rounding_mode = rm_to_mode(rm, $encoding); + X[xd] = f32_to_i32(f[fs1], rounding_mode); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fcvt.wu.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.wu.s.yaml new file mode 100644 index 000000000000..8c3f9c840140 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fcvt.wu.s.yaml @@ -0,0 +1,83 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.wu.s +long_name: Floating-Point Convert Single-Precision to Unsigned Word +description: | + Converts a floating-point number in floating-point register `fs1` to an unsigned 32-bit integer + in integer register `xd`. For XLEN >32, `fcvt.wu.s` sign-extends the 32-bit result to the + destination register width. + + If the rounded result is not representable as a 32-bit unsigned integer, it is clipped to the + nearest value and the invalid flag is set. + + The range of valid inputs and behavior for invalid inputs are: + + [separator="!"] + !=== + ! ! Value + + h! Minimum valid input (after rounding) ! `0` + h! Maximum valid input (after rounding) ! `2^32 - 1` + h! Output for out-of-range negative input ! `0` + h! Output for `-∞` ! `0` + h! Output for out-of-range positive input ! `2^32 - 1` + h! Output for `+∞` for `NaN` ! `2^32 - 1` + !=== + + All floating-point to integer and integer to floating-point conversion instructions round + according to the `rm` field. + + A floating-point register can be initialized to floating-point positive zero using + `fcvt.s.w xd, x0`, which will never set any exception flags. + + All floating-point conversion instructions set the Inexact exception flag if the rounded + result differs from the operand value and the Invalid exception flag is not set. +definedBy: + extension: + name: F +assembly: xd, fs1, rm +encoding: + match: 110000000001-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + RoundingMode rounding_mode = rm_to_mode(rm, $encoding); + X[xd] = f32_to_ui32(f[fs1], rounding_mode); +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fdiv.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fdiv.s.yaml new file mode 100644 index 000000000000..bdab30c21778 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fdiv.s.yaml @@ -0,0 +1,60 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fdiv.s +long_name: Floating-Point Divide Single-Precision +description: | + The `fdiv.s` instruction performs the single-precision floating-point division of `fs1` by `fs2`, and + writes the final result to `fd`. +definedBy: + extension: + name: F +assembly: fd, fs1, fs2, rm +encoding: + match: 0001100------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_32b = F_or_X_S(rs1); + let rs2_val_32b = F_or_X_S(rs2); + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op { + FADD_S => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b), + FSUB_S => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b), + FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b), + FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b) + }; + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_32b; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/feq.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/feq.s.yaml new file mode 100644 index 000000000000..496dad1a2834 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/feq.s.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: feq.s +long_name: Floating-Point Equal Single-Precision +description: | + The `feq.s` instruction writes 1 to `xd` if `fs1` and `fs2` are equal, and 0 otherwise. + If either operand is NaN, the result is 0 (not equal). If either operand is a signaling NaN, + the invalid flag is set. Positive zero is considered equal to negative zero. + +definedBy: + extension: + name: F +assembly: xd, fs1, fs2 +encoding: + match: 1010000----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + + Bits<32> sp_value_a = f[fs1][31:0]; + Bits<32> sp_value_b = f[fs1][31:0]; + + if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) { + if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) { + set_fp_flag(FpFlag::NV); + } + X[xd] = 0; + } else { + X[xd] = ( + (sp_value_a == sp_value_b) + || ((sp_value_a | sp_value_b)[30:0] == 0) # pos 0 is equal to neg zero + ) ? 1 : 0; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_or_X_S(rs1); + let rs2_val_S = F_or_X_S(rs2); + + let (fflags, rd_val) : (bits_fflags, bool) = + riscv_f32Le (rs1_val_S, rs2_val_S); + + accrue_fflags(fflags); + X(rd) = zero_extend(bool_to_bits(rd_val)); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fle.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fle.s.yaml new file mode 100644 index 000000000000..423401445717 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fle.s.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fle.s +long_name: Floating-Point Less Than or Equal Single-Precision +description: | + The `fle.s` instruction writes 1 to `xd` if `fs1` is less than or equal to `fs2`, and 0 otherwise. + If either operand is NaN, the result is 0 (not equal). If either operand is a NaN (signaling or quiet), + the invalid flag is set. Positive zero and negative zero are considered equal. + +definedBy: + extension: + name: F +assembly: xd, fs1, fs2 +encoding: + match: 1010000----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + + Bits<32> sp_value_a = f[fs1][31:0]; + Bits<32> sp_value_b = f[fs2][31:0]; + + if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) { + if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) { + set_fp_flag(FpFlag::NV); + } + X[xd] = 0; + } else { + X[xd] = ( + (sp_value_a == sp_value_b) + || ((sp_value_a | sp_value_b)[30:0] == 0) # pos 0 is equal to neg zero + ) ? 1 : 0; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_or_X_S(rs1); + let rs2_val_S = F_or_X_S(rs2); + + let (fflags, rd_val) : (bits_fflags, bool) = + riscv_f32Le (rs1_val_S, rs2_val_S); + + accrue_fflags(fflags); + X(rd) = zero_extend(bool_to_bits(rd_val)); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fleq.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fleq.s.yaml new file mode 100644 index 000000000000..9e2e734bd9bb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fleq.s.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fleq.s +long_name: Floating-Point Less Than or Equal Quiet Single-Precision +description: | + The `fleq.s` instruction is defined like the `fle.s` instruction, except that quiet NaN inputs do + not cause the invalid operation exception flag to be set. +definedBy: + extension: + name: Zfa +assembly: xd, fs1, fs2 +encoding: + match: 1010000----------100-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_S(rs1); + let rs2_val_S = F_S(rs2); + + let (fflags, rd_val) : (bits_fflags, bool) = + riscv_f32Le_quiet (rs1_val_S, rs2_val_S); + + accrue_fflags(fflags); + X(rd) = zero_extend(bool_to_bits(rd_val)); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/flt.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/flt.s.yaml new file mode 100644 index 000000000000..80c470d24a3d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/flt.s.yaml @@ -0,0 +1,70 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: flt.s +long_name: Floating-Point Less Than Single-Precision +description: | + The `flt.s` instruction writes 1 to `xd` if `fs1` is less than `fs2`, and 0 otherwise. + If either operand is NaN, the result is 0 (not equal). If either operand is a NaN + (signaling or quiet), the invalid flag is set. + +definedBy: + extension: + name: F +assembly: xd, fs1, fs2 +encoding: + match: 1010000----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + + Bits<32> sp_value_a = f[fs1][31:0]; + Bits<32> sp_value_b = f[fs2][31:0]; + + if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) { + set_fp_flag(FpFlag::NV); + X[xd] = 0; + } else { + Boolean sign_a = sp_value_a[31] == 1; + Boolean sign_b = sp_value_b[31] == 1; + + Boolean a_lt_b = + (sign_a != sign_b) + ? (sign_a && ((sp_value_a[30:0] | sp_value_b[30:0]) != 0)) # opposite sign, a is negative. a is less than b as long as both are not zero + : ((sp_value_a != sp_value_b) && (sign_a != (sp_value_a < sp_value_b))); + X[xd] = a_lt_b ? 1 : 0; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_or_X_S(rs1); + let rs2_val_S = F_or_X_S(rs2); + + let (fflags, rd_val) : (bits_fflags, bool) = + riscv_f32Le (rs1_val_S, rs2_val_S); + + accrue_fflags(fflags); + X(rd) = zero_extend(bool_to_bits(rd_val)); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fltq.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fltq.s.yaml new file mode 100644 index 000000000000..0848786cf7ff --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fltq.s.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fltq.s +long_name: Floating-Point Less Than Quiet Single-Precision +description: | + The `fltq.s` is defined like the `flt.s` instruction, except that quiet NaN inputs do not cause + the invalid operation exception flag to be set. +definedBy: + extension: + name: Zfa +assembly: xd, fs1, fs2 +encoding: + match: 1010000----------101-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_S(rs1); + let rs2_val_S = F_S(rs2); + + let (fflags, rd_val) : (bits_fflags, bool) = + riscv_f32Lt_quiet (rs1_val_S, rs2_val_S); + + accrue_fflags(fflags); + X(rd) = zero_extend(bool_to_bits(rd_val)); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/flw.yaml b/pkg/ifuzz/riscv64/gen/inst/F/flw.yaml new file mode 100644 index 000000000000..1c73596451ea --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/flw.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: flw +long_name: Floating-Point Load Single-Precision +description: | + The `flw` instruction loads a single-precision floating-point value from memory at address `xs1` + `imm` into floating-point register `fd`. + It does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. + +definedBy: + extension: + name: F +assembly: fd, imm(xs1) +encoding: + match: "-----------------010-----0000111" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + + XReg virtual_address = X[xs1] + $signed(imm); + + Bits<32> sp_value = read_memory<32>(virtual_address, $encoding); + + if (implemented?(ExtensionName::D)) { + f[fd] = nan_box<32, 64>(sp_value); + } else { + f[fd] = sp_value; + } + + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let (aq, rl, res) = (false, false, false); + match (width) { + BYTE => { handle_illegal(); RETIRE_FAIL }, + HALF => + process_fload16(rd, vaddr, mem_read(Read(Data), addr, 2, aq, rl, res)), + WORD => + process_fload32(rd, vaddr, mem_read(Read(Data), addr, 4, aq, rl, res)), + DOUBLE if sizeof(flen) >= 64 => + process_fload64(rd, vaddr, mem_read(Read(Data), addr, 8, aq, rl, res)), + _ => report_invalid_width(__FILE__, __LINE__, width, "floating point load"), + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fmadd.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fmadd.s.yaml new file mode 100644 index 000000000000..e84605599530 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fmadd.s.yaml @@ -0,0 +1,63 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmadd.s +long_name: Floating-Point Multiply-Add Single-Precision +description: | + The `fmadd.s` multiplies the values in `fs1` and `fs2`, adds the value in `fs3`, and writes the final result to `fd`. +definedBy: + extension: + name: F +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----00------------------1000011" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_32b = F_or_X_S(rs1); + let rs2_val_32b = F_or_X_S(rs2); + let rs3_val_32b = F_or_X_S(rs3); + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_32b) : (bits(5), bits(32)) = + match op { + FMADD_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b), + FMSUB_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, negate_S (rs3_val_32b)), + FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b), + FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b)) + }; + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_32b; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fmax.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fmax.s.yaml new file mode 100644 index 000000000000..04c622af9e7a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fmax.s.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmax.s +long_name: Floating-Point Maximum-Number Single-Precision +description: | + The `fmax.s` instruction writes larger of `fs1` and `fs2` to `fd`. For the purposes of this instruction, + the value `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is + the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs + set the invalid operation exception flag, even when the result is not NaN. + + [NOTE] + ==== + Note that in version 2.2 of the F extension, the `fmin.s` and `fmax.s` instructions were amended to implement + the proposed _IEEE 754-201x_ `minimumNumber` and `maximumNumber` operations, rather than the _IEEE 754-2008_ + _minNum_ and _maxNum_ operations. These operations differ in their handling of signaling NaNs. + ==== +definedBy: + extension: + name: F +assembly: fd, fs1, fs2 +encoding: + match: 0010100----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_or_X_S(rs1); + let rs2_val_S = F_or_X_S(rs2); + + let (fflags, rd_val) : (bits_fflags, bool) = + riscv_f32Le (rs1_val_S, rs2_val_S); + + accrue_fflags(fflags); + X(rd) = zero_extend(bool_to_bits(rd_val)); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fmin.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fmin.s.yaml new file mode 100644 index 000000000000..283b3ba963df --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fmin.s.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmin.s +long_name: Floating-Point Minimum-Number Single-Precision +description: | + The `fmin.s` instruction writes smaller of `fs1` and `fs2` to `fd`. For the purposes of this instruction, + the value `-0.0` is considered to be less than the value `+0.0`. If both inputs are NaNs, the result is + the canonical NaN. If only one operand is a NaN, the result is the non-NaN operand. Signaling NaN inputs + set the invalid operation exception flag, even when the result is not NaN. + + [NOTE] + ==== + Note that in version 2.2 of the F extension, the `fmin.s` and `fmax.s` instructions were amended to implement + the proposed _IEEE 754-201x_ `minimumNumber` and `maximumNumber` operations, rather than the _IEEE 754-2008_ + _minNum_ and _maxNum_ operations. These operations differ in their handling of signaling NaNs. + ==== +definedBy: + extension: + name: F +assembly: fd, fs1, fs2 +encoding: + match: 0010100----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_or_X_S(rs1); + let rs2_val_S = F_or_X_S(rs2); + + let (fflags, rd_val) : (bits_fflags, bool) = + riscv_f32Le (rs1_val_S, rs2_val_S); + + accrue_fflags(fflags); + X(rd) = zero_extend(bool_to_bits(rd_val)); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fmsub.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fmsub.s.yaml new file mode 100644 index 000000000000..1eb72b3433ea --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fmsub.s.yaml @@ -0,0 +1,63 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmsub.s +long_name: Floating-Point Multiply-Subtract Single-Precision +description: | + The `fmsub.s` multiplies the values in `fs1` and `fs2`, subtracts the value in `fs3`, and writes the final result to `fd`. +definedBy: + extension: + name: F +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----00------------------1000111" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_32b = F_or_X_S(rs1); + let rs2_val_32b = F_or_X_S(rs2); + let rs3_val_32b = F_or_X_S(rs3); + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_32b) : (bits(5), bits(32)) = + match op { + FMADD_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b), + FMSUB_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, negate_S (rs3_val_32b)), + FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b), + FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b)) + }; + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_32b; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fmul.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fmul.s.yaml new file mode 100644 index 000000000000..4360f1f95390 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fmul.s.yaml @@ -0,0 +1,60 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmul.s +long_name: Floating-Point Multiply Single-Precision +description: | + The `fmul.s` instruction performs the single-precision floating-point multiplication between `fs1` and `fs2`, and + writes the result in `fd`. +definedBy: + extension: + name: F +assembly: fd, fs1, fs2, rm +encoding: + match: 0001000------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_32b = F_or_X_S(rs1); + let rs2_val_32b = F_or_X_S(rs2); + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op { + FADD_S => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b), + FSUB_S => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b), + FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b), + FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b) + }; + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_32b; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fmv.w.x.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fmv.w.x.yaml new file mode 100644 index 000000000000..8bc10adb7f05 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fmv.w.x.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmv.w.x +long_name: Floating-Point Move Single-Precision Word from Integer Register +description: | + The `fmv.w.x` instruction moves the single-precision value encoded in `IEEE 754-2008` standard encoding + from the lower 32 bits of integer register `xs1` to the floating-point register `fd`. The bits are not + modified in the transfer, and in particular, the payloads of non-canonical NaNs are preserved. +definedBy: + extension: + name: F +assembly: fd, xs1 +encoding: + match: 111100000000-----000-----1010011 + variables: + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + + Bits<32> sp_value = X[xs1][31:0]; + + if (implemented?(ExtensionName::D)) { + f[fd] = nan_box<32, 64>(sp_value); + } else { + f[fd] = sp_value; + } + + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_X = X(rs1); + let rd_val_S = rs1_val_X [31..0]; + F(rd) = nan_box (rd_val_S); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fmv.x.w.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fmv.x.w.yaml new file mode 100644 index 000000000000..40ba95a78bce --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fmv.x.w.yaml @@ -0,0 +1,48 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmv.x.w +long_name: Floating-Point Move Single-Precision Word to Integer Register +description: | + The `fmv.x.w` instruction moves the single-precision value in floating-point register `fs1`` represented in `IEEE 754-2008` + encoding to the lower 32 bits of integer register `xd`. The bits are not modified in the transfer, and in particular, the + payloads of non-canonical NaNs are preserved. For RV64, the higher 32 bits of the destination register are filled with copies + of the floating-point number's sign bit. +definedBy: + extension: + name: F +assembly: xd, fs1 +encoding: + match: 111000000000-----000-----1010011 + variables: + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + + X[xd] = sext(f[fs1][31:0], 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_X = X(rs1); + let rd_val_S = rs1_val_X [31..0]; + F(rd) = nan_box (rd_val_S); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fnmadd.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fnmadd.s.yaml new file mode 100644 index 000000000000..b31ac89133d6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fnmadd.s.yaml @@ -0,0 +1,64 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fnmadd.s +long_name: Floating-Point Negate-Multiply-Add Single-Precision +description: | + The `fnmadd.s` multiplies the values in `fs1` and `fs2`, negates the product, subtracts the value in `fs3`, and + writes the final result to `fd`. +definedBy: + extension: + name: F +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----00------------------1001111" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_32b = F_or_X_S(rs1); + let rs2_val_32b = F_or_X_S(rs2); + let rs3_val_32b = F_or_X_S(rs3); + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_32b) : (bits(5), bits(32)) = + match op { + FMADD_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b), + FMSUB_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, negate_S (rs3_val_32b)), + FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b), + FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b)) + }; + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_32b; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fnmsub.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fnmsub.s.yaml new file mode 100644 index 000000000000..ae5e25a2a8a3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fnmsub.s.yaml @@ -0,0 +1,64 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fnmsub.s +long_name: Floating-Point Negate-Multiply-Subtract Single-Precision +description: | + The `fnmsub.s` instruction multiplies the values in `fs1` and `fs2`, negates the product, adds the value in `fs3`, and + writes the final result to `fd`. +definedBy: + extension: + name: F +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----00------------------1001011" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_32b = F_or_X_S(rs1); + let rs2_val_32b = F_or_X_S(rs2); + let rs3_val_32b = F_or_X_S(rs3); + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_32b) : (bits(5), bits(32)) = + match op { + FMADD_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, rs3_val_32b), + FMSUB_S => riscv_f32MulAdd (rm_3b, rs1_val_32b, rs2_val_32b, negate_S (rs3_val_32b)), + FNMSUB_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, rs3_val_32b), + FNMADD_S => riscv_f32MulAdd (rm_3b, negate_S (rs1_val_32b), rs2_val_32b, negate_S (rs3_val_32b)) + }; + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_32b; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fsgnj.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fsgnj.s.yaml new file mode 100644 index 000000000000..a887542d8b1f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fsgnj.s.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsgnj.s +long_name: Floating-Point Sign-Inject Single-Precision +description: | + The `fsgnj.s` instruction produces a result that takes all bits except the sign bit from `fs1`. + The result's sign bit is taken from `fs2`'s sign bit, and the result is written to the destination + register `fd`. Sign-injection instructions do not set floating-point exception flags, nor do they + canonicalize NaNs. + +definedBy: + extension: + name: F +assembly: fd, fs1, fs2 +encoding: + match: 0010000----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: (rs2 == rs1) + to: fmv.s + +operation(): | + check_f_ok($encoding); + + Bits<32> sp_value = {f[fs2][31], f[fs1][30:0]}; + + if (implemented?(ExtensionName::D)) { + f[fd] = nan_box<32, 64>(sp_value); + } else { + f[fd] = sp_value; + } + + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_or_X_S(rs1); + let rs2_val_S = F_or_X_S(rs2); + + let (fflags, rd_val) : (bits_fflags, bool) = + riscv_f32Le (rs1_val_S, rs2_val_S); + + accrue_fflags(fflags); + X(rd) = zero_extend(bool_to_bits(rd_val)); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fsgnjn.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fsgnjn.s.yaml new file mode 100644 index 000000000000..c6c89d2cb58c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fsgnjn.s.yaml @@ -0,0 +1,67 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsgnjn.s +long_name: Floating-Point Sign-Inject Negate Single-Precision +description: | + The `fsgnjn.s` instruction produces a result that takes all bits except the sign bit from `fs1`. + The result's sign bit is opposite of `fs2`'s sign bit, and the result is written to the destination + register `fd`. Sign-injection instructions do not set floating-point exception flags, nor do they + canonicalize NaNs. +definedBy: + extension: + name: F +assembly: fd, fs1, fs2 +encoding: + match: 0010000----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: (fs2 == fs1) + to: fneg.s fd, fs1 + +operation(): | + check_f_ok($encoding); + + Bits<32> sp_value = {~f[fs2][31], f[fs1][30:0]}; + + if (implemented?(ExtensionName::D)) { + f[fd] = nan_box<32, 64>(sp_value); + } else { + f[fd] = sp_value; + } + + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_or_X_S(rs1); + let rs2_val_S = F_or_X_S(rs2); + + let (fflags, rd_val) : (bits_fflags, bool) = + riscv_f32Le (rs1_val_S, rs2_val_S); + + accrue_fflags(fflags); + X(rd) = zero_extend(bool_to_bits(rd_val)); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fsgnjx.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fsgnjx.s.yaml new file mode 100644 index 000000000000..3843eb260489 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fsgnjx.s.yaml @@ -0,0 +1,66 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsgnjx.s +long_name: Floating-Point Sign-Inject XOR Single-Precision +description: | + The `fsgnjx.s` instruction produces a result that takes all bits except the sign bit from `fs1`. + The result's sign bit is the XOR of sign bits of `fs1` and `fs2`, and the result is written to + the destination register `fd`. Sign-injection instructions do not set floating-point exception + flags, nor do they canonicalize NaNs. +definedBy: + extension: + name: F +assembly: fd, fs1, fs2 +encoding: + match: 0010000----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: (xs2 == xs1) + to: fabs.s +operation(): | + check_f_ok($encoding); + + Bits<32> sp_value = {f[fs1][31] ^ f[fs2][31], f[fs1][30:0]}; + + if (implemented?(ExtensionName::D)) { + f[fd] = nan_box<32, 64>(sp_value); + } else { + f[fd] = sp_value; + } + + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_or_X_S(rs1); + let rs2_val_S = F_or_X_S(rs2); + + let (fflags, rd_val) : (bits_fflags, bool) = + riscv_f32Le (rs1_val_S, rs2_val_S); + + accrue_fflags(fflags); + X(rd) = zero_extend(bool_to_bits(rd_val)); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fsqrt.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fsqrt.s.yaml new file mode 100644 index 000000000000..6a21fbf5f598 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fsqrt.s.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsqrt.s +long_name: Floating-Point Square Root Single-Precision +description: | + The `fsqrt.s` instruction computes the square root of `fs1` and writes the result is written to `fd`. +definedBy: + extension: + name: F +assembly: fd, fs1, rm +encoding: + match: 010110000000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fsub.s.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fsub.s.yaml new file mode 100644 index 000000000000..3e05c2513309 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fsub.s.yaml @@ -0,0 +1,61 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsub.s +long_name: Floating-Point Subtract Single-Precision +description: | + The `fsub.s` instruction performs the single-precision floating-point subtraction of `fs2` from `fs1` and writes the result in `fd`. +definedBy: + extension: + name: F +assembly: fd, fs1, fs2, rm +encoding: + match: 0000100------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + RoundingMode mode = rm_to_mode(rm, $encoding); + f[fd] = f32_sub(f[fs1], f[fs2], mode); +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_32b = F_or_X_S(rs1); + let rs2_val_32b = F_or_X_S(rs2); + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_32b) : (bits(5), bits(32)) = match op { + FADD_S => riscv_f32Add (rm_3b, rs1_val_32b, rs2_val_32b), + FSUB_S => riscv_f32Sub (rm_3b, rs1_val_32b, rs2_val_32b), + FMUL_S => riscv_f32Mul (rm_3b, rs1_val_32b, rs2_val_32b), + FDIV_S => riscv_f32Div (rm_3b, rs1_val_32b, rs2_val_32b) + }; + accrue_fflags(fflags); + F_or_X_S(rd) = rd_val_32b; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/F/fsw.yaml b/pkg/ifuzz/riscv64/gen/inst/F/fsw.yaml new file mode 100644 index 000000000000..d4510ff52f11 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/F/fsw.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsw +long_name: Floating-Point Store Single-Precision +description: | + The `fsw` instruction stores a single-precision floating-point value in `fs2` to memory at address `xs1` + `imm`. + It does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. + +definedBy: + extension: + name: F +assembly: fs2, imm(xs1) +encoding: + match: "-----------------010-----0100111" + variables: + - name: imm + location: 31-25|11-7 + - name: fs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + + XReg virtual_address = X[xs1] + $signed(imm); + + write_memory<32>(virtual_address, f[fs2][31:0], $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + let (aq, rl, con) = (false, false, false); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Write(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match width { + BYTE => MemValue () /* bogus placeholder for illegal size */, + HALF => mem_write_ea(addr, 2, aq, rl, false), + WORD => mem_write_ea(addr, 4, aq, rl, false), + DOUBLE => mem_write_ea(addr, 8, aq, rl, false) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let rs2_val = F(rs2); + match (width) { + BYTE => { handle_illegal(); RETIRE_FAIL }, + HALF => process_fstore (vaddr, mem_write_value(addr, 2, rs2_val[15..0], aq, rl, con)), + WORD => process_fstore (vaddr, mem_write_value(addr, 4, rs2_val[31..0], aq, rl, con)), + DOUBLE if sizeof(flen) >= 64 => + process_fstore (vaddr, mem_write_value(addr, 8, rs2_val, aq, rl, con)), + _ => report_invalid_width(__FILE__, __LINE__, width, "floating point store"), + }; + } + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hfence.gvma.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hfence.gvma.yaml new file mode 100644 index 000000000000..2d2d9191c651 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hfence.gvma.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hfence.gvma +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xs1, xs2 +encoding: + match: 0110001----------000000001110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hfence.vvma.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hfence.vvma.yaml new file mode 100644 index 000000000000..3c68d5b598e9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hfence.vvma.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hfence.vvma +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xs1, xs2 +encoding: + match: 0010001----------000000001110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hlv.b.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hlv.b.yaml new file mode 100644 index 000000000000..1779f9dc521f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hlv.b.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hlv.b +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xd, xs1 +encoding: + match: 011000000000-----100-----1110011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hlv.bu.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hlv.bu.yaml new file mode 100644 index 000000000000..1aa288340ef8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hlv.bu.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hlv.bu +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xd, xs1 +encoding: + match: 011000000001-----100-----1110011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hlv.d.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hlv.d.yaml new file mode 100644 index 000000000000..9d57ae60b7a8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hlv.d.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hlv.d +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 64 + - extension: + name: H +assembly: xd, xs1 +encoding: + match: 011011000000-----100-----1110011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hlv.h.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hlv.h.yaml new file mode 100644 index 000000000000..9f5cb9d2b9fd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hlv.h.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hlv.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xd, xs1 +encoding: + match: 011001000000-----100-----1110011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hlv.hu.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hlv.hu.yaml new file mode 100644 index 000000000000..f031554921c1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hlv.hu.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hlv.hu +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xd, xs1 +encoding: + match: 011001000001-----100-----1110011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hlv.w.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hlv.w.yaml new file mode 100644 index 000000000000..aa5f33aa9c9d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hlv.w.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hlv.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xd, xs1 +encoding: + match: 011010000000-----100-----1110011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hlv.wu.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hlv.wu.yaml new file mode 100644 index 000000000000..d7ee96f1fdd0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hlv.wu.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hlv.wu +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 64 + - extension: + name: H +assembly: xd, xs1 +encoding: + match: 011010000001-----100-----1110011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hlvx.hu.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hlvx.hu.yaml new file mode 100644 index 000000000000..108a8f4207ac --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hlvx.hu.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hlvx.hu +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xd, xs1 +encoding: + match: 011001000011-----100-----1110011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hlvx.wu.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hlvx.wu.yaml new file mode 100644 index 000000000000..a5877fd779ef --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hlvx.wu.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hlvx.wu +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xd, xs1 +encoding: + match: 011010000011-----100-----1110011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hsv.b.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hsv.b.yaml new file mode 100644 index 000000000000..91cefd4d1e19 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hsv.b.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hsv.b +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xs1, xs2 +encoding: + match: 0110001----------100000001110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hsv.d.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hsv.d.yaml new file mode 100644 index 000000000000..f58bdd0fa9f4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hsv.d.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hsv.d +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 64 + - extension: + name: H +assembly: xs1, xs2 +encoding: + match: 0110111----------100000001110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hsv.h.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hsv.h.yaml new file mode 100644 index 000000000000..f80aff457521 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hsv.h.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hsv.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xs1, xs2 +encoding: + match: 0110011----------100000001110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/H/hsv.w.yaml b/pkg/ifuzz/riscv64/gen/inst/H/hsv.w.yaml new file mode 100644 index 000000000000..31fba27e1eb7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/H/hsv.w.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: hsv.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: H +assembly: xs1, xs2 +encoding: + match: 0110101----------100000001110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/I/add.yaml b/pkg/ifuzz/riscv64/gen/inst/I/add.yaml new file mode 100644 index 000000000000..3c4fd9abe78f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/add.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: add +long_name: Integer add +description: | + Add the value in xs1 to xs2, and store the result in xd. + Any overflow is thrown away. +definedBy: + extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +hints: + - { $ref: inst/Zihintntl/ntl.p1.yaml# } + - { $ref: inst/Zihintntl/ntl.pall.yaml# } + - { $ref: inst/Zihintntl/ntl.s1.yaml# } + - { $ref: inst/Zihintntl/ntl.all.yaml# } +operation(): X[xd] = X[xs1] + X[xs2]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let result : xlenbits = match op { + RISCV_ADD => xs1_val + xs2_val, + RISCV_SLT => zero_extend(bool_to_bits(xs1_val <_s xs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(xs1_val <_u xs2_val)), + RISCV_AND => xs1_val & xs2_val, + RISCV_OR => xs1_val | xs2_val, + RISCV_XOR => xs1_val ^ xs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then xs1_val << (xs2_val[4..0]) + else xs1_val << (xs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then xs1_val >> (xs2_val[4..0]) + else xs1_val >> (xs2_val[5..0]), + RISCV_SUB => xs1_val - xs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, xs2_val[4..0]) + else shift_right_arith64(xs1_val, xs2_val[5..0]) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/addi.yaml b/pkg/ifuzz/riscv64/gen/inst/I/addi.yaml new file mode 100644 index 000000000000..b584fb201cfc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/addi.yaml @@ -0,0 +1,58 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: addi +long_name: Add immediate +description: + Adds an immediate value to the value in xs1, and store the result in + xd +definedBy: + extension: + name: I +assembly: xd, xs1, imm +encoding: + match: "-----------------000-----0010011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: (xd == 0 && xs1 == 0 && imm == 0) + to: nop + - when: imm == 0 + to: mv xd,xs1 +operation(): X[xd] = X[xs1] + $signed(imm); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let immext : xlenbits = sign_extend(imm); + let result : xlenbits = match op { + RISCV_ADDI => xs1_val + immext, + RISCV_SLTI => zero_extend(bool_to_bits(xs1_val <_s immext)), + RISCV_SLTIU => zero_extend(bool_to_bits(xs1_val <_u immext)), + RISCV_ANDI => xs1_val & immext, + RISCV_ORI => xs1_val | immext, + RISCV_XORI => xs1_val ^ immext + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/addiw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/addiw.yaml new file mode 100644 index 000000000000..2b3596f5656b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/addiw.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: addiw +long_name: Add immediate word +description: + Add an immediate to the 32-bit value in xs1, and store the sign extended + result in xd +definedBy: + allOf: + - xlen: 64 + - extension: + name: I +assembly: xd, xs1, imm +encoding: + match: "-----------------000-----0011011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: imm == 0 + to: sext.w xd,xs1 +operation(): | + X[xd] = $signed((X[xs1] + $signed(imm))[31:0]); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let result : xlenbits = sign_extend(imm) + X(xs1); + X(xd) = sign_extend(result[31..0]); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/addw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/addw.yaml new file mode 100644 index 000000000000..1dfc75ecd968 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/addw.yaml @@ -0,0 +1,57 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: addw +long_name: Add word +description: | + Add the 32-bit values in xs1 to xs2, and store the sign-extended result in xd. + Any overflow is thrown away. +definedBy: + allOf: + - xlen: 64 + - extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------000-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + XReg operand1 = sext(X[xs1], 32); + XReg operand2 = sext(X[xs2], 32); + X[xd] = sext(operand1 + operand2, 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = (X(xs1))[31..0]; + let xs2_val = (X(xs2))[31..0]; + let result : bits(32) = match op { + RISCV_ADDW => xs1_val + xs2_val, + RISCV_SUBW => xs1_val - xs2_val, + RISCV_SLLW => xs1_val << (xs2_val[4..0]), + RISCV_SRLW => xs1_val >> (xs2_val[4..0]), + RISCV_SRAW => shift_right_arith32(xs1_val, xs2_val[4..0]) + }; + X(xd) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/and.yaml b/pkg/ifuzz/riscv64/gen/inst/I/and.yaml new file mode 100644 index 000000000000..f4e39f127ac1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/and.yaml @@ -0,0 +1,61 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: and +long_name: And +description: And xs1 with xs2, and store the result in xd +definedBy: + extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------111-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): X[xd] = X[xs1] & X[xs2]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let result : xlenbits = match op { + RISCV_ADD => xs1_val + xs2_val, + RISCV_SLT => zero_extend(bool_to_bits(xs1_val <_s xs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(xs1_val <_u xs2_val)), + RISCV_AND => xs1_val & xs2_val, + RISCV_OR => xs1_val | xs2_val, + RISCV_XOR => xs1_val ^ xs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then xs1_val << (xs2_val[4..0]) + else xs1_val << (xs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then xs1_val >> (xs2_val[4..0]) + else xs1_val >> (xs2_val[5..0]), + RISCV_SUB => xs1_val - xs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, xs2_val[4..0]) + else shift_right_arith64(xs1_val, xs2_val[5..0]) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/andi.yaml b/pkg/ifuzz/riscv64/gen/inst/I/andi.yaml new file mode 100644 index 000000000000..d9a342ec4d4a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/andi.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: andi +long_name: And immediate +description: And an immediate to the value in xs1, and store the result in xd +definedBy: + extension: + name: I +assembly: xd, xs1, imm +encoding: + match: "-----------------111-----0010011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: imm == 255 + to: zext.b +operation(): X[xd] = X[xs1] & $signed(imm); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let immext : xlenbits = sign_extend(imm); + let result : xlenbits = match op { + RISCV_ADDI => xs1_val + immext, + RISCV_SLTI => zero_extend(bool_to_bits(xs1_val <_s immext)), + RISCV_SLTIU => zero_extend(bool_to_bits(xs1_val <_u immext)), + RISCV_ANDI => xs1_val & immext, + RISCV_ORI => xs1_val | immext, + RISCV_XORI => xs1_val ^ immext + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/auipc.yaml b/pkg/ifuzz/riscv64/gen/inst/I/auipc.yaml new file mode 100644 index 000000000000..ca167678e6c8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/auipc.yaml @@ -0,0 +1,47 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: auipc +long_name: Add upper immediate to pc +description: Add an immediate to the current PC. +definedBy: + extension: + name: I +assembly: xd, imm +encoding: + match: "-------------------------0010111" + variables: + - name: imm + location: 31-12 + left_shift: 12 + - name: xd + location: 11-7 +hints: + - { $ref: inst/Zicfilp/lpad.yaml# } +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): X[xd] = $pc + $signed(imm); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let off : xlenbits = sign_extend(imm @ 0x000); + let ret : xlenbits = match op { + RISCV_LUI => off, + RISCV_AUIPC => get_arch_pc() + off + }; + X(xd) = ret; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/beq.yaml b/pkg/ifuzz/riscv64/gen/inst/I/beq.yaml new file mode 100644 index 000000000000..71cfc926744f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/beq.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: beq +long_name: Branch if equal +description: | + Branch to PC + imm if + the value in register xs1 is equal to the value in register xs2. + + Raise a `MisalignedAddress` exception if PC + imm is misaligned. +definedBy: + extension: + name: I +assembly: xs1, xs2, imm +encoding: + match: "-----------------000-----1100011" + variables: + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +pseudoinstructions: + - when: xs2 == 0 + to: beqz xs1,imm +operation(): | + XReg lhs = X[xs1]; + XReg rhs = X[xs2]; + + if (lhs == rhs) { + jump_halfword($pc + $signed(imm)); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let taken : bool = match op { + RISCV_BEQ => xs1_val == xs2_val, + RISCV_BNE => xs1_val != xs2_val, + RISCV_BLT => xs1_val <_s xs2_val, + RISCV_BGE => xs1_val >=_s xs2_val, + RISCV_BLTU => xs1_val <_u xs2_val, + RISCV_BGEU => xs1_val >=_u xs2_val + }; + let t : xlenbits = PC + sign_extend(imm); + if taken then { + /* Extensions get the first checks on the prospective target address. */ + match ext_control_check_pc(t) { + Ext_ControlAddr_Error(e) => { + ext_handle_control_check_error(e); + RETIRE_FAIL + }, + Ext_ControlAddr_OK(target) => { + if bit_to_bool(target[1]) & not(extension("C")) then { + handle_mem_exception(target, E_Fetch_Addr_Align()); + RETIRE_FAIL; + } else { + set_next_pc(target); + RETIRE_SUCCESS + } + } + } + } else RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/bge.yaml b/pkg/ifuzz/riscv64/gen/inst/I/bge.yaml new file mode 100644 index 000000000000..395d83fe05d5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/bge.yaml @@ -0,0 +1,84 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: bge +long_name: Branch if greater than or equal +description: | + Branch to PC + imm if + the signed value in register xs1 is greater than or equal to the signed value in register xs2. + + Raise a `MisalignedAddress` exception if PC + imm is misaligned. +definedBy: + extension: + name: I +assembly: xs1, xs2, imm +encoding: + match: "-----------------101-----1100011" + variables: + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +pseudoinstructions: + - when: xs1 == 0 + to: blez xs2,imm + - when: xs2 == 0 + to: bgez xs1,imm +operation(): | + XReg lhs = X[xs1]; + XReg rhs = X[xs2]; + + if ($signed(lhs) >= $signed(rhs)) { + jump_halfword($pc + $signed(imm)); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let taken : bool = match op { + RISCV_BEQ => xs1_val == xs2_val, + RISCV_BNE => xs1_val != xs2_val, + RISCV_BLT => xs1_val <_s xs2_val, + RISCV_BGE => xs1_val >=_s xs2_val, + RISCV_BLTU => xs1_val <_u xs2_val, + RISCV_BGEU => xs1_val >=_u xs2_val + }; + let t : xlenbits = PC + sign_extend(imm); + if taken then { + /* Extensions get the first checks on the prospective target address. */ + match ext_control_check_pc(t) { + Ext_ControlAddr_Error(e) => { + ext_handle_control_check_error(e); + RETIRE_FAIL + }, + Ext_ControlAddr_OK(target) => { + if bit_to_bool(target[1]) & not(extension("C")) then { + handle_mem_exception(target, E_Fetch_Addr_Align()); + RETIRE_FAIL; + } else { + set_next_pc(target); + RETIRE_SUCCESS + } + } + } + } else RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/bgeu.yaml b/pkg/ifuzz/riscv64/gen/inst/I/bgeu.yaml new file mode 100644 index 000000000000..0e7a1d7a7c32 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/bgeu.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: bgeu +long_name: Branch if greater than or equal unsigned +description: | + Branch to PC + imm if + the unsigned value in register xs1 is greater than or equal to the unsigned value in register xs2. + + Raise a `MisalignedAddress` exception if PC + imm is misaligned. +definedBy: + extension: + name: I +assembly: xs1, xs2, imm +encoding: + match: "-----------------111-----1100011" + variables: + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg lhs = X[xs1]; + XReg rhs = X[xs2]; + + if (lhs >= rhs) { + jump_halfword($pc + $signed(imm)); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let taken : bool = match op { + RISCV_BEQ => xs1_val == xs2_val, + RISCV_BNE => xs1_val != xs2_val, + RISCV_BLT => xs1_val <_s xs2_val, + RISCV_BGE => xs1_val >=_s xs2_val, + RISCV_BLTU => xs1_val <_u xs2_val, + RISCV_BGEU => xs1_val >=_u xs2_val + }; + let t : xlenbits = PC + sign_extend(imm); + if taken then { + /* Extensions get the first checks on the prospective target address. */ + match ext_control_check_pc(t) { + Ext_ControlAddr_Error(e) => { + ext_handle_control_check_error(e); + RETIRE_FAIL + }, + Ext_ControlAddr_OK(target) => { + if bit_to_bool(target[1]) & not(extension("C")) then { + handle_mem_exception(target, E_Fetch_Addr_Align()); + RETIRE_FAIL; + } else { + set_next_pc(target); + RETIRE_SUCCESS + } + } + } + } else RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/blt.yaml b/pkg/ifuzz/riscv64/gen/inst/I/blt.yaml new file mode 100644 index 000000000000..a587044dd742 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/blt.yaml @@ -0,0 +1,84 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: blt +long_name: Branch if less than +description: | + Branch to PC + imm if + the signed value in register xs1 is less than the signed value in register xs2. + + Raise a `MisalignedAddress` exception if PC + imm is misaligned. +definedBy: + extension: + name: I +assembly: xs1, xs2, imm +encoding: + match: "-----------------100-----1100011" + variables: + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +pseudoinstructions: + - when: xs2 == 0 + to: bltz xs1,imm + - when: xs1 == 0 + to: bgtz xs2,imm +operation(): | + XReg lhs = X[xs1]; + XReg rhs = X[xs2]; + + if ($signed(lhs) < $signed(rhs)) { + jump_halfword($pc + $signed(imm)); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let taken : bool = match op { + RISCV_BEQ => xs1_val == xs2_val, + RISCV_BNE => xs1_val != xs2_val, + RISCV_BLT => xs1_val <_s xs2_val, + RISCV_BGE => xs1_val >=_s xs2_val, + RISCV_BLTU => xs1_val <_u xs2_val, + RISCV_BGEU => xs1_val >=_u xs2_val + }; + let t : xlenbits = PC + sign_extend(imm); + if taken then { + /* Extensions get the first checks on the prospective target address. */ + match ext_control_check_pc(t) { + Ext_ControlAddr_Error(e) => { + ext_handle_control_check_error(e); + RETIRE_FAIL + }, + Ext_ControlAddr_OK(target) => { + if bit_to_bool(target[1]) & not(extension("C")) then { + handle_mem_exception(target, E_Fetch_Addr_Align()); + RETIRE_FAIL; + } else { + set_next_pc(target); + RETIRE_SUCCESS + } + } + } + } else RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/bltu.yaml b/pkg/ifuzz/riscv64/gen/inst/I/bltu.yaml new file mode 100644 index 000000000000..b3300bc6007a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/bltu.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: bltu +long_name: Branch if less than unsigned +description: | + Branch to PC + imm if + the unsigned value in register xs1 is less than the unsigned value in register xs2. + + Raise a `MisalignedAddress` exception if PC + imm is misaligned. +definedBy: + extension: + name: I +assembly: xs1, xs2, imm +encoding: + match: "-----------------110-----1100011" + variables: + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg lhs = X[xs1]; + XReg rhs = X[xs2]; + + if (lhs < rhs) { + jump_halfword($pc + $signed(imm)); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let taken : bool = match op { + RISCV_BEQ => xs1_val == xs2_val, + RISCV_BNE => xs1_val != xs2_val, + RISCV_BLT => xs1_val <_s xs2_val, + RISCV_BGE => xs1_val >=_s xs2_val, + RISCV_BLTU => xs1_val <_u xs2_val, + RISCV_BGEU => xs1_val >=_u xs2_val + }; + let t : xlenbits = PC + sign_extend(imm); + if taken then { + /* Extensions get the first checks on the prospective target address. */ + match ext_control_check_pc(t) { + Ext_ControlAddr_Error(e) => { + ext_handle_control_check_error(e); + RETIRE_FAIL + }, + Ext_ControlAddr_OK(target) => { + if bit_to_bool(target[1]) & not(extension("C")) then { + handle_mem_exception(target, E_Fetch_Addr_Align()); + RETIRE_FAIL; + } else { + set_next_pc(target); + RETIRE_SUCCESS + } + } + } + } else RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/bne.yaml b/pkg/ifuzz/riscv64/gen/inst/I/bne.yaml new file mode 100644 index 000000000000..cfd651b4500b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/bne.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: bne +long_name: Branch if not equal +description: | + Branch to PC + imm if + the value in register xs1 is not equal to the value in register xs2. + + Raise a `MisalignedAddress` exception if PC + imm is misaligned. +definedBy: + extension: + name: I +assembly: xs1, xs2, imm +encoding: + match: "-----------------001-----1100011" + variables: + - name: imm + location: 31|7|30-25|11-8 + left_shift: 1 + sign_extend: true + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +pseudoinstructions: + - when: xs2 == 0 + to: bnez xs1,imm +operation(): | + XReg lhs = X[xs1]; + XReg rhs = X[xs2]; + + if (lhs != rhs) { + jump_halfword($pc + $signed(imm)); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let taken : bool = match op { + RISCV_BEQ => xs1_val == xs2_val, + RISCV_BNE => xs1_val != xs2_val, + RISCV_BLT => xs1_val <_s xs2_val, + RISCV_BGE => xs1_val >=_s xs2_val, + RISCV_BLTU => xs1_val <_u xs2_val, + RISCV_BGEU => xs1_val >=_u xs2_val + }; + let t : xlenbits = PC + sign_extend(imm); + if taken then { + /* Extensions get the first checks on the prospective target address. */ + match ext_control_check_pc(t) { + Ext_ControlAddr_Error(e) => { + ext_handle_control_check_error(e); + RETIRE_FAIL + }, + Ext_ControlAddr_OK(target) => { + if bit_to_bool(target[1]) & not(extension("C")) then { + handle_mem_exception(target, E_Fetch_Addr_Align()); + RETIRE_FAIL; + } else { + set_next_pc(target); + RETIRE_SUCCESS + } + } + } + } else RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/ebreak.yaml b/pkg/ifuzz/riscv64/gen/inst/I/ebreak.yaml new file mode 100644 index 000000000000..327bc3c93855 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/ebreak.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: ebreak +long_name: Breakpoint exception +description: | + The EBREAK instruction is used by debuggers to cause control to be transferred back to + a debugging environment. Unless overridden by an external debug environment, + EBREAK raises a breakpoint exception and performs no other operation. + + [NOTE] + As described in the `C` Standaxd Extension for Compressed Instructions, the `c.ebreak` + instruction performs the same operation as the EBREAK instruction. + + EBREAK causes the receiving privilege mode's epc register to be set to the address of + the EBREAK instruction itself, not the address of the following instruction. + As EBREAK causes a synchronous exception, it is not considered to retire, + and should not increment the `minstret` CSR. +definedBy: + extension: + name: I +assembly: "" +encoding: + match: "00000000000100000000000001110011" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (TRAP_ON_EBREAK) { + raise_precise(ExceptionCode::Breakpoint, mode(), $pc); + } else { + eei_ebreak(); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + handle_mem_exception(PC, E_Breakpoint()); + RETIRE_FAIL + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/ecall.yaml b/pkg/ifuzz/riscv64/gen/inst/I/ecall.yaml new file mode 100644 index 000000000000..be5e78689317 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/ecall.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: ecall +long_name: Environment call +description: | + Makes a request to the supporting execution environment. + When executed in U-mode, S-mode, or M-mode, it generates an environment-call-from-U-mode + exception, environment-call-from-S-mode exception, or environment-call-from-M-mode + exception, respectively, and performs no other operation. + + [NOTE] + ECALL generates a different exception for each originating privilege mode so that + environment call exceptions can be selectively delegated. + A typical use case for Unix-like operating systems is to delegate to S-mode + the environment-call-from-U-mode exception but not the others. + + ECALL causes the receiving privilege mode's epc register to be set to the address of + the ECALL instruction itself, not the address of the following instruction. + As ECALL causes a synchronous exception, it is not considered to retire, + and should not increment the `minstret` CSR. +definedBy: + extension: + name: I +assembly: "" +encoding: + match: "00000000000000000000000001110011" +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (mode() == PrivilegeMode::M) { + if (TRAP_ON_ECALL_FROM_M) { + raise_precise(ExceptionCode::Mcall, PrivilegeMode::M, 0); + } else { + eei_ecall_from_m(); + } + } else if (mode() == PrivilegeMode::S) { + if (TRAP_ON_ECALL_FROM_S) { + raise_precise(ExceptionCode::Scall, PrivilegeMode::S, 0); + } else { + eei_ecall_from_s(); + } + } else if (mode() == PrivilegeMode::U || mode() == PrivilegeMode::VU) { + if (TRAP_ON_ECALL_FROM_U) { + raise_precise(ExceptionCode::Ucall, mode(), 0); + } else { + eei_ecall_from_u(); + } + } else if (mode() == PrivilegeMode::VS) { + if (TRAP_ON_ECALL_FROM_VS) { + raise_precise(ExceptionCode::VScall, PrivilegeMode::VS, 0); + } else { + eei_ecall_from_vs(); + } + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let t : sync_exception = + struct { trap = match (cur_privilege) { + User => E_U_EnvCall(), + Supervisor => E_S_EnvCall(), + Machine => E_M_EnvCall() + }, + excinfo = (None() : option(xlenbits)), + ext = None() }; + set_next_pc(exception_handler(cur_privilege, CTL_TRAP(t), PC)); + RETIRE_FAIL + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/fence.tso.yaml b/pkg/ifuzz/riscv64/gen/inst/I/fence.tso.yaml new file mode 100644 index 000000000000..400e98debb66 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/fence.tso.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fence.tso +long_name: Memory ordering fence, total store ordering +description: | + Orders memory operations. + + `fence.tso` orders all load operations + in its predecessor set before all memory operations in its successor set, and all store operations + in its predecessor set before all store operations in its successor set. This leaves non-AMO store + operations in the 'fence.tso's predecessor set unordered with non-AMO loads in its successor set. + + The `xs1` and `xd` fields are unused and ignored. + + In modes other than M-mode, `fence.tso` is further affected by `menvcfg.FIOM`, + `senvcfg.FIOM`<% if ext?(:H) %>, and/or `henvcfg.FIOM`<% end %>. + +definedBy: + extension: + name: I +assembly: "" +encoding: + match: 100000110011-----000-----0001111 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + fence_tso(); + +sail(): | + { + match (pred, succ) { + (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => sail_barrier(Barrier_RISCV_tso), + (_ : bits(2) @ 0b00, _ : bits(2) @ 0b00) => (), + + _ => { print("FIXME: unsupported fence"); + () } + }; + RETIRE_SUCCESS + } diff --git a/pkg/ifuzz/riscv64/gen/inst/I/fence.yaml b/pkg/ifuzz/riscv64/gen/inst/I/fence.yaml new file mode 100644 index 000000000000..82caf7a7d372 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/fence.yaml @@ -0,0 +1,239 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fence +long_name: Memory ordering fence +description: | + Orders memory operations. + + The `fence` instruction is used to order device I/O and memory accesses as + viewed by other RISC-V harts and external devices or coprocessors. Any + combination of device input (I), device output (O), memory reads \(R), + and memory writes (W) may be ordered with respect to any combination of + the same. Informally, no other RISC-V hart or external device can + observe any operation in the _successor_ set following a `fence` before + any operation in the _predecessor_ set preceding the `fence`. + + The predecessor and successor fields have the same format to specify operation types: + + [%autowidth] + |=== + 4+| `pred` 4+| `succ` + + | 27 | 26 |25 | 24 | 23 | 22 | 21| 20 + | PI | PO |PR | PW | SI | SO |SR | SW + |=== + + [%autowidth,align="center",cols="^1,^1,<3",options="header"] + .Fence mode encoding + |=== + |_fm_ field |Mnemonic |Meaning + |0000 |_none_ |Normal Fence + |1000 |TSO |With `FENCE RW,RW`: exclude write-to-read ordering; otherwise: _Reserved for future use._ + 2+|_other_ |_Reserved for future use._ + |=== + + When the mode field _fm_ is `0001` and both the predecessor and successor sets are 'RW', + then the instruction acts as a special-case `fence.tso`. `fence.tso` orders all load operations + in its predecessor set before all memory operations in its successor set, and all store operations + in its predecessor set before all store operations in its successor set. This leaves non-AMO store + operations in the 'fence.tso's predecessor set unordered with non-AMO loads in its successor set. + + When mode field _fm_ is not `0001`, or when mode field _fm_ is `0001` but the _pred_ and + _succ_ fields are not both 'RW' (0x3), then the fence acts as a baseline fence (_e.g._, _fm_ is + effectively `0000`). This is unaffected by the FIOM bits, described below (implicit promotion does + not change how `fence.tso` is decoded). + + The `xs1` and `xd` fields are unused and ignored. + + In modes other than M-mode, `fence` is further affected by `menvcfg.FIOM`, + `senvcfg.FIOM`<% if ext?(:H) %>, and/or `henvcfg.FIOM`<% end %> + as follows: + + .Effective PR/PW/SR/SW in (H)S-mode + [%autowidth,cols=",,,",options="header",separator="!"] + !=== + ! [.rotate]#`menvcfg.FIOM`# ! `pred.PI` + + `pred.PO` + + `succ.SI` + + `succ.SO` + ! -> + + -> + + -> + + -> + ! effective `PR` + + effective `PW` + + effective `SR` + + effective `SW` + + ! 0 ! - ! ! from encoding + ! 1 ! 0 ! ! from encoding + ! 1 ! 1 ! ! 1 + !=== + + .Effective PR/PW/SR/SW in U-mode + [%autowidth,options="header",separator="!",cols=",,,,"] + !=== + ! [.rotate]#`menvcfg.FIOM`# ! [.rotate]#`senvcfg.FIOM`# ! `pred.PI` + + `pred.PO` + + `succ.SI` + + `succ.SO` + ! -> + + -> + + -> + + -> + ! effective `PR` + + effective `PW` + + effective `SR` + + effective `SW` + + ! 0 ! 0 ! - ! ! from encoding + ! 0 ! 1 ! 0 ! ! from encoding + ! 0 ! 1 ! 1 ! ! 1 + ! 1 ! - ! 0 ! ! from encoding + ! 1 ! - ! 1 ! ! 1 + !=== + + <%- if ext?(:H) -%> + .Effective PR/PW/SR/SW in VS-mode and VU-mode + [%autowidth,options="header",separator="!",cols=",,,,"] + !=== + ! [.rotate]#`menvcfg.FIOM`# ! [.rotate]#`henvcfg.FIOM`# ! `pred.PI` + + `pred.PO` + + `succ.SI` + + `succ.SO` + ! -> + + -> + + -> + + -> + ! effective `PR` + + effective `PW` + + effective `SR` + + effective `SW` + + ! 0 ! 0 ! - ! ! from encoding + ! 0 ! 1 ! 0 ! ! from encoding + ! 0 ! 1 ! 1 ! ! 1 + ! 1 ! - ! 0 ! ! from encoding + ! 1 ! - ! 1 ! ! 1 + !=== + <%- end -%> + +definedBy: + extension: + name: I +assembly: pred, succ +encoding: + match: "-----------------000-----0001111" + variables: + - name: fm + location: 31-28 + - name: pred + location: 27-24 + - name: succ + location: 23-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Boolean is_pause; + + if (implemented?(ExtensionName::Zihintpause)) { + if ((pred == 1) && (succ == 0) && (xd == 0) && (xs1 == 0)) { + # this is a PAUSE instruction + is_pause = true; + } + } + + Boolean pred_i = pred[3] == 1; + Boolean pred_o = pred[2] == 1; + Boolean pred_r = pred[1] == 1; + Boolean pred_w = pred[0] == 1; + + Boolean succ_i = succ[3] == 1; + Boolean succ_o = succ[2] == 1; + Boolean succ_r = succ[1] == 1; + Boolean succ_w = succ[0] == 1; + + if (is_pause) { + pause(); + } else { + + # apply FIOM overrides + if (mode() == PrivilegeMode::S) { + if (CSR[menvcfg].FIOM == 1) { + if (pred_i) { pred_r = true; } + if (pred_o) { pred_w = true; } + if (succ_i) { succ_r = true; } + if (succ_o) { succ_w = true; } + } + } else if (mode() == PrivilegeMode::U) { + if ((CSR[menvcfg].FIOM | CSR[senvcfg].FIOM) == 1) { + if (pred_i) { pred_r = true; } + if (pred_o) { pred_w = true; } + if (succ_i) { succ_r = true; } + if (succ_o) { succ_w = true; } + } + } else if (mode() == PrivilegeMode::VS || mode() == PrivilegeMode::VU) { + if ((CSR[menvcfg].FIOM | CSR[henvcfg].FIOM) == 1) { + if (pred_i) { pred_r = true; } + if (pred_o) { pred_w = true; } + if (succ_i) { succ_r = true; } + if (succ_o) { succ_w = true; } + } + } + + fence( + pred_i, pred_o, pred_r, pred_w, + succ_i, succ_o, succ_r, succ_w + ); + } +hints: + - { $ref: inst/I/fence.tso.yaml# } +pseudoinstructions: + - when: (pred == 1) && (succ == 0) && (xd == 0) && (xs1 == 0) + to: pause + - when: (pred == 4'b1111) && (succ == 4'b1111) + to: fence # fence => fence iorw,iorw + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + // If the FIOM bit in menvcfg/senvcfg is set then the I/O bits can imply R/W. + let fiom = is_fiom_active(); + let pred = effective_fence_set(pred, fiom); + let succ = effective_fence_set(succ, fiom); + + match (pred, succ) { + (_ : bits(2) @ 0b11, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_rw_rw()), + (_ : bits(2) @ 0b10, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_r_rw()), + (_ : bits(2) @ 0b10, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_r_r()), + (_ : bits(2) @ 0b11, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_rw_w()), + (_ : bits(2) @ 0b01, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_w_w()), + (_ : bits(2) @ 0b01, _ : bits(2) @ 0b11) => __barrier(Barrier_RISCV_w_rw()), + (_ : bits(2) @ 0b11, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_rw_r()), + (_ : bits(2) @ 0b10, _ : bits(2) @ 0b01) => __barrier(Barrier_RISCV_r_w()), + (_ : bits(2) @ 0b01, _ : bits(2) @ 0b10) => __barrier(Barrier_RISCV_w_r()), + + (_ : bits(4) , _ : bits(2) @ 0b00) => (), + (_ : bits(2) @ 0b00, _ : bits(4) ) => (), + + _ => { print("FIXME: unsupported fence"); + () } + }; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/jal.yaml b/pkg/ifuzz/riscv64/gen/inst/I/jal.yaml new file mode 100644 index 000000000000..b0134f74e473 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/jal.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: jal +long_name: Jump and link +description: | + Jump to a PC-relative offset and store the return + address in xd. +definedBy: + extension: + name: I +assembly: xd, imm +encoding: + match: "-------------------------1101111" + variables: + - name: imm + location: 31|19-12|20|30-21 + left_shift: 1 + sign_extend: true + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +pseudoinstructions: + - when: imm == 0 + to: j xd + - when: xd == x1 + to: jal imm +operation(): | + XReg return_addr = $pc + 4; + + X[xd] = return_addr; + jump_halfword($pc + $signed(imm)); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let t : xlenbits = PC + sign_extend(imm); + /* Extensions get the first checks on the prospective target address. */ + match ext_control_check_pc(t) { + Ext_ControlAddr_Error(e) => { + ext_handle_control_check_error(e); + RETIRE_FAIL + }, + Ext_ControlAddr_OK(target) => { + /* Perform standaxd alignment check */ + if bit_to_bool(target[1]) & not(extension("C")) + then { + handle_mem_exception(target, E_Fetch_Addr_Align()); + RETIRE_FAIL + } else { + X(xd) = get_next_pc(); + set_next_pc(target); + RETIRE_SUCCESS + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/jalr.yaml b/pkg/ifuzz/riscv64/gen/inst/I/jalr.yaml new file mode 100644 index 000000000000..6ebe4b507d43 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/jalr.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: jalr +long_name: Jump and link register +description: | + Jump to an address formed by adding xs1 + to a signed offset then clearing the least + significant bit, and store the return address + in xd. +definedBy: + extension: + name: I +assembly: xd, imm(xs1) +encoding: + match: "-----------------000-----1100111" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +pseudoinstructions: + - when: xd == 0 + to: jr imm(xs1) + - when: (rd == 0 && xs1 == x1 && imm == 0) + to: ret +operation(): | + XReg addr = (X[xs1] + $signed(imm)) & ~MXLEN'1; + XReg returnaddr; + returnaddr = $pc + 4; + + X[xd] = returnaddr; + jump(addr); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + /* For the sequential model, the memory-model definition doesn't work directly + * if xs1 = xd. We would effectively have to keep a regfile for reads and another for + * writes, and swap on instruction completion. This could perhaps be optimized in + * some manner, but for now, we just keep a reoxdered definition to improve simulator + * performance. + */ + let t : xlenbits = X(xs1) + sign_extend(imm); + /* Extensions get the first checks on the prospective target address. */ + match ext_control_check_addr(t) { + Ext_ControlAddr_Error(e) => { + ext_handle_control_check_error(e); + RETIRE_FAIL + }, + Ext_ControlAddr_OK(addr) => { + let target = [addr with 0 = bitzero]; /* clear addr[0] */ + if bit_to_bool(target[1]) & not(extension("C")) then { + handle_mem_exception(target, E_Fetch_Addr_Align()); + RETIRE_FAIL + } else { + X(xd) = get_next_pc(); + set_next_pc(target); + RETIRE_SUCCESS + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/lb.yaml b/pkg/ifuzz/riscv64/gen/inst/I/lb.yaml new file mode 100644 index 000000000000..8e7f7532cd7f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/lb.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lb +long_name: Load byte +description: | + Load 8 bits of data into register `xd` from an + address formed by adding `xs1` to a signed offset. + Sign extend the result. +definedBy: + extension: + name: I +assembly: xd, imm(xs1) +encoding: + match: "-----------------000-----0000011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[xs1] + $signed(imm); + + X[xd] = sext(read_memory<8>(virtual_address, $encoding), 8); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/lbu.yaml b/pkg/ifuzz/riscv64/gen/inst/I/lbu.yaml new file mode 100644 index 000000000000..0f643e62d157 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/lbu.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lbu +long_name: Load byte unsigned +description: | + Load 8 bits of data into register `xd` from an + address formed by adding `xs1` to a signed offset. + Zero extend the result. +definedBy: + extension: + name: I +assembly: xd, imm(xs1) +encoding: + match: "-----------------100-----0000011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[xs1] + $signed(imm); + + X[xd] = read_memory<8>(virtual_address, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/ld.yaml b/pkg/ifuzz/riscv64/gen/inst/I/ld.yaml new file mode 100644 index 000000000000..1310bbe6cc64 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/ld.yaml @@ -0,0 +1,98 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: ld +long_name: Load doubleword +description: | + For RV64, load 64 bits of data into register `xd` from an + address formed by adding `xs1` to a signed offset. + + <% if ext?(:Zilsd) %> + For RV32, Loads a 64-bit value into registers xd and xd+1. + The effective address is obtained by adding + register xs1 to the sign-extended 12-bit offset. + <% end %> + +definedBy: + extension: + anyOf: + - name: I + - name: Zilsd +assembly: xd, imm(xs1) +encoding: + RV32: + match: -----------------011-----0000011 + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + RV64: + match: -----------------011-----0000011 + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[xs1] + $signed(imm); + + if (xlen() == 32) { + if (implemented?(ExtensionName::Zilsd)) { + Bits<64> data = read_memory<64>(virtual_address, $encoding); + + X[xd] = data[31:0]; + X[xd+1] = data[63:32]; + } else { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + } else { + X[xd] = read_memory<64>(virtual_address, $encoding); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/lh.yaml b/pkg/ifuzz/riscv64/gen/inst/I/lh.yaml new file mode 100644 index 000000000000..3c8c54809262 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/lh.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lh +long_name: Load halfword +description: | + Load 16 bits of data into register `xd` from an + address formed by adding `xs1` to a signed offset. + Sign extend the result. +definedBy: + extension: + name: I +assembly: xd, imm(xs1) +encoding: + match: "-----------------001-----0000011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[xs1] + $signed(imm); + + X[xd] = sext(read_memory<16>(virtual_address, $encoding), 16); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/lhu.yaml b/pkg/ifuzz/riscv64/gen/inst/I/lhu.yaml new file mode 100644 index 000000000000..fe47bdaaf25e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/lhu.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lhu +long_name: Load halfword unsigned +description: | + Load 16 bits of data into register `xd` from an + address formed by adding `xs1` to a signed offset. + Zero extend the result. +definedBy: + extension: + name: I +assembly: xd, imm(xs1) +encoding: + match: "-----------------101-----0000011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[xs1] + $signed(imm); + + X[xd] = read_memory<16>(virtual_address, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/lui.yaml b/pkg/ifuzz/riscv64/gen/inst/I/lui.yaml new file mode 100644 index 000000000000..127c514f1ada --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/lui.yaml @@ -0,0 +1,45 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lui +long_name: Load upper immediate +description: Load the zero-extended imm into xd. +definedBy: + extension: + name: I +assembly: xd, imm +encoding: + match: "-------------------------0110111" + variables: + - name: imm + location: 31-12 + left_shift: 12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): X[xd] = $signed(imm); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let off : xlenbits = sign_extend(imm @ 0x000); + let ret : xlenbits = match op { + RISCV_LUI => off, + RISCV_AUIPC => get_arch_pc() + off + }; + X(xd) = ret; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/lw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/lw.yaml new file mode 100644 index 000000000000..ae36a81fdc88 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/lw.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lw +long_name: Load word +description: | + Load 32 bits of data into register `xd` from an + address formed by adding `xs1` to a signed offset. + Sign extend the result. +definedBy: + extension: + name: I +assembly: xd, imm(xs1) +encoding: + match: "-----------------010-----0000011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[xs1] + $signed(imm); + + X[xd] = sext(read_memory<32>(virtual_address, $encoding), 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/lwu.yaml b/pkg/ifuzz/riscv64/gen/inst/I/lwu.yaml new file mode 100644 index 000000000000..5a5adb23bcfb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/lwu.yaml @@ -0,0 +1,70 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lwu +long_name: Load word unsigned +description: | + Load 64 bits of data into register `xd` from an + address formed by adding `xs1` to a signed offset. + Zero extend the result. +definedBy: + allOf: + - xlen: 64 + - extension: + name: I +assembly: xd, imm(xs1) +encoding: + match: "-----------------110-----0000011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[xs1] + $signed(imm); + + X[xd] = read_memory<32>(virtual_address, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(xd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/mret.yaml b/pkg/ifuzz/riscv64/gen/inst/I/mret.yaml new file mode 100644 index 000000000000..f23ce6b1af51 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/mret.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +$schema: "inst_schema.json#" +kind: instruction +name: mret +long_name: Machine-mode Return from Trap +description: | + Return from machine mode after handling a trap. +assembly: "" +definedBy: + extension: + name: Sm +access: + s: never + u: never + vs: never + vu: never +encoding: + match: "00110000001000000000000001110011" +operation(): | + if (CSR[mstatus].MPP != 2'b11) { + CSR[mstatus].MPRV = 0; + } + if (implemented?(ExtensionName::Smdbltrp)) { + if (xlen() == 64) { + CSR[mstatus].MDT = 1'b0; + } else { + CSR[mstatush].MDT = 1'b0; + } + } + CSR[mstatus].MIE = CSR[mstatus].MPIE; + CSR[mstatus].MPIE = 1; + if (CSR[mstatus].MPP == 2'b00) { + set_mode(PrivilegeMode::U); + } else if (CSR[mstatus].MPP == 2'b01) { + set_mode(PrivilegeMode::S); + } else if (CSR[mstatus].MPP == 2'b11) { + set_mode(PrivilegeMode::M); + } + CSR[mstatus].MPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11; + $pc = $bits(CSR[mepc]); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if cur_privilege != Machine + then { handle_illegal(); RETIRE_FAIL } + else if not(ext_check_xret_priv (Machine)) + then { ext_fail_xret_priv(); RETIRE_FAIL } + else { + set_next_pc(exception_handler(cur_privilege, CTL_MRET(), PC)); + RETIRE_SUCCESS + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/or.yaml b/pkg/ifuzz/riscv64/gen/inst/I/or.yaml new file mode 100644 index 000000000000..056228d3ddee --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/or.yaml @@ -0,0 +1,61 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: or +long_name: Or +description: Or xs1 with xs2, and store the result in xd +definedBy: + extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------110-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): X[xd] = X[xs1] | X[xs2]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let result : xlenbits = match op { + RISCV_ADD => xs1_val + xs2_val, + RISCV_SLT => zero_extend(bool_to_bits(xs1_val <_s xs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(xs1_val <_u xs2_val)), + RISCV_AND => xs1_val & xs2_val, + RISCV_OR => xs1_val | xs2_val, + RISCV_XOR => xs1_val ^ xs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then xs1_val << (xs2_val[4..0]) + else xs1_val << (xs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then xs1_val >> (xs2_val[4..0]) + else xs1_val >> (xs2_val[5..0]), + RISCV_SUB => xs1_val - xs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, xs2_val[4..0]) + else shift_right_arith64(xs1_val, xs2_val[5..0]) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/ori.yaml b/pkg/ifuzz/riscv64/gen/inst/I/ori.yaml new file mode 100644 index 000000000000..9351e1da57a3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/ori.yaml @@ -0,0 +1,56 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: ori +long_name: Or immediate +description: Or an immediate to the value in xs1, and store the result in xd +definedBy: + extension: + name: I +assembly: xd, xs1, imm +encoding: + match: "-----------------110-----0010011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +hints: + - { $ref: inst/Zicbop/prefetch.r.yaml# } + - { $ref: inst/Zicbop/prefetch.w.yaml# } + - { $ref: inst/Zicbop/prefetch.i.yaml# } +operation(): | + X[xd] = X[xs1] | $signed(imm); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let immext : xlenbits = sign_extend(imm); + let result : xlenbits = match op { + RISCV_ADDI => xs1_val + immext, + RISCV_SLTI => zero_extend(bool_to_bits(xs1_val <_s immext)), + RISCV_SLTIU => zero_extend(bool_to_bits(xs1_val <_u immext)), + RISCV_ANDI => xs1_val & immext, + RISCV_ORI => xs1_val | immext, + RISCV_XORI => xs1_val ^ immext + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sb.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sb.yaml new file mode 100644 index 000000000000..5da1f2339417 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sb.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sb +long_name: Store byte +description: | + Store 8 bits of data from register `xs2` to an + address formed by adding `xs1` to a signed offset. +definedBy: + extension: + name: I +assembly: xs2, imm(xs1) +encoding: + match: "-----------------000-----0100011" + variables: + - name: imm + location: 31-25|11-7 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[xs1] + $signed(imm); + + write_memory<8>(virtual_address, X[xs2][7:0], $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Write(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => { + let eares : MemoryOpResult(unit) = match width { + BYTE => mem_write_ea(paddr, 1, aq, rl, false), + HALF => mem_write_ea(paddr, 2, aq, rl, false), + WORD => mem_write_ea(paddr, 4, aq, rl, false), + DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let xs2_val = X(xs2); + let res : MemoryOpResult(bool) = match (width) { + BYTE => mem_write_value(paddr, 1, xs2_val[7..0], aq, rl, false), + HALF => mem_write_value(paddr, 2, xs2_val[15..0], aq, rl, false), + WORD => mem_write_value(paddr, 4, xs2_val[31..0], aq, rl, false), + DOUBLE if sizeof(xlen) >= 64 + => mem_write_value(paddr, 8, xs2_val, aq, rl, false), + _ => report_invalid_width(__FILE__, __LINE__, width, "store"), + }; + match (res) { + MemValue(true) => RETIRE_SUCCESS, + MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sd.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sd.yaml new file mode 100644 index 000000000000..c5c43620714c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sd.yaml @@ -0,0 +1,110 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sd +long_name: Store doubleword +description: | + For RV64, store 64 bits of data from register `xs2` to an + address formed by adding `xs1` to a signed offset. + <% if ext?(:Zilsd) %> + For RV32, store doubleword from even/odd register pair. + <% end %> +definedBy: + extension: + anyOf: + - name: I + - name: Zilsd +assembly: xs2, imm(xs1) +encoding: + RV32: + match: -----------------011-----0100011 + variables: + - name: imm + location: 31-25|11-7 + - name: xs2 + not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + location: 24-20 + - name: xs1 + location: 19-15 + RV64: + match: -----------------011-----0100011 + variables: + - name: imm + location: 31-25|11-7 + sign_extend: true + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + Bits<64> data; + XReg virtual_address = X[xs1] + $signed(imm); + + if (xlen() == 32) { + if (implemented?(ExtensionName::Zclsd)) { + data = {X[xs2 + 1], X[xs2]}; + } else { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + } else { + data = X[xs2]; + } + + write_memory<64>(virtual_address, data, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Write(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => { + let eares : MemoryOpResult(unit) = match width { + BYTE => mem_write_ea(paddr, 1, aq, rl, false), + HALF => mem_write_ea(paddr, 2, aq, rl, false), + WORD => mem_write_ea(paddr, 4, aq, rl, false), + DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let xs2_val = X(xs2); + let res : MemoryOpResult(bool) = match (width) { + BYTE => mem_write_value(paddr, 1, xs2_val[7..0], aq, rl, false), + HALF => mem_write_value(paddr, 2, xs2_val[15..0], aq, rl, false), + WORD => mem_write_value(paddr, 4, xs2_val[31..0], aq, rl, false), + DOUBLE if sizeof(xlen) >= 64 + => mem_write_value(paddr, 8, xs2_val, aq, rl, false), + _ => report_invalid_width(__FILE__, __LINE__, width, "store"), + }; + match (res) { + MemValue(true) => RETIRE_SUCCESS, + MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sh.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sh.yaml new file mode 100644 index 000000000000..fc4c9e099c3a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sh.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sh +long_name: Store halfword +description: | + Store 16 bits of data from register `xs2` to an + address formed by adding `xs1` to a signed offset. +definedBy: + extension: + name: I +assembly: xs2, imm(xs1) +encoding: + match: "-----------------001-----0100011" + variables: + - name: imm + location: 31-25|11-7 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[xs1] + $signed(imm); + + write_memory<16>(virtual_address, X[xs2][15:0], $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Write(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => { + let eares : MemoryOpResult(unit) = match width { + BYTE => mem_write_ea(paddr, 1, aq, rl, false), + HALF => mem_write_ea(paddr, 2, aq, rl, false), + WORD => mem_write_ea(paddr, 4, aq, rl, false), + DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let xs2_val = X(xs2); + let res : MemoryOpResult(bool) = match (width) { + BYTE => mem_write_value(paddr, 1, xs2_val[7..0], aq, rl, false), + HALF => mem_write_value(paddr, 2, xs2_val[15..0], aq, rl, false), + WORD => mem_write_value(paddr, 4, xs2_val[31..0], aq, rl, false), + DOUBLE if sizeof(xlen) >= 64 + => mem_write_value(paddr, 8, xs2_val, aq, rl, false), + _ => report_invalid_width(__FILE__, __LINE__, width, "store"), + }; + match (res) { + MemValue(true) => RETIRE_SUCCESS, + MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sll.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sll.yaml new file mode 100644 index 000000000000..d45e9aebce51 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sll.yaml @@ -0,0 +1,67 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sll +long_name: Shift left logical +description: | + Shift the value in `xs1` left by the value in the lower 6 bits of `xs2`, and store the result in `xd`. +definedBy: + extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------001-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (xlen() == 64) { + X[xd] = X[xs1] << X[xs2][5:0]; + } else { + X[xd] = X[xs1] << X[xs2][4:0]; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let result : xlenbits = match op { + RISCV_ADD => xs1_val + xs2_val, + RISCV_SLT => zero_extend(bool_to_bits(xs1_val <_s xs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(xs1_val <_u xs2_val)), + RISCV_AND => xs1_val & xs2_val, + RISCV_OR => xs1_val | xs2_val, + RISCV_XOR => xs1_val ^ xs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then xs1_val << (xs2_val[4..0]) + else xs1_val << (xs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then xs1_val >> (xs2_val[4..0]) + else xs1_val >> (xs2_val[5..0]), + RISCV_SUB => xs1_val - xs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, xs2_val[4..0]) + else shift_right_arith64(xs1_val, xs2_val[5..0]) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/slli.yaml b/pkg/ifuzz/riscv64/gen/inst/I/slli.yaml new file mode 100644 index 000000000000..035e5c9aa587 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/slli.yaml @@ -0,0 +1,66 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: slli +long_name: Shift left logical immediate +description: Shift the value in xs1 left by shamt, and store the result in xd +definedBy: + extension: + name: I +assembly: xd, xs1, shamt +encoding: + RV32: + match: 0000000----------001-----0010011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + RV64: + match: 000000-----------001-----0010011 + variables: + - name: shamt + location: 25-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + # shamt is between 0-(XLEN-1) + X[xd] = X[xs1] << shamt; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + /* the decoder guaxd should ensure that shamt[5] = 0 for RV32 */ + let result : xlenbits = match op { + RISCV_SLLI => if sizeof(xlen) == 32 + then xs1_val << shamt[4..0] + else xs1_val << shamt, + RISCV_SRLI => if sizeof(xlen) == 32 + then xs1_val >> shamt[4..0] + else xs1_val >> shamt, + RISCV_SRAI => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, shamt[4..0]) + else shift_right_arith64(xs1_val, shamt) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/slliw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/slliw.yaml new file mode 100644 index 000000000000..07e76efc4ac9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/slliw.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: slliw +long_name: Shift left logical immediate word +description: + Shift the 32-bit value in xs1 left by shamt, and store the sign-extended + result in xd +definedBy: + allOf: + - xlen: 64 + - extension: + name: I +assembly: xd, xs1, shamt +encoding: + match: 0000000----------001-----0011011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + # shamt is between 0-32 + X[xd] = sext(X[xs1] << shamt, 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = (X(xs1))[31..0]; + let result : bits(32) = match op { + RISCV_SLLIW => xs1_val << shamt, + RISCV_SRLIW => xs1_val >> shamt, + RISCV_SRAIW => shift_right_arith32(xs1_val, shamt) + }; + X(xd) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sllw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sllw.yaml new file mode 100644 index 000000000000..d93396f251da --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sllw.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sllw +long_name: Shift left logical word +description: | + Shift the 32-bit value in `xs1` left by the value in the lower 5 bits of `xs2`, and store the sign-extended result in `xd`. +definedBy: + allOf: + - xlen: 64 + - extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------001-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): X[xd] = sext(X[xs1] << X[xs2][4:0], 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = (X(xs1))[31..0]; + let xs2_val = (X(xs2))[31..0]; + let result : bits(32) = match op { + RISCV_ADDW => xs1_val + xs2_val, + RISCV_SUBW => xs1_val - xs2_val, + RISCV_SLLW => xs1_val << (xs2_val[4..0]), + RISCV_SRLW => xs1_val >> (xs2_val[4..0]), + RISCV_SRAW => shift_right_arith32(xs1_val, xs2_val[4..0]) + }; + X(xd) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/slt.yaml b/pkg/ifuzz/riscv64/gen/inst/I/slt.yaml new file mode 100644 index 000000000000..a37c8e43ee6d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/slt.yaml @@ -0,0 +1,72 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: slt +long_name: Set on less than +description: | + Places the value 1 in register `xd` if register `xs1` is less than the value in register `xs2`, where + both sources are treated as signed numbers, else 0 is written to `xd`. +definedBy: + extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------010-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: xs2 == 0 + to: sltz xd,xs1 + - when: xs1 == 0 + to: sgtz xd,xs2 +operation(): | + XReg src1 = X[xs1]; + XReg src2 = X[xs2]; + + X[xd] = ($signed(src1) < $signed(src2)) ? '1 : '0; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let result : xlenbits = match op { + RISCV_ADD => xs1_val + xs2_val, + RISCV_SLT => zero_extend(bool_to_bits(xs1_val <_s xs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(xs1_val <_u xs2_val)), + RISCV_AND => xs1_val & xs2_val, + RISCV_OR => xs1_val | xs2_val, + RISCV_XOR => xs1_val ^ xs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then xs1_val << (xs2_val[4..0]) + else xs1_val << (xs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then xs1_val >> (xs2_val[4..0]) + else xs1_val >> (xs2_val[5..0]), + RISCV_SUB => xs1_val - xs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, xs2_val[4..0]) + else shift_right_arith64(xs1_val, xs2_val[5..0]) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/slti.yaml b/pkg/ifuzz/riscv64/gen/inst/I/slti.yaml new file mode 100644 index 000000000000..4ba41b352906 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/slti.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: slti +long_name: Set on less than immediate +description: | + Places the value 1 in register `xd` if register `xs1` is less than the sign-extended immediate + when both are treated as signed numbers, else 0 is written to `xd`. +definedBy: + extension: + name: I +assembly: xd, xs1, imm +encoding: + match: "-----------------010-----0010011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + X[xd] = ($signed(X[xs1]) < $signed(imm)) ? '1 : '0; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let immext : xlenbits = sign_extend(imm); + let result : xlenbits = match op { + RISCV_ADDI => xs1_val + immext, + RISCV_SLTI => zero_extend(bool_to_bits(xs1_val <_s immext)), + RISCV_SLTIU => zero_extend(bool_to_bits(xs1_val <_u immext)), + RISCV_ANDI => xs1_val & immext, + RISCV_ORI => xs1_val | immext, + RISCV_XORI => xs1_val ^ immext + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sltiu.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sltiu.yaml new file mode 100644 index 000000000000..15140038c3ff --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sltiu.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sltiu +long_name: Set on less than immediate unsigned +description: | + Places the value 1 in register `xd` if register `xs1` is less than the sign-extended immediate + when both are treated as unsigned numbers (_i.e._, the immediate is first sign-extended to + XLEN bits then treated as an unsigned number), else 0 is written to `xd`. + + NOTE: `sltiu xd, xs1, 1` sets `xd` to 1 if `xs1` equals zero, otherwise sets `xd` to 0 + (assembler pseudoinstruction `SEQZ xd, rs`). +definedBy: + extension: + name: I +assembly: xd, xs1, imm +encoding: + match: "-----------------011-----0010011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: imm == 1 + to: seqz xd,xs1 +operation(): | + Bits sign_extend_imm = $signed(imm); + X[xd] = (X[xs1] < sign_extend_imm) ? 1 : 0; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let immext : xlenbits = sign_extend(imm); + let result : xlenbits = match op { + RISCV_ADDI => xs1_val + immext, + RISCV_SLTI => zero_extend(bool_to_bits(xs1_val <_s immext)), + RISCV_SLTIU => zero_extend(bool_to_bits(xs1_val <_u immext)), + RISCV_ANDI => xs1_val & immext, + RISCV_ORI => xs1_val | immext, + RISCV_XORI => xs1_val ^ immext + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sltu.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sltu.yaml new file mode 100644 index 000000000000..faa08872519c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sltu.yaml @@ -0,0 +1,67 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sltu +long_name: Set on less than unsigned +description: | + Places the value 1 in register `xd` if register `xs1` is less than the value in register `xs2`, where + both sources are treated as unsigned numbers, else 0 is written to `xd`. +definedBy: + extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------011-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: xs1 == 0 + to: snez xd,xs2 +operation(): | + X[xd] = (X[xs1] < X[xs2]) ? 1 : 0; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let result : xlenbits = match op { + RISCV_ADD => xs1_val + xs2_val, + RISCV_SLT => zero_extend(bool_to_bits(xs1_val <_s xs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(xs1_val <_u xs2_val)), + RISCV_AND => xs1_val & xs2_val, + RISCV_OR => xs1_val | xs2_val, + RISCV_XOR => xs1_val ^ xs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then xs1_val << (xs2_val[4..0]) + else xs1_val << (xs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then xs1_val >> (xs2_val[4..0]) + else xs1_val >> (xs2_val[5..0]), + RISCV_SUB => xs1_val - xs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, xs2_val[4..0]) + else shift_right_arith64(xs1_val, xs2_val[5..0]) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sra.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sra.yaml new file mode 100644 index 000000000000..7c1dabeaedfc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sra.yaml @@ -0,0 +1,67 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sra +long_name: Shift right arithmetic +description: | + Arithmetic shift the value in `xs1` right by the value in the lower 5 bits of `xs2`, and store the result in `xd`. +definedBy: + extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0100000----------101-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (xlen() == 64) { + X[xd] = X[xs1] >>> X[xs2][5:0]; + } else { + X[xd] = X[xs1] >>> X[xs2][4:0]; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let result : xlenbits = match op { + RISCV_ADD => xs1_val + xs2_val, + RISCV_SLT => zero_extend(bool_to_bits(xs1_val <_s xs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(xs1_val <_u xs2_val)), + RISCV_AND => xs1_val & xs2_val, + RISCV_OR => xs1_val | xs2_val, + RISCV_XOR => xs1_val ^ xs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then xs1_val << (xs2_val[4..0]) + else xs1_val << (xs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then xs1_val >> (xs2_val[4..0]) + else xs1_val >> (xs2_val[5..0]), + RISCV_SUB => xs1_val - xs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, xs2_val[4..0]) + else shift_right_arith64(xs1_val, xs2_val[5..0]) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/srai.yaml b/pkg/ifuzz/riscv64/gen/inst/I/srai.yaml new file mode 100644 index 000000000000..0a1970f6990b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/srai.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: srai +long_name: Shift right arithmetic immediate +description: | + Arithmetic shift (the original sign bit is copied into the vacated upper bits) the + value in xs1 right by shamt, and store the result in xd. +definedBy: + extension: + name: I +assembly: xd, xs1, shamt +encoding: + RV32: + match: 0100000----------101-----0010011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + RV64: + match: 010000-----------101-----0010011 + variables: + - name: shamt + location: 25-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + # shamt is between 0-63 + X[xd] = X[xs1] >>> shamt; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + /* the decoder guaxd should ensure that shamt[5] = 0 for RV32 */ + let result : xlenbits = match op { + RISCV_SLLI => if sizeof(xlen) == 32 + then xs1_val << shamt[4..0] + else xs1_val << shamt, + RISCV_SRLI => if sizeof(xlen) == 32 + then xs1_val >> shamt[4..0] + else xs1_val >> shamt, + RISCV_SRAI => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, shamt[4..0]) + else shift_right_arith64(xs1_val, shamt) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sraiw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sraiw.yaml new file mode 100644 index 000000000000..d49c86d2bd63 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sraiw.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sraiw +long_name: Shift right arithmetic immediate word +description: | + Arithmetic shift (the original sign bit is copied into the vacated upper bits) the + 32-bit value in xs1 right by shamt, and store the sign-extended result in xd. +definedBy: + allOf: + - xlen: 64 + - extension: + name: I +assembly: xd, xs1, shamt +encoding: + match: 0100000----------101-----0011011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + # shamt is between 0-32 + XReg operand = sext(X[xs1], 32); + X[xd] = sext(operand >>> shamt, 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = (X(xs1))[31..0]; + let result : bits(32) = match op { + RISCV_SLLIW => xs1_val << shamt, + RISCV_SRLIW => xs1_val >> shamt, + RISCV_SRAIW => shift_right_arith32(xs1_val, shamt) + }; + X(xd) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sraw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sraw.yaml new file mode 100644 index 000000000000..89a3e9c56378 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sraw.yaml @@ -0,0 +1,56 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sraw +long_name: Shift right arithmetic word +description: | + Arithmetic shift the 32-bit value in `xs1` right by the value in the lower 5 bits of `xs2`, and store the sign-extended result in `xd`. +definedBy: + allOf: + - xlen: 64 + - extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0100000----------101-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + XReg operand1 = sext(X[xs1], 32); + + X[xd] = sext(operand1 >>> X[xs2][4:0], 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = (X(xs1))[31..0]; + let xs2_val = (X(xs2))[31..0]; + let result : bits(32) = match op { + RISCV_ADDW => xs1_val + xs2_val, + RISCV_SUBW => xs1_val - xs2_val, + RISCV_SLLW => xs1_val << (xs2_val[4..0]), + RISCV_SRLW => xs1_val >> (xs2_val[4..0]), + RISCV_SRAW => shift_right_arith32(xs1_val, xs2_val[4..0]) + }; + X(xd) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/srl.yaml b/pkg/ifuzz/riscv64/gen/inst/I/srl.yaml new file mode 100644 index 000000000000..e6fda17749ac --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/srl.yaml @@ -0,0 +1,67 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: srl +long_name: Shift right logical +description: | + Logical shift the value in `xs1` right by the value in the lower bits of `xs2`, and store the result in `xd`. +definedBy: + extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------101-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (xlen() == 64) { + X[xd] = X[xs1] >> X[xs2][5:0]; + } else { + X[xd] = X[xs1] >> X[xs2][4:0]; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let result : xlenbits = match op { + RISCV_ADD => xs1_val + xs2_val, + RISCV_SLT => zero_extend(bool_to_bits(xs1_val <_s xs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(xs1_val <_u xs2_val)), + RISCV_AND => xs1_val & xs2_val, + RISCV_OR => xs1_val | xs2_val, + RISCV_XOR => xs1_val ^ xs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then xs1_val << (xs2_val[4..0]) + else xs1_val << (xs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then xs1_val >> (xs2_val[4..0]) + else xs1_val >> (xs2_val[5..0]), + RISCV_SUB => xs1_val - xs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, xs2_val[4..0]) + else shift_right_arith64(xs1_val, xs2_val[5..0]) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/srli.yaml b/pkg/ifuzz/riscv64/gen/inst/I/srli.yaml new file mode 100644 index 000000000000..9c3fd2f19b04 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/srli.yaml @@ -0,0 +1,65 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +$schema: "inst_schema.json#" +kind: instruction +name: srli +long_name: Shift right logical immediate +description: Shift the value in xs1 right by shamt, and store the result in xd +definedBy: + extension: + name: I +assembly: xd, xs1, shamt +encoding: + RV32: + match: 0000000----------101-----0010011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + RV64: + match: 000000-----------101-----0010011 + variables: + - name: shamt + location: 25-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + # shamt is between 0-63 + X[xd] = X[xs1] >> shamt; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + /* the decoder guaxd should ensure that shamt[5] = 0 for RV32 */ + let result : xlenbits = match op { + RISCV_SLLI => if sizeof(xlen) == 32 + then xs1_val << shamt[4..0] + else xs1_val << shamt, + RISCV_SRLI => if sizeof(xlen) == 32 + then xs1_val >> shamt[4..0] + else xs1_val >> shamt, + RISCV_SRAI => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, shamt[4..0]) + else shift_right_arith64(xs1_val, shamt) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/srliw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/srliw.yaml new file mode 100644 index 000000000000..f9ad0f75e767 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/srliw.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: srliw +long_name: Shift right logical immediate word +description: + Shift the 32-bit value in xs1 right by shamt, and store the sign-extended + result in xd +definedBy: + allOf: + - xlen: 64 + - extension: + name: I +assembly: xd, xs1, shamt +encoding: + match: 0000000----------101-----0011011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + # shamt is between 0-31 + XReg operand = X[xs1][31:0]; + + X[xd] = sext(operand >> shamt, 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = (X(xs1))[31..0]; + let result : bits(32) = match op { + RISCV_SLLIW => xs1_val << shamt, + RISCV_SRLIW => xs1_val >> shamt, + RISCV_SRAIW => shift_right_arith32(xs1_val, shamt) + }; + X(xd) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/srlw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/srlw.yaml new file mode 100644 index 000000000000..f2a5244fc467 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/srlw.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: srlw +long_name: Shift right logical word +description: | + Logical shift the 32-bit value in `xs1` right by the value in the lower 5 bits of `xs2`, and store the sign-extended result in `xd`. +definedBy: + allOf: + - xlen: 64 + - extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------101-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): X[xd] = sext(X[xs1][31:0] >> X[xs2][4:0], 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = (X(xs1))[31..0]; + let xs2_val = (X(xs2))[31..0]; + let result : bits(32) = match op { + RISCV_ADDW => xs1_val + xs2_val, + RISCV_SUBW => xs1_val - xs2_val, + RISCV_SLLW => xs1_val << (xs2_val[4..0]), + RISCV_SRLW => xs1_val >> (xs2_val[4..0]), + RISCV_SRAW => shift_right_arith32(xs1_val, xs2_val[4..0]) + }; + X(xd) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sub.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sub.yaml new file mode 100644 index 000000000000..35eea26c3c22 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sub.yaml @@ -0,0 +1,67 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sub +long_name: Subtract +description: Subtract the value in xs2 from xs1, and store the result in xd +definedBy: + extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0100000----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: xs1 == 0 + to: neg xd,xs2 +operation(): | + XReg t0 = X[xs1]; + XReg t1 = X[xs2]; + X[xd] = t0 - t1; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let result : xlenbits = match op { + RISCV_ADD => xs1_val + xs2_val, + RISCV_SLT => zero_extend(bool_to_bits(xs1_val <_s xs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(xs1_val <_u xs2_val)), + RISCV_AND => xs1_val & xs2_val, + RISCV_OR => xs1_val | xs2_val, + RISCV_XOR => xs1_val ^ xs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then xs1_val << (xs2_val[4..0]) + else xs1_val << (xs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then xs1_val >> (xs2_val[4..0]) + else xs1_val >> (xs2_val[5..0]), + RISCV_SUB => xs1_val - xs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, xs2_val[4..0]) + else shift_right_arith64(xs1_val, xs2_val[5..0]) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/subw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/subw.yaml new file mode 100644 index 000000000000..91f1e0706810 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/subw.yaml @@ -0,0 +1,60 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: subw +long_name: Subtract word +description: + Subtract the 32-bit values in xs2 from xs1, and store the sign-extended + result in xd +definedBy: + allOf: + - xlen: 64 + - extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0100000----------000-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: xs1 == 0 + to: negw xd,xs2 +operation(): | + Bits<32> t0 = X[xs1][31:0]; + Bits<32> t1 = X[xs2][31:0]; + X[xd] = sext(t0 - t1, 32); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = (X(xs1))[31..0]; + let xs2_val = (X(xs2))[31..0]; + let result : bits(32) = match op { + RISCV_ADDW => xs1_val + xs2_val, + RISCV_SUBW => xs1_val - xs2_val, + RISCV_SLLW => xs1_val << (xs2_val[4..0]), + RISCV_SRLW => xs1_val >> (xs2_val[4..0]), + RISCV_SRAW => shift_right_arith32(xs1_val, xs2_val[4..0]) + }; + X(xd) = sign_extend(result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/sw.yaml b/pkg/ifuzz/riscv64/gen/inst/I/sw.yaml new file mode 100644 index 000000000000..3d3e0064e647 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/sw.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sw +long_name: Store word +description: | + Store 32 bits of data from register `xs2` to an + address formed by adding `xs1` to a signed offset. +definedBy: + extension: + name: I +assembly: xs2, imm(xs1) +encoding: + match: "-----------------010-----0100011" + variables: + - name: imm + location: 31-25|11-7 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +operation(): | + XReg virtual_address = X[xs1] + $signed(imm); + + write_memory<32>(virtual_address, X[xs2][31:0], $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(xs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(xs1, offset, Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Write(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => { + let eares : MemoryOpResult(unit) = match width { + BYTE => mem_write_ea(paddr, 1, aq, rl, false), + HALF => mem_write_ea(paddr, 2, aq, rl, false), + WORD => mem_write_ea(paddr, 4, aq, rl, false), + DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let xs2_val = X(xs2); + let res : MemoryOpResult(bool) = match (width) { + BYTE => mem_write_value(paddr, 1, xs2_val[7..0], aq, rl, false), + HALF => mem_write_value(paddr, 2, xs2_val[15..0], aq, rl, false), + WORD => mem_write_value(paddr, 4, xs2_val[31..0], aq, rl, false), + DOUBLE if sizeof(xlen) >= 64 + => mem_write_value(paddr, 8, xs2_val, aq, rl, false), + _ => report_invalid_width(__FILE__, __LINE__, width, "store"), + }; + match (res) { + MemValue(true) => RETIRE_SUCCESS, + MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/wfi.yaml b/pkg/ifuzz/riscv64/gen/inst/I/wfi.yaml new file mode 100644 index 000000000000..c91d1151210e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/wfi.yaml @@ -0,0 +1,131 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: wfi +long_name: Wait for interrupt +description: | + Can causes the processor to enter a low-power state until the next interrupt occurs. + + <%- if ext?(:H) -%> + The behavior of `wfi` is affected by the `mstatus.TW` + and `hstatus.VTW` bits, as summarized below. + + [%autowidth,%footer] + |=== + .2+| [.rotate]#`mstatus.TW`# .2+| [.rotate]#`hstatus.VTW`# 4+^.>| `wfi` behavior + h| HS-mode h| U-mode h| VS-mode h| in VU-mode + + | 0 | 0 | Wait | Trap (I) | Wait | Trap (V) + | 0 | 1 | Wait | Trap (I) | Trap (V) | Trap (V) + | 1 | - | Trap (I) | Trap (I) | Trap (I) | Trap (I) + + 6+| Trap (I) - Trap with `Illegal Instruction` code + + Trap (V) - Trap with `Virtual Instruction` code + |=== + + <%- else -%> + The `wfi` instruction is also affected by `mstatus.TW`, as shown below: + + [%autowidth,%footer] + |=== + .2+| [.rotate]#`mstatus.TW`# 2+^.>| `wfi` behavior + h| S-mode h| U-mode + + | 0 | Wait | Trap (I) + | 1 | Trap (I) | Trap (I) + + 3+| Trap (I) - Trap with `Illegal Instruction` code + |=== + + <%- end -%> + + When `wfi` is marked as causing a trap above, the implementation is allowed to wait + for an unspecified period of time to see if an interrupt occurs before raising the trap. + That period of time can be zero (_i.e._, `wfi` always causes a trap in the cases identified + above). +definedBy: + extension: + name: Sm +assembly: "" +encoding: + match: "00010000010100000000000001110011" +access: + s: sometimes + u: sometimes + vs: sometimes + vu: sometimes +access_detail: | + <%- if ext?(:H) -%> + The behavior of `wfi` is affected by the `mstatus.TW` + and `hstatus.VTW` bits, as summarized below. + + [%autowidth,%footer] + |=== + .2+| [.rotate]#`mstatus.TW`# .2+| [.rotate]#`hstatus.VTW`# 4+^.>| `wfi` behavior + h| HS-mode h| U-mode h| VS-mode h| in VU-mode + + | 0 | 0 | Wait | Trap (I) | Wait | Trap (V) + | 0 | 1 | Wait | Trap (I) | Trap (V) | Trap (V) + | 1 | - | Trap (I) | Trap (I) | Trap (I) | Trap (I) + + 6+| Trap (I) - Trap with `Illegal Instruction` code + + Trap (V) - Trap with `Virtual Instruction` code + |=== + + <%- else -%> + The `wfi` instruction is also affected by `mstatus.TW`, as shown below: + + [%autowidth,%footer] + |=== + .2+| [.rotate]#`mstatus.TW`# 2+^.>| `wfi` behavior + h| S-mode h| U-mode + + | 0 | Wait | Trap (I) + | 1 | Trap (I) | Trap (I) + + 3+| Trap (I) - Trap with `Illegal Instruction` code + |=== + + <%- end -%> +operation(): | + # first, perform all the access checks + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + if ((CSR[misa].S == 1) && (CSR[mstatus].TW == 1'b1)) { + if (mode() != PrivilegeMode::M) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + } + if (CSR[misa].H == 1) { + if (CSR[hstatus].VTW == 1'b0) { + if (mode() == PrivilegeMode::VU) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + } else if (CSR[hstatus].VTW == 1'b1) { + if ((mode() == PrivilegeMode::VS) || (mode() == PrivilegeMode::VU)) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + } + } + + # passed, so now do the wait + wfi(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + match cur_privilege { + Machine => { platform_wfi(); RETIRE_SUCCESS }, + Supervisor => if mstatus.TW() == 0b1 + then { handle_illegal(); RETIRE_FAIL } + else { platform_wfi(); RETIRE_SUCCESS }, + User => { handle_illegal(); RETIRE_FAIL } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/xor.yaml b/pkg/ifuzz/riscv64/gen/inst/I/xor.yaml new file mode 100644 index 000000000000..2a2abd986b65 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/xor.yaml @@ -0,0 +1,61 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: xor +long_name: Exclusive Or +description: Exclusive or xs1 with xs2, and store the result in xd +definedBy: + extension: + name: I +assembly: xd, xs1, xs2 +encoding: + match: 0000000----------100-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): X[xd] = X[xs1] ^ X[xs2]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let xs2_val = X(xs2); + let result : xlenbits = match op { + RISCV_ADD => xs1_val + xs2_val, + RISCV_SLT => zero_extend(bool_to_bits(xs1_val <_s xs2_val)), + RISCV_SLTU => zero_extend(bool_to_bits(xs1_val <_u xs2_val)), + RISCV_AND => xs1_val & xs2_val, + RISCV_OR => xs1_val | xs2_val, + RISCV_XOR => xs1_val ^ xs2_val, + RISCV_SLL => if sizeof(xlen) == 32 + then xs1_val << (xs2_val[4..0]) + else xs1_val << (xs2_val[5..0]), + RISCV_SRL => if sizeof(xlen) == 32 + then xs1_val >> (xs2_val[4..0]) + else xs1_val >> (xs2_val[5..0]), + RISCV_SUB => xs1_val - xs2_val, + RISCV_SRA => if sizeof(xlen) == 32 + then shift_right_arith32(xs1_val, xs2_val[4..0]) + else shift_right_arith64(xs1_val, xs2_val[5..0]) + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/I/xori.yaml b/pkg/ifuzz/riscv64/gen/inst/I/xori.yaml new file mode 100644 index 000000000000..29f0d3ddd19b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/I/xori.yaml @@ -0,0 +1,56 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: xori +long_name: Exclusive Or immediate +description: + Exclusive or an immediate to the value in xs1, and store the result in + xd +definedBy: + extension: + name: I +assembly: xd, xs1, imm +encoding: + match: "-----------------100-----0010011" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: $signed(imm) == -1 + to: not xd,xs1 +operation(): X[xd] = X[xs1] ^ $signed(imm); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let xs1_val = X(xs1); + let immext : xlenbits = sign_extend(imm); + let result : xlenbits = match op { + RISCV_ADDI => xs1_val + immext, + RISCV_SLTI => zero_extend(bool_to_bits(xs1_val <_s immext)), + RISCV_SLTIU => zero_extend(bool_to_bits(xs1_val <_u immext)), + RISCV_ANDI => xs1_val & immext, + RISCV_ORI => xs1_val | immext, + RISCV_XORI => xs1_val ^ immext + }; + X(xd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/div.yaml b/pkg/ifuzz/riscv64/gen/inst/M/div.yaml new file mode 100644 index 000000000000..1368d0e97434 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/div.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: div +long_name: Signed division +description: | + Divide xs1 by xs2, and store the result in xd. The remainder is discarded. + + Division by zero will put -1 into xd. + + Division resulting in signed overflow (when most negative number is divided by -1) + will put the most negative number into xd; +definedBy: + extension: + name: M +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------100-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg src1 = X[xs1]; + XReg src2 = X[xs2]; + + # smallest signed value + XReg signed_min = (xlen() == 32) ? $signed({1'b1, {31{1'b0}}}) : {1'b1, {63{1'b0}}}; + + if (src2 == 0) { + # division by zero. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be -1 + X[xd] = {MXLEN{1'b1}}; + + } else if ((src1 == signed_min) && (src2 == {MXLEN{1'b1}})) { + # signed overflow. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be the most negative number (-2^(MXLEN-1)) + X[xd] = signed_min; + + } else { + # no special case, just divide + X[xd] = $signed(src1) / $signed(src2); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") then { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); + let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); + /* check for signed overflow */ + let q': int = if s & q > xlen_max_signed then xlen_min_signed else q; + X(rd) = to_bits(sizeof(xlen), q'); + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/divu.yaml b/pkg/ifuzz/riscv64/gen/inst/M/divu.yaml new file mode 100644 index 000000000000..f3eb696f1635 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/divu.yaml @@ -0,0 +1,71 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: divu +long_name: Unsigned division +description: | + Divide unsigned values in xs1 by xs2, and store the result in xd. + + The remainder is discarded. + + If the value in xs2 is zero, xd gets the largest unsigned value. +definedBy: + extension: + name: M +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------101-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg src1 = X[xs1]; + XReg src2 = X[xs2]; + + if (src2 == 0) { + # division by zero. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be -1 + X[xd] = {MXLEN{1'b1}}; + } else { + X[xd] = src1 / src2; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") then { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); + let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); + /* check for signed overflow */ + let q': int = if s & q > xlen_max_signed then xlen_min_signed else q; + X(rd) = to_bits(sizeof(xlen), q'); + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/divuw.yaml b/pkg/ifuzz/riscv64/gen/inst/M/divuw.yaml new file mode 100644 index 000000000000..2b287253e645 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/divuw.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: divuw +long_name: Unsigned 32-bit division +description: | + Divide the unsigned 32-bit values in xs1 and xs2, and store the sign-extended result in xd. + + The remainder is discarded. + + If the value in xs2 is zero, xd is written with all 1s. +definedBy: + allOf: + - xlen: 64 + - extension: + name: M +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------101-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + Bits<32> src1 = X[xs1][31:0]; + Bits<32> src2 = X[xs2][31:0]; + + if (src2 == 0) { + # division by zero. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be the largest 32-bit unsigned value (sign extended to 64-bits) + X[xd] = {64{1'b1}}; + + } else { + + Bits<32> result = src1 / src2; + Bits<1> sign_bit = result[31]; + + X[xd] = {{32{sign_bit}}, result}; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") then { + let rs1_val = X(rs1)[31..0]; + let rs2_val = X(rs2)[31..0]; + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); + let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); + /* check for signed overflow */ + let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q; + X(rd) = sign_extend(to_bits(32, q')); + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/divw.yaml b/pkg/ifuzz/riscv64/gen/inst/M/divw.yaml new file mode 100644 index 000000000000..dd8a57350f31 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/divw.yaml @@ -0,0 +1,85 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: divw +long_name: Signed 32-bit division +description: | + Divide the lower 32-bits of register xs1 by the lower 32-bits of register xs2, + and store the sign-extended result in xd. + + The remainder is discarded. + + Division by zero will put -1 into xd. + + Division resulting in signed overflow (when most negative number is divided by -1) + will put the most negative number into xd; +definedBy: + allOf: + - xlen: 64 + - extension: + name: M +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------100-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + Bits<32> src1 = X[xs1][31:0]; + Bits<32> src2 = X[xs2][31:0]; + + if (src2 == 0) { + # division by zero. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be -1 + X[xd] = {MXLEN{1'b1}}; + + } else if ((src1 == 32'h80000000) && (src2 == 32'hFFFFFFFF)) { + #INT_MIN / -1 = INT_MIN + #signed overflow. Since RISC-V does not have arithmetic exceptions, the result is defined + #to be the most negative number (-2^(31)) + X[xd] = sext(32'h80000000, 32); + + } else { + # no special case, just divide + X[xd] = sext($signed(src1) / $signed(src2), 32); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") then { + let rs1_val = X(rs1)[31..0]; + let rs2_val = X(rs2)[31..0]; + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); + let q : int = if rs2_int == 0 then -1 else quot_round_zero(rs1_int, rs2_int); + /* check for signed overflow */ + let q': int = if s & q > (2 ^ 31 - 1) then (0 - 2^31) else q; + X(rd) = sign_extend(to_bits(32, q')); + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/mul.yaml b/pkg/ifuzz/riscv64/gen/inst/M/mul.yaml new file mode 100644 index 000000000000..99f712bc5d35 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/mul.yaml @@ -0,0 +1,109 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: mul +long_name: Signed multiply +description: | + MUL performs an XLEN-bitxXLEN-bit multiplication of `xs1` by `xs2` and places the lower + XLEN bits in the destination register. + Any overflow is thrown away. + + [NOTE] + If both the high and low bits of the same product are required, then the recommended code + sequence is: + MULH[[S]U] xdh, xs1, xs2; MUL xdl, xs1, xs2 + (source register specifiers must be in same order and xdh cannot be the same as xs1 or xs2). + Microarchitectures can then fuse these into a single multiply operation instead of + performing two separate multiplies. + +definedBy: + extension: + anyOf: + - name: M + - name: Zmmul +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg src1 = X[xs1]; + XReg src2 = X[xs2]; + + X[xd] = (src1 * src2)[MXLEN-1:0]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") | haveZmmul() then { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val); + let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int); + let result = if high + then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)] + else result_wide[(sizeof(xlen) - 1) .. 0]; + X(rd) = result; + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd + +cert_normative_rules: + - id: inst.mul.encoding + name: Encoding + description: Encoding of `mul` instruction + doc_links: + - manual:inst:mul:encoding + - id: inst.mul.basic_op + name: Basic operation + description: Basic operation of `mul` instruction + doc_links: + - manual:inst:mul:operation + - id: inst.mul.ill_exc_misa_M_disabled + name: Illegal instruction exception when misa.M is 0 + description: | + An illegal instruction exception is raised when the instruction is executed + and `misa.M` is 0. + doc_links: + - manual:csr:misa:disabling-extension + +cert_test_procedures: + - id: inst.mul.encoding + description: Verify the encoding of the `mul` instruction + normative_rules: [inst.mul.encoding] + steps: | + . Setup + .. Load a variety of known values into rs1 & rs2 with a variety of rs1/rs2/rd values. + . Execution + .. Execute the `mul` instruction + . Validation + .. Check each result in rd + . Teardown + .. Clear the registers used for rd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/mulh.yaml b/pkg/ifuzz/riscv64/gen/inst/M/mulh.yaml new file mode 100644 index 000000000000..5f2e10f767ba --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/mulh.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: mulh +long_name: Signed multiply high +description: | + Multiply the signed values in xs1 to xs2, and store the upper half of the result in xd. + The lower half is thrown away. + + If both the upper and lower halves are needed, it suggested to use the sequence: + + --- + mulh xdh, xs1, xs2 + mul xdl, xs1, xs2 + --- + + Microarchitectures may look for that sequence and fuse the operations. +definedBy: + extension: + anyOf: + - name: M + - name: Zmmul +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------001-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + # enlarge and sign extend the sources + Bits<1> xs1_sign_bit = X[xs1][xlen()-1]; + Bits src1 = {{xlen(){xs1_sign_bit}}, X[xs1]}; + + Bits<1> xs2_sign_bit = X[xs2][xlen()-1]; + Bits src2 = {{xlen(){xs2_sign_bit}}, X[xs2]}; + + # grab the high half of the result, and put it in xd + X[xd] = (src1 * src2)[(xlen()*8'd2)-1:xlen()]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") | haveZmmul() then { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val); + let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int); + let result = if high + then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)] + else result_wide[(sizeof(xlen) - 1) .. 0]; + X(rd) = result; + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/mulhsu.yaml b/pkg/ifuzz/riscv64/gen/inst/M/mulhsu.yaml new file mode 100644 index 000000000000..96ab151862ed --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/mulhsu.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: mulhsu +long_name: Signed/unsigned multiply high +description: | + Multiply the signed value in xs1 by the unsigned value in xs2, and store the upper half of the result in xd. + The lower half is thrown away. + + If both the upper and lower halves are needed, it suggested to use the sequence: + + --- + mulhsu xdh, xs1, xs2 + mul xdl, xs1, xs2 + --- + + Microarchitectures may look for that sequence and fuse the operations. +definedBy: + extension: + anyOf: + - name: M + - name: Zmmul +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------010-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + # enlarge and extend the sources + Bits<1> xs1_sign_bit = X[xs1][MXLEN-1]; + Bits src1 = {{MXLEN{xs1_sign_bit}}, X[xs1]}; + Bits src2 = {{MXLEN{1'b0}}, X[xs2]}; + + X[xd] = (src1 * src2)[(MXLEN*8'd2)-1:MXLEN]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") | haveZmmul() then { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val); + let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int); + let result = if high + then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)] + else result_wide[(sizeof(xlen) - 1) .. 0]; + X(rd) = result; + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/mulhu.yaml b/pkg/ifuzz/riscv64/gen/inst/M/mulhu.yaml new file mode 100644 index 000000000000..0831e8ec0107 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/mulhu.yaml @@ -0,0 +1,76 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: mulhu +long_name: Unsigned multiply high +description: | + Multiply the unsigned values in xs1 to xs2, and store the upper half of the result in xd. + The lower half is thrown away. + + If both the upper and lower halves are needed, it suggested to use the sequence: + + --- + mulhu xdh, xs1, xs2 + mul xdl, xs1, xs2 + --- + + Microarchitectures may look for that sequence and fuse the operations. +definedBy: + extension: + anyOf: + - name: M + - name: Zmmul +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------011-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + # enlarge and zero-extend the sources + Bits src1 = {{MXLEN{1'b0}}, X[xs1]}; + Bits src2 = {{MXLEN{1'b0}}, X[xs2]}; + + X[xd] = (src1 * src2)[(MXLEN*8'd2)-1:MXLEN]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") | haveZmmul() then { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let rs1_int : int = if signed1 then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if signed2 then signed(rs2_val) else unsigned(rs2_val); + let result_wide = to_bits(2 * sizeof(xlen), rs1_int * rs2_int); + let result = if high + then result_wide[(2 * sizeof(xlen) - 1) .. sizeof(xlen)] + else result_wide[(sizeof(xlen) - 1) .. 0]; + X(rd) = result; + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/mulw.yaml b/pkg/ifuzz/riscv64/gen/inst/M/mulw.yaml new file mode 100644 index 000000000000..745501f2bb70 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/mulw.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: mulw +long_name: Signed 32-bit multiply +description: | + Multiplies the lower 32 bits of the source registers, placing the sign-extension of the + lower 32 bits of the result into the destination register. + + Any overflow is thrown away. + + [NOTE] + In RV64, MUL can be used to obtain the upper 32 bits of the 64-bit product, + but signed arguments must be proper 32-bit signed values, whereas unsigned arguments + must have their upper 32 bits clear. If the arguments are not known to be sign- or zero-extended, + an alternative is to shift both arguments left by 32 bits, then use MULH[[S]U]. +definedBy: + allOf: + - xlen: 64 + - extension: + anyOf: + - name: M + - name: Zmmul +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------000-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + Bits<32> src1 = X[xs1][31:0]; + Bits<32> src2 = X[xs2][31:0]; + + Bits<32> result = src1 * src2; + Bits<1> sign_bit = result[31]; + + # return the sign-extended result + X[xd] = {{32{sign_bit}}, result}; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") | haveZmmul() then { + let rs1_val = X(rs1)[31..0]; + let rs2_val = X(rs2)[31..0]; + let rs1_int : int = signed(rs1_val); + let rs2_int : int = signed(rs2_val); + /* to_bits requires expansion to 64 bits followed by truncation */ + let result32 = to_bits(64, rs1_int * rs2_int)[31..0]; + let result : xlenbits = sign_extend(result32); + X(rd) = result; + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/rem.yaml b/pkg/ifuzz/riscv64/gen/inst/M/rem.yaml new file mode 100644 index 000000000000..fa6c7cd36d90 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/rem.yaml @@ -0,0 +1,76 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: rem +long_name: Signed remainder +description: | + Calculate the remainder of signed division of xs1 by xs2, and store the result in xd. + + If the value in register xs2 is zero, write the value in xs1 into xd; + + If the result of the division overflows, write zero into xd; +definedBy: + extension: + name: M +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------110-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg src1 = X[xs1]; + XReg src2 = X[xs2]; + + if (src2 == 0) { + # division by zero. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be the dividend + X[xd] = src1; + + } else if ((src1 == {1'b1, {MXLEN-1{1'b0}}}) && (src2 == {MXLEN{1'b1}})) { + # signed overflow. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be zero + X[xd] = 0; + + } else { + X[xd] = $signed(src1) % $signed(src2); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") then { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); + let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + X(rd) = to_bits(sizeof(xlen), r); + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/remu.yaml b/pkg/ifuzz/riscv64/gen/inst/M/remu.yaml new file mode 100644 index 000000000000..bc19ffdac914 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/remu.yaml @@ -0,0 +1,66 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: remu +long_name: Unsigned remainder +description: | + Calculate the remainder of unsigned division of xs1 by xs2, and store the result in xd. +definedBy: + extension: + name: M +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------111-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg src1 = X[xs1]; + XReg src2 = X[xs2]; + + if (src2 == 0) { + # division by zero. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be the dividend + X[xd] = src1; + } else { + X[xd] = src1 % src2; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") then { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); + let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + X(rd) = to_bits(sizeof(xlen), r); + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/remuw.yaml b/pkg/ifuzz/riscv64/gen/inst/M/remuw.yaml new file mode 100644 index 000000000000..849a5c57273a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/remuw.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: remuw +long_name: Unsigned 32-bit remainder +description: | + Calculate the remainder of unsigned division of the 32-bit values in xs1 by xs2, + and store the sign-extended result in xd. + + If the value in xs2 is zero, xd gets the sign-extended value in xs1. +definedBy: + allOf: + - xlen: 64 + - extension: + name: M +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------111-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + Bits<32> src1 = X[xs1][31:0]; + Bits<32> src2 = X[xs2][31:0]; + + if (src2 == 0) { + # division by zero. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be the dividend + Bits<1> sign_bit = src1[31]; + X[xd] = {{32{sign_bit}}, src1}; + + } else { + # no special case + + Bits<32> result = src1 % src2; + + Bits<1> sign_bit = result[31]; + + X[xd] = {{32{sign_bit}}, result}; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") then { + let rs1_val = X(rs1)[31..0]; + let rs2_val = X(rs2)[31..0]; + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); + let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + X(rd) = sign_extend(to_bits(32, r)); + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/M/remw.yaml b/pkg/ifuzz/riscv64/gen/inst/M/remw.yaml new file mode 100644 index 000000000000..76e42657da1a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/M/remw.yaml @@ -0,0 +1,84 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: remw +long_name: Signed 32-bit remainder +description: | + Calculate the remainder of signed division of the 32-bit values xs1 by xs2, + and store the sign-extended result in xd. + + If the value in register xs2 is zero, write the sign-extended 32-bit value in xs1 into xd; + + If the result of the division overflows, write zero into xd; +definedBy: + allOf: + - xlen: 64 + - extension: + name: M +assembly: xd, xs1, xs2 +encoding: + match: 0000001----------110-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + Bits<32> src1 = X[xs1][31:0]; + Bits<32> src2 = X[xs2][31:0]; + + if (src2 == 0) { + # division by zero. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be the dividend, sign extended to into the 64-bit register + Bits<1> sign_bit = src1[31]; + X[xd] = {{32{sign_bit}}, src1}; + + } else if ((src1 == 32'h80000000) && (src2 == 32'hFFFFFFFF)) { + # signed overflow. Since RISC-V does not have arithmetic exceptions, the result is defined + # to be zero + X[xd] = 0; + + } else { + # no special case + Bits<32> result = $signed(src1) % $signed(src2); + Bits<1> sign_bit = result[31]; + + X[xd] = {{32{sign_bit}}, result}; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("M") then { + let rs1_val = X(rs1)[31..0]; + let rs2_val = X(rs2)[31..0]; + let rs1_int : int = if s then signed(rs1_val) else unsigned(rs1_val); + let rs2_int : int = if s then signed(rs2_val) else unsigned(rs2_val); + let r : int = if rs2_int == 0 then rs1_int else rem_round_zero(rs1_int, rs2_int); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + X(rd) = sign_extend(to_bits(32, r)); + RETIRE_SUCCESS + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fadd.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fadd.q.yaml new file mode 100644 index 000000000000..4f4a860a500e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fadd.q.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fadd.q +long_name: Floating-point Add Quad-Precision +definedBy: + extension: + name: Q +description: | + `fadd.q` is analogous to `fadd.d` and performs double-precision floating-point addition between + `qs1` and `qs2` and writes the final result to `qd`. +assembly: fd, fs1, fs2, rm +encoding: + match: 0000011------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fclass.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fclass.q.yaml new file mode 100644 index 000000000000..2067046849c2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fclass.q.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fclass.q +long_name: Floating-Point Classify Quad-Precision +description: | + The `fclass.q` instruction examines the value in floating-point register `rs1` and writes to integer + register `rd` a 10-bit mask that indicates the class of the floating-point number. + + The format of the mask is described in table given below. The corresponding bit in `rd` + will be set if the property is true and clear otherwise. All other bits in `rd` are cleared. + + Note that exactly one bit in `rd` will be set. `fclass.q` does not set the floating-point + exception flags. + + .Format of result of `fclass` instruction. + [%autowidth,float="center",align="center",cols="^,<",options="header",] + |=== + |_xd_ bit |Meaning + |0 |_fs1_ is latexmath:[$-\infty$]. + |1 |_fs1_ is a negative normal number. + |2 |_fs1_ is a negative subnormal number. + |3 |_fs1_ is latexmath:[$-0$]. + |4 |_fs1_ is latexmath:[$+0$]. + |5 |_fs1_ is a positive subnormal number. + |6 |_fs1_ is a positive normal number. + |7 |_fs1_ is latexmath:[$+\infty$]. + |8 |_fs1_ is a signaling NaN. + |9 |_fs1_ is a quiet NaN. + |=== + +definedBy: + extension: + name: Q +assembly: xd, fs1 +encoding: + match: 111001100000-----001-----1010011 + variables: + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.d.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.d.q.yaml new file mode 100644 index 000000000000..2f847f26c3ac --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.d.q.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.d.q +long_name: Floating-Point Convert Quad-Precision to Double-Precision +definedBy: + extension: + name: Q +description: | + `fcvt.d.q` converts a quad-precision floating-point number to a double-precision floating-point number. +assembly: fd, fs1, rm +encoding: + match: 010000100011-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.h.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.h.q.yaml new file mode 100644 index 000000000000..d2c9169d3e76 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.h.q.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.h.q +long_name: Floating-point Convert Quad-precision to Half-precision +description: | + `fcvt.h.q` converts a Quad-precision Floating-point number to a Half-precision Floating-point number. +definedBy: + extension: + allOf: + - name: Q + - name: Zfhmin +assembly: fd, fs1, rm +encoding: + match: 010001000011-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.l.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.l.q.yaml new file mode 100644 index 000000000000..bc159e559146 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.l.q.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.l.q +long_name: Floating-Point Convert Quad-Precision to Long +definedBy: + allOf: + - xlen: 64 + - extension: + name: Q +description: | + `fcvt.l.q` converts a quad-precision floating-point number to a signed 64-bit integer. +assembly: xd, fs1, rm +encoding: + match: 110001100010-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.lu.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.lu.q.yaml new file mode 100644 index 000000000000..c79998e0beb1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.lu.q.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.lu.q +long_name: Floating-Point Convert Quad-Precision to Unsigned Long +definedBy: + allOf: + - xlen: 64 + - extension: + name: Q +description: | + `fcvt.lu.q` converts a quad-precision floating-point number to an unsigned 64-bit integer. +assembly: xd, fs1, rm +encoding: + match: 110001100011-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.d.yaml new file mode 100644 index 000000000000..13788fb761dd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.d.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.q.d +long_name: Floating-Point Convert Double-Precision to Quad-Precision +definedBy: + extension: + name: Q +description: | + `fcvt.d.q` converts a double-precision floating-point number to a quad-precision floating-point number. +assembly: fd, fs1, rm +encoding: + match: 010001100001-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.h.yaml new file mode 100644 index 000000000000..af42639a9aaf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.q.h +long_name: Floating-point Convert Half-precision to Quad-precision +description: | + `fcvt.q.h` converts a half-precision floating-point number to a quad-precision floating-point number. +definedBy: + extension: + allOf: + - name: Q + - name: Zfhmin +assembly: fd, fs1, rm +encoding: + match: 010001100010-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.l.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.l.yaml new file mode 100644 index 000000000000..05baa1ffd5da --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.l.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.q.l +long_name: Floating-Point Convert Long to Quad-Precision +definedBy: + allOf: + - xlen: 64 + - extension: + name: Q +description: | + `fcvt.q.l` converts a 64-bit signed integer, into a quad-precision floating-point number. +assembly: fd, xs1, rm +encoding: + match: 110101100010-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.lu.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.lu.yaml new file mode 100644 index 000000000000..a28021477ed9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.lu.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.q.lu +long_name: Floating-Point Convert Unsigned Long to Quad-Precision +definedBy: + allOf: + - xlen: 64 + - extension: + name: Q +description: | + `fcvt.q.lu` converts a 64-bit unsigned integer, into a quad-precision floating-point number. +assembly: fd, xs1, rm +encoding: + match: 110101100011-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.s.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.s.yaml new file mode 100644 index 000000000000..c59585ec9205 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.s.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.q.s +long_name: Floating-Point Convert Single-Precision to Quad-Precision +definedBy: + extension: + name: Q +description: | + `fcvt.q.s` converts a single-precision floating-point number to a quad-precision floating-point number. +assembly: fd, fs1, rm +encoding: + match: 010001100000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.w.yaml new file mode 100644 index 000000000000..e3a57ce2ffd1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.w.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.q.w +long_name: Floating-Point Convert Word to Quad-Precision +definedBy: + extension: + name: Q +description: | + `fcvt.q.w` converts a 32-bit signed integer into a quad-precision floating-point number. +assembly: fd, xs1, rm +encoding: + match: 110101100000-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.wu.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.wu.yaml new file mode 100644 index 000000000000..5866babb9738 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.q.wu.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.q.wu +long_name: Floating-Point Convert Unsigned Word to Quad-Precision +definedBy: + extension: + name: Q +description: | + `fcvt.q.wu` converts a 32-bit unsigned integer into a quad-precision floating-point number. +assembly: fd, xs1, rm +encoding: + match: 110101100001-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.s.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.s.q.yaml new file mode 100644 index 000000000000..df3a3d8260e8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.s.q.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.s.q +long_name: Floating-Point Convert Quad-Precision to Single-Precision +definedBy: + extension: + name: Q +description: | + `fcvt.s.q` converts a quad-precision floating-point number to a single-precision floating-point number. +assembly: fd, fs1, rm +encoding: + match: 010000000011-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.w.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.w.q.yaml new file mode 100644 index 000000000000..c5bb981c3edb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.w.q.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.w.q +long_name: Floating-point Convert Quad-precision to Word +definedBy: + extension: + name: Q +description: | + `fcvt.w.q` converts a quad-precision floating-point number to a 32-bit signed integer. +assembly: xd, fs1, rm +encoding: + match: 110001100000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.wu.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.wu.q.yaml new file mode 100644 index 000000000000..70d4bbab9da2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fcvt.wu.q.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.wu.q +long_name: Floating-Point Convert Unsigned Quad-Precision to Word +definedBy: + extension: + name: Q +description: | + `fcvt.wu.q` converts a quad-precision floating-point number to a 32-bit unsigned integer. +assembly: xd, fs1, rm +encoding: + match: 110001100001-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fdiv.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fdiv.q.yaml new file mode 100644 index 000000000000..e104d770d6df --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fdiv.q.yaml @@ -0,0 +1,40 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fdiv.q +long_name: Floating-Point Divide Quad-Precision +description: | + The `fdiv.q` performs the quad-precision floating-point division of `fs1` by `fs2` and writes + the result to floating-point register `fd`.` + The rounding mode is specified by the value in the floating-point Control and Status register (FCSR) + or by the value in the `rm` field of the instruction. + + The operation is performed according to the IEEE 754-2008 standard for quad-precision floating-point arithmetic. + + The instruction sets the floating-point exception flags according to the result of the operation. +definedBy: + extension: + name: Q +assembly: fd, fs1, fs2, rm +encoding: + match: 0001111------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/feq.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/feq.q.yaml new file mode 100644 index 000000000000..b71cf864f463 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/feq.q.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: feq.q +long_name: Floating-Point Equal Quad-Precision +description: | + The `feq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`, + and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise. + + `feq.q` performs a quiet comparison: + it only sets the invalid operation exception flag if either input is a signaling _NaN_. + The result is 0 if either operand is _NaN_. + +definedBy: + extension: + name: Q +assembly: xd, fs1, fs2 +encoding: + match: 1010011----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fle.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fle.q.yaml new file mode 100644 index 000000000000..6cda57ef6b72 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fle.q.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fle.q +long_name: Floating-Point Less Than or Equal Quad-Precision +description: | + The `fle.q` performs the specified comparison between floating-point registers `fs1` and `fs2`, + and writes 1 to integer register `xd` if the condition holds, and 0 otherwise. + + `fle.q` performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is, + they set the invalid operation exception flag if either input is _NaN_. + The result is 0 if either operand is _NaN_. + +definedBy: + extension: + name: Q +assembly: xd, fs1, fs2 +encoding: + match: 1010011----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fleq.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fleq.q.yaml new file mode 100644 index 000000000000..62de7b8d0130 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fleq.q.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fleq.q +long_name: Floating-Point Less Than or Equal Quiet Quad-Precision +description: | + The `fleq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`, + and writes 1 to integer register `xd` if the condition holds, and 0 otherwise. + + `fleq.q` is defined like `fle.q`, except that quiet _NaN_ inputs do not cause the invalid + operation exception flag to be set. + This instruction is encoded like its `flt` counterpart, but with instruction bit 14 set to 1. +definedBy: + extension: + allOf: + - name: Q + - name: Zfa +assembly: xd, fs1, fs2 +encoding: + match: 1010011----------100-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fli.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fli.q.yaml new file mode 100644 index 000000000000..da4bb65d77bf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fli.q.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fli.q +long_name: Floating-Point Load Immediate Quad-Precision +description: | + The `fli.q` instruction loads one of 32 quad-precision floating-point constants, encoded in the `xs1` + field, into floating-point register `rd`. + `fli.q` is encoded like `fmv.w.x`, but with _fmt_ = Q. +definedBy: + extension: + allOf: + - name: Q + - name: Zfa +assembly: fd, xs1 +encoding: + match: 111101100001-----000-----1010011 + variables: + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/flq.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/flq.yaml new file mode 100644 index 000000000000..f3cc587241c6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/flq.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: flq +long_name: Floating-Point Load Quad-Precision +description: | + The `flq` is the new variant of LOAD-FP, encoded with a new value for the `funct3`. + + `flq` is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128. + + `flq` does not modify the bits being transferred; in particular, the payloads of non-canonical + _NaNs_ are preserved. + +definedBy: + extension: + name: Q +assembly: fd, xs1, imm +encoding: + match: "-----------------100-----0000111" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/flt.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/flt.q.yaml new file mode 100644 index 000000000000..7f8db7944fe2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/flt.q.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: flt.q +long_name: Floating-Point Less Than Quad-Precision +description: | + The `flt.q` performs the specified comparison between floating-point registers `fs1` and `fs2`, + and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise. + + + `flt.q` performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is, + they set the invalid operation exception flag if either input is _NaN_. + The result is 0 if either operand is _NaN_. + +definedBy: + extension: + name: Q +assembly: xd, fs1, fs2 +encoding: + match: 1010011----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fltq.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fltq.q.yaml new file mode 100644 index 000000000000..50cec0030c9f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fltq.q.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fltq.q +long_name: Floating-Point Less Than Quiet Quad-Precision +description: | + The `fltq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`, + and writes 1 to integer register `xd` if the condition holds, and 0 otherwise. + + `fltq.q` is defined like `flt.q`, except that quiet _NaN_ inputs do not cause the invalid + operation exception flag to be set. + This instruction is encoded like its `fle` counterpart, but with instruction bit 14 set to 1. +definedBy: + extension: + allOf: + - name: Q + - name: Zfa +assembly: fd, fs1, fs2 +encoding: + match: 1010011----------101-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fmadd.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fmadd.q.yaml new file mode 100644 index 000000000000..2294e49f9a98 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fmadd.q.yaml @@ -0,0 +1,40 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmadd.q +long_name: Floating-Point Multiply-Add Quad-Precision +description: | + The `fmadd.q` instruction performs a floating-point multiply-add operation on the values in registers `fs1`, `fs2`, and `fs3`. + It computes the result as `(fs1 * fs2) + fs3` and writes the result to the destination register `fd`. + + The fused multiply-add instructions must set the invalid operation exception flag when the + multiplicands are latexmath:[$\infty$] and zero, even when the addend is a quiet _NaN_. + +definedBy: + extension: + name: Q +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----11------------------1000011" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fmax.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fmax.q.yaml new file mode 100644 index 000000000000..b4881733b711 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fmax.q.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmax.q +long_name: Floating-Point Maximum-Number Quad-Precision +definedBy: + extension: + name: Q +description: | + The `fmax.q` instruction writes the larger/maximum of `fs1` and `fs2` to `fd`. + The value `-0.0` is considered to be less than the value `+0.0`. + If both inputs are _NaN_s, the result is the canonical _NaN_. + If only one operand is a _NaN_, the result is the non-_NaN_ operand. + Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_. +assembly: fd, fs1, fs2 +encoding: + match: 0010111----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fmaxm.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fmaxm.q.yaml new file mode 100644 index 000000000000..37e816cdf563 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fmaxm.q.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmaxm.q +long_name: Floating-Point Maximum-Number NaN Quad-Precision +description: | + The `fmaxm.q` instruction, defined like `fmax.q`, writes the larger/maximum of `fs1` and `fs2` to `fd`. + The value `-0.0` is considered to be less than the value `+0.0`. + If both inputs are _NaN_s, the result is the canonical _NaN_. + If either input is _NaN_, the result is the canonical _NaN_. + Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_. + This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1. +definedBy: + extension: + allOf: + - name: Q + - name: Zfa +assembly: fd, fs1, fs2 +encoding: + match: 0010111----------011-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fmin.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fmin.q.yaml new file mode 100644 index 000000000000..9d33376d8ab7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fmin.q.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmin.q +long_name: Floating-Point Minimum-Number Quad-Precision +definedBy: + extension: + name: Q +description: | + The `fmin.q` instruction writes the smaller/minimum of `fs1` and `fs2` to `fd`. + The value `-0.0` is considered to be less than the value `+0.0`. + If both inputs are _NaN_s, the result is the canonical _NaN_. + If only one operand is a _NaN_, the result is the non-_NaN_ operand. + Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_. +assembly: fd, fs1, fs2 +encoding: + match: 0010111----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fminm.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fminm.q.yaml new file mode 100644 index 000000000000..8c27725b5a07 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fminm.q.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fminm.q +long_name: Floating-Point Minimum-Number NaN Quad-Precision +description: | + The `fminm.q` instruction, defined like `fmin.q`, writes the smaller/minimum of `fs1` and `fs2` to `fd`. + The value `-0.0` is considered to be less than the value `+0.0`. + If both inputs are _NaN_s, the result is the canonical _NaN_. + If either input is _NaN_, the result is the canonical _NaN_. + Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_. + This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1. +definedBy: + extension: + allOf: + - name: Q + - name: Zfa +assembly: fd, fs1, fs2 +encoding: + match: 0010111----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fmsub.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fmsub.q.yaml new file mode 100644 index 000000000000..b797207d2a1f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fmsub.q.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmsub.q +long_name: Floating-Point Multiply-Subtract Quad-Precision +definedBy: + extension: + name: Q +description: | + The `fmsub.q` instruction performs a floating-point multiply-subtract operation on the values in registers `fs1`, `fs2`, and `fs3`. + It computes the result as `(fs1 * fs2) - fs3` and writes the result to the destination register `fd`. +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----11------------------1000111" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fmul.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fmul.q.yaml new file mode 100644 index 000000000000..30a39ae62cc9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fmul.q.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmul.q +long_name: Floating-point Multiply Quad-Precision +definedBy: + extension: + name: Q +description: | + `fmul.q` performs quad-precision floating-point multiplication, between `fs1` and `fs2`. +assembly: fd, fs1, fs2, rm +encoding: + match: 0001011------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fmvh.x.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fmvh.x.q.yaml new file mode 100644 index 000000000000..b53144ddab25 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fmvh.x.q.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmvh.x.q +long_name: Floating-Point Move High Half to Integer from Quad-Precision +description: | + The `fmvh.x.q` instruction moves bits `127:64` of floating-point register `fs1` into integer register `xd`. + It is encoded in the OP-FP major opcode with _funct3_=0, _rs2_=1, and _funct7_=1110011. + + `fmvh.x.q` is used in conjunction with the existing `fmv.x.d` instruction to move a quad-precision floating-point + number to a pair of x-registers. +definedBy: + allOf: + - xlen: 64 + - extension: + allOf: + - name: Q + - name: Zfa +assembly: xd, fs1 +encoding: + match: 111001100001-----000-----1010011 + variables: + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fmvp.q.x.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fmvp.q.x.yaml new file mode 100644 index 000000000000..0a0cecf0a7af --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fmvp.q.x.yaml @@ -0,0 +1,39 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmvp.q.x +long_name: Floating-Point Move Pair from Integer Registers to Quad-Precision Register +description: | + The `fmvp.q.x` instruction moves a double-precision number from a pair of integer registers into + a floating-point register. + Integer registers `xs1` and `xs2` supply bits 63:0 and 127:64, respectively; the result is written to + floating-point register `fd`. + `fmvp.q.x` is encoded in the OP-FP major opcode with _funct3_=0 and _funct7_=1011011. +definedBy: + allOf: + - xlen: 64 + - extension: + allOf: + - name: Q + - name: Zfa +assembly: fd, xs1, xs2 +encoding: + match: 1011011----------000-----1010011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fnmadd.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fnmadd.q.yaml new file mode 100644 index 000000000000..102ec9c49441 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fnmadd.q.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fnmadd.q +long_name: Floating-Point Negate-Multiply-Add Quad-Precision +definedBy: + extension: + name: Q +description: | + The `fnmadd.q` instruction multiplies the values in `fs1` and `fs2`, negates the product, adds the + value in `fs3`, and writes the final result to `fd`. + `fnmadd.q` computes `-(fs1 * fs2) + fs3`. +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----11------------------1001111" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fnmsub.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fnmsub.q.yaml new file mode 100644 index 000000000000..65cad9405192 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fnmsub.q.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fnmsub.q +long_name: Floating-Point Negate-Multiply-Subtract Quad-Precision +definedBy: + extension: + name: Q +description: | + The `fnmsub.q` instruction multiplies the values in `fs1` and `fs2`, negates the product, subtracts the + value in `fs3`, and writes the final result to `fd`. + `fnmsub.q` computes `-(fs1 * fs2) - fs3`. +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----11------------------1001011" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fround.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fround.q.yaml new file mode 100644 index 000000000000..82235d652866 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fround.q.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fround.q +long_name: Floating-Point Round Quad-Precision +description: | + The `fround.q` instruction rounds the quad-precision floating-point number in floating-point register + `fs1` to an integer, according to the rounding mode specified in the instruction's `rm` field. It then writes + that integer, represented as a quad-precision floating-point number, to floating-point register `fd`. Zero + and infinite inputs are copied to `fd` unmodified. Signaling _NaN_ inputs cause the invalid operation + exception flag to be set; no other exception flags are set. `fround.q` is encoded like `fcvt.q.s`, but with + `rs2`=4. +definedBy: + extension: + allOf: + - name: Q + - name: Zfa +assembly: fd, fs1, rm +encoding: + match: 010001100100-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/froundnx.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/froundnx.q.yaml new file mode 100644 index 000000000000..2a09834513bc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/froundnx.q.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: froundnx.q +long_name: Floating-Point Round-to-Integer Inexact Quad-Precision +description: | + The `froundnx.q` instruction is encoded like `fround.q` but with `rs2`=5 and it also sets the + inexact exception flag if the input differs from the rounded result and is not _NaN_. +definedBy: + extension: + allOf: + - name: Q + - name: Zfa +assembly: fd, fs1, rm +encoding: + match: 010001100101-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fsgnj.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fsgnj.q.yaml new file mode 100644 index 000000000000..f8a1f375905b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fsgnj.q.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsgnj.q +long_name: Floating-Point Sign-Inject Quad-Precision +definedBy: + extension: + name: Q +description: | + The `fsgnj.q` instruction produces a result that takes all bits except the sign bit from `fs1`. + The result's sign bit is taken from `fs2`'s sign bit, and the result is written to the destination register `fd`. + `fsgnj.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s. +assembly: fd, fs1, fs2 +encoding: + match: 0010011----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +pseudoinstructions: + - when: (rs2 == rs1) + to: fmv.q +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fsgnjn.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fsgnjn.q.yaml new file mode 100644 index 000000000000..cc11a5108327 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fsgnjn.q.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsgnjn.q +long_name: Floating-Point Sign-Inject Negate Quad-Precision +definedBy: + extension: + name: Q +description: | + The `fsgnjn.q` instruction produces a result that takes all bits except the sign bit from `fs1`. + The result's sign bit is opposite of `fs2`'s sign bit, and the result is written to the destination register `fd`. + `fsgnjn.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s. +assembly: fd, fs1, fs2 +encoding: + match: 0010011----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +pseudoinstructions: + - when: (fs2 == fs1) + to: fneg.q fd, fs1 +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fsgnjx.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fsgnjx.q.yaml new file mode 100644 index 000000000000..b992a2863588 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fsgnjx.q.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsgnjx.q +long_name: Floating-Point Sign-Inject XOR Quad-Precision +definedBy: + extension: + name: Q +description: | + The `fsgnjx.q` instruction produces a result that takes all bits except the sign bit from `fs1`. + The result's sign bit is the XOR of sign bits of `fs1` and `fs2`, and the result is written to the destination register `fd`. + `fsgnjx.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s. +assembly: fd, fs1, fs2 +encoding: + match: 0010011----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +pseudoinstructions: + - when: (fs2 == fs1) + to: fabs.q fd, fs1 +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fsq.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fsq.yaml new file mode 100644 index 000000000000..d64c278c01cd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fsq.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsq +long_name: Floating-Point Store Quad-Precision +description: | + The `fsq` is the new variant of LOAD-FP, encoded with a new value for the `funct3`. + + `fsq` is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128. + + `fsq` does not modify the bits being transferred; in particular, the payloads of non-canonical + _NaNs_ are preserved. +definedBy: + extension: + name: Q +assembly: fs2, imm(xs1) +encoding: + match: "-----------------100-----0100111" + variables: + - name: imm + location: 31-25|11-7 + - name: fs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fsqrt.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fsqrt.q.yaml new file mode 100644 index 000000000000..ff6e91e0f189 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fsqrt.q.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsqrt.q +long_name: Floating-Point Square Root Quad-Precision +definedBy: + extension: + name: Q +description: | + The `fsqrt.q` instruction computes the square root of the value in `fs1` and writes the result to `fd`. +assembly: fd, fs1, rm +encoding: + match: 010111100000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Q/fsub.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Q/fsub.q.yaml new file mode 100644 index 000000000000..4d12fcf71150 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Q/fsub.q.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsub.q +long_name: Floating-Point Subtract Quad-Precision +definedBy: + extension: + name: Q +description: | + The `fsub.q` instruction performs the quad-precision floating-point subtraction of `fs2` from `fs1`. + It computes the result as `fs1 - fs2` and writes the result to the destination register `fd`. +assembly: fd, fs1, fs2, rm +encoding: + match: 0000111------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/S/sfence.vma.yaml b/pkg/ifuzz/riscv64/gen/inst/S/sfence.vma.yaml new file mode 100644 index 000000000000..23805b6f5ef7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/S/sfence.vma.yaml @@ -0,0 +1,331 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sfence.vma +long_name: Supervisor memory-management fence +definedBy: + extension: + name: S +description: | + The supervisor memory-management fence instruction `SFENCE.VMA` is used to + synchronize updates to in-memory memory-management data structures with + current execution. Instruction execution causes implicit reads and + writes to these data structures; however, these implicit references are + ordinarily not ordered with respect to explicit loads and stores. + Executing an SFENCE.VMA instruction guarantees that any previous stores + already visible to the current RISC-V hart are ordered before certain + implicit references by subsequent instructions in that hart to the + memory-management data structures. The specific set of operations + ordered by SFENCE.VMA is determined by _xs1_ and _xs2_, as described + below. SFENCE.VMA is also used to invalidate entries in the + address-translation cache associated with a hart (see <>). Further details on the behavior of this instruction are described in <> and <>. + + [NOTE] + ==== + The SFENCE.VMA is used to flush any local hardware caches related to + address translation. It is specified as a fence rather than a TLB flush + to provide cleaner semantics with respect to which instructions are + affected by the flush operation and to support a wider variety of + dynamic caching structures and memory-management schemes. SFENCE.VMA is + also used by higher privilege levels to synchronize page table writes + and the address translation hardware. + ==== + + SFENCE.VMA orders only the local hart's implicit references to the + memory-management data structures. + + [NOTE] + ==== + Consequently, other harts must be notified separately when the + memory-management data structures have been modified. One approach is to + use 1) a local data fence to ensure local writes are visible globally, + then 2) an interprocessor interrupt to the other thread, then 3) a local + SFENCE.VMA in the interrupt handler of the remote thread, and finally 4) + signal back to originating thread that operation is complete. This is, + of course, the RISC-V analog to a TLB shootdown. + ==== + + For the common case that the translation data structures have only been + modified for a single address mapping (i.e., one page or superpage), + _xs1_ can specify a virtual address within that mapping to effect a + translation fence for that mapping only. Furthermore, for the common + case that the translation data structures have only been modified for a + single address-space identifier, _xs2_ can specify the address space. + The behavior of SFENCE.VMA depends on _xs1_ and _xs2_ as follows: + + * If __xs1__=`x0` and __xs2__=`x0`, the fence orders all reads and writes + made to any level of the page tables, for all address spaces. The fence + also invalidates all address-translation cache entries, for all address + spaces. + * If __xs1__=`x0` and __xs2__≠``x0``, the fence orders all + reads and writes made to any level of the page tables, but only for the + address space identified by integer register _xs2_. Accesses to _global_ + mappings (see <>) are not ordered. The + fence also invalidates all address-translation cache entries matching + the address space identified by integer register _xs2_, except for + entries containing global mappings. + * If __xs1__≠``x0`` and __xs2__=`x0`, the fence orders only + reads and writes made to leaf page table entries corresponding to the + virtual address in __xs1__, for all address spaces. The fence also + invalidates all address-translation cache entries that contain leaf page + table entries corresponding to the virtual address in _xs1_, for all + address spaces. + * If __xs1__≠``x0`` and __xs2__≠``x0``, the + fence orders only reads and writes made to leaf page table entries + corresponding to the virtual address in _xs1_, for the address space + identified by integer register _xs2_. Accesses to global mappings are + not ordered. The fence also invalidates all address-translation cache + entries that contain leaf page table entries corresponding to the + virtual address in _xs1_ and that match the address space identified by + integer register _xs2_, except for entries containing global mappings. + + If the value held in _xs1_ is not a valid virtual address, then the + SFENCE.VMA instruction has no effect. No exception is raised in this + case. + + When __xs2__≠``x0``, bits SXLEN-1:ASIDMAX of the value held + in _xs2_ are reserved for future standard use. Until their use is + defined by a standard extension, they should be zeroed by software and + ignored by current implementations. Furthermore, if + ASIDLEN asid = X[xs2][ASID_WIDTH-1:0]; + + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (CSR[misa].H == 1 && mode() == PrivilegeMode::VU) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (CSR[mstatus].TVM == 1 && + ((mode() == PrivilegeMode::S) || (mode() == PrivilegeMode::VS))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (CSR[misa].H == 1 && CSR[hstatus].VTVM == 1 && mode() == PrivilegeMode::VS) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + + if (!implemented?(ExtensionName::Sv32) && !implemented?(ExtensionName::Sv39) && !implemented?(ExtensionName::Sv48) && !implemented?(ExtensionName::Sv57)) { + if (TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + } + + # note: this will default to "all", without globals included + VmaOrderType vma_type; + if (CSR[misa].H == 1 && mode() == PrivilegeMode::VS) { + vma_type.vsmode = true; + vma_type.single_vmid = true; + vma_type.vmid = CSR[hgatp].VMID; + } else { + vma_type.smode = true; + } + + if ((xs1 == 0) && (xs2 == 0)) { + # invalidate all translations, from all addresses and all ASIDs + # includes global mappings + vma_type.global = true; + + order_pgtbl_writes_before_vmafence(vma_type); + invalidate_translations(vma_type); + order_pgtbl_reads_after_vmafence(vma_type); + + } else if ((xs1 == 0) && (xs2 != 0)) { + # invalidates all translations from ASID 'asid' + # does not affect global mappings + vma_type.single_asid = true; + vma_type.asid = asid; + + order_pgtbl_writes_before_vmafence(vma_type); + invalidate_translations(vma_type); + order_pgtbl_reads_after_vmafence(vma_type); + + } else if ((xs1 != 0) && (xs2 == 0)) { + # invalidate all translations from leaf page tables containing 'vaddr' + # does not affect global mappings + if (canonical_vaddr?(vaddr)) { + vma_type.single_vaddr = true; + vma_type.vaddr = vaddr; + + order_pgtbl_writes_before_vmafence(vma_type); + invalidate_translations(vma_type); + order_pgtbl_reads_after_vmafence(vma_type); + } + # else, silently do nothing + + } else { + # invalidate all translations from leaf page tables for address space 'asid' containing 'vaddr' + # does not affect global mappings + if (canonical_vaddr?(vaddr)) { + vma_type.single_asid = true; + vma_type.asid = asid; + vma_type.single_vaddr = true; + vma_type.vaddr = vaddr; + + order_pgtbl_writes_before_vmafence(vma_type); + invalidate_translations(vma_type); + order_pgtbl_reads_after_vmafence(vma_type); + } + # else, silently do nothing + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let addr : option(xlenbits) = if rs1 == 0b00000 then None() else Some(X(rs1)); + let asid : option(xlenbits) = if rs2 == 0b00000 then None() else Some(X(rs2)); + match cur_privilege { + User => { handle_illegal(); RETIRE_FAIL }, + Supervisor => match (architecture(get_mstatus_SXL(mstatus)), mstatus.TVM()) { + (Some(_), 0b1) => { handle_illegal(); RETIRE_FAIL }, + (Some(_), 0b0) => { flush_TLB(asid, addr); RETIRE_SUCCESS }, + (_, _) => internal_error(__FILE__, __LINE__, "unimplemented sfence architecture") + }, + Machine => { flush_TLB(asid, addr); RETIRE_SUCCESS } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/S/sret.yaml b/pkg/ifuzz/riscv64/gen/inst/S/sret.yaml new file mode 100644 index 000000000000..9bd840655d69 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/S/sret.yaml @@ -0,0 +1,166 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sret +long_name: Supervisor Mode Return from Trap +description: | + Returns from supervisor mode after handling a trap. + + When `sret` is allowed to execute, its behavior depends on whether or not the current privilege + mode is virtualized. + + *When the current privilege mode is (H)S-mode or M-mode* + + `sret` sets `hstatus.HPV` = 0, `mstatus.SPP` = 0, + `mstatus.SIE` = `mstatus.SPIE`, and `mstatus.SPIE` = 1, + changes the privilege mode according to the table below, + and then jumps to the address in `sepc`. + + .Next privilege mode following an `sret` in (H)S-mode or M-mode + [%autowidth] + |=== + | [.rotate]#`mstatus.SPP`# | [.rotate]#`hstatus.SPV`# .>| Mode after `sret` + + | 0 | 0 | U-mode + | 0 | 1 | VU-mode + | 1 | 0 | (H)S-mode + | 1 | 1 | VS-mode + |=== + + *When the current privilege mode is VS-mode* + + `sret` sets + `vsstatus.SPP` = 0, `vsstatus.SIE` = `vstatus.SPIE`, and `vsstatus.SPIE` = 1, + changes the privilege mode according to the table below, + and then jumps to the address in `vsepc`. + + .Next privilege mode following an `sret` in (H)S-mode or M-mode + [%autowidth] + |=== + | [.rotate]#`vsstatus.SPP`# .>| Mode after `sret` + + | 0 | VU-mode + | 1 | VS-mode + |=== + +definedBy: + extension: + name: S +assembly: "" +encoding: + match: "00010000001000000000000001110011" +access: + s: sometimes + u: never + vs: sometimes + vu: never +access_detail: | + Access is determined as follows: + + [%autowidth] + |=== + .2+| [.rotate]#`mstatus.TSR`# .2+| [.rotate]#`hstatus.VTSR`# 5+^.>| Behavior when executed from: + h| M-mode h| U-mode h| (H)S-mode h| VU-mode h| VS-mode + + | 0 | 0 | executes | `Illegal Instruction` | executes | `Virtual Instruction` | executes + | 0 | 1 | executes | `Illegal Instruction` | executes | `Virtual Instruction` | `Virtual Instruction` + | 1 | 0 | executes | `Illegal Instruction` | `Illegal Instruction` | `Virtual Instruction` | executes + | 1 | 1 | executes | `Illegal Instruction` | `Illegal Instruction` | `Virtual Instruction` | `Virtual Instruction` + |=== +operation(): | + # first, check access requirements + if (implemented?(ExtensionName::H)) { + if (CSR[mstatus].TSR == 1'b0 && CSR[hstatus].VTSR == 1'b0) { + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (mode() == PrivilegeMode::VU) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + } else if (CSR[mstatus].TSR == 1'b0 && CSR[hstatus].VTSR == 1'b1) { + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (mode() == PrivilegeMode::VU || mode() == PrivilegeMode::VS) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + } else if (CSR[mstatus].TSR == 1'b1 && CSR[hstatus].VTSR == 1'b0) { + if (mode() == PrivilegeMode::U || mode() == PrivilegeMode::S) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (mode() == PrivilegeMode::VU) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + } else if (CSR[mstatus].TSR == 1'b1 && CSR[hstatus].VTSR == 1'b1) { + if (mode() == PrivilegeMode::U || mode() == PrivilegeMode::S) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (mode() == PrivilegeMode::VU || mode() == PrivilegeMode::VS) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + } + } else { + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + } + + # now pop the interrupt stack and change modes + if (!virtual_mode?()) { + if (implemented?(ExtensionName::H)) { + if (CSR[hstatus].SPV == 1'b1) { + if (CSR[mstatus].SPP == 1'b1) { + set_mode(PrivilegeMode::VS); + } else { + set_mode(PrivilegeMode::VU); + } + } else { + if (CSR[mstatus].SPP == 1'b1) { + set_mode(PrivilegeMode::S); + } else { + set_mode(PrivilegeMode::U); + } + } + CSR[hstatus].SPV = 0; + } else { + if (CSR[mstatus].SPP == 1'b1) { + set_mode(PrivilegeMode::S); + } else { + set_mode(PrivilegeMode::U); + } + } + CSR[mstatus].SIE = CSR[mstatus].SPIE; + CSR[mstatus].SPIE = 1; + CSR[mstatus].SPP = 2'b00; + $pc = $bits(CSR[sepc]); + } else { + if (CSR[mstatus].TSR == 1'b1) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + CSR[vsstatus].SPP = 0; + CSR[vsstatus].SIE = CSR[vsstatus].SPIE; + CSR[vsstatus].SPIE = 1; + $pc = $bits(CSR[vsepc]); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let sret_illegal : bool = match cur_privilege { + User => true, + Supervisor => not(haveSupMode ()) | mstatus.TSR() == 0b1, + Machine => not(haveSupMode ()) + }; + if sret_illegal + then { handle_illegal(); RETIRE_FAIL } + else if not(ext_check_xret_priv (Supervisor)) + then { ext_fail_xret_priv(); RETIRE_FAIL } + else { + set_next_pc(exception_handler(cur_privilege, CTL_SRET(), PC)); + RETIRE_SUCCESS + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Sdext/dret.yaml b/pkg/ifuzz/riscv64/gen/inst/Sdext/dret.yaml new file mode 100644 index 000000000000..87c25ab72e1c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Sdext/dret.yaml @@ -0,0 +1,25 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: dret +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Sdext +assembly: "" +encoding: + match: "01111011001000000000000001110011" + variables: [] +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Smdbltrp/sctrclr.yaml b/pkg/ifuzz/riscv64/gen/inst/Smdbltrp/sctrclr.yaml new file mode 100644 index 000000000000..0ae7c85f7785 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Smdbltrp/sctrclr.yaml @@ -0,0 +1,47 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: sctrclr +long_name: Supervisor Control Transfer Record (CTR) clear +description: | + When `mstateen0.CTR`=1, the SCTRCLR instruction performs the following operations: + + * Zeroes all CTR Entry Registers, for all DEPTH values + * Reset to Zero the optional CTR cycle counter where implemented + ** `ctrdata.CC` and `ctrdata.CCV` bit fields. + + Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next + qualified control transfer, will return the value 0. + + Further, the first recorded transfer following SCTRCLR will have `ctrdata.CCV`=0. + + SCTRCLR execution causes an `IllegalInstruction` exception if: + + * `Smctr` is not implemented + * The instruction is executed in S/VS/VU-mode and `Ssctr` is not implemented, or `mstateen0.CTR`=0 + * The instruction is executed in U-mode + + SCTRCLR execution causes a `VirtualInstruciton` exception if `mstateen0.CTR`=1 and: + + * The instruction is executed in VS-mode and `hstateen0.CTR`=0 + * The instruction is executed in VU-mode +definedBy: + extension: + anyOf: + - name: Smctr + - name: Ssctr +assembly: "" +encoding: + match: "00010000010000000000000001110011" + variables: [] +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Smrnmi/mnret.yaml b/pkg/ifuzz/riscv64/gen/inst/Smrnmi/mnret.yaml new file mode 100644 index 000000000000..2866c51f31db --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Smrnmi/mnret.yaml @@ -0,0 +1,49 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: mnret +long_name: Machine mode resume from the RNMI or Double Trap handler +description: | + MNRET is an M-mode-only instruction that uses the values in mnepc and mnstatus to return to the + program counter, privilege mode, and virtualization mode of the interrupted context. This instruction + also sets mnstatus.NMIE. If MNRET changes the privilege mode to a mode less privileged than M, it + also sets mstatus.MPRV to 0. If the Zicfilp extension is implemented, then if the new privileged mode is + y, MNRET sets ELP to the logical AND of yLPE (see Section 22.1.1) and mnstatus.MNPELP. +definedBy: + extension: + name: Smrnmi +assembly: "" +encoding: + match: "01110000001000000000000001110011" + variables: [] +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + if (CSR[mnstatus].MNPP != 2'b11) { + CSR[mstatus].MPRV = 0; + if (implemented?(ExtensionName::Smdbltrp)) { + if (xlen() == 64) { + CSR[mstatus].MDT = 1'b0; + } else { + CSR[mstatush].MDT = 1'b0; + } + } + } + CSR[mnstatus].NMIE = 1'b1; + if (CSR[mnstatus].MNPP == 2'b00) { + set_mode(PrivilegeMode::U); + } else if (CSR[mnstatus].MNPP == 2'b01) { + set_mode(PrivilegeMode::S); + } else if (CSR[mnstatus].MNPP == 2'b11) { + set_mode(PrivilegeMode::M); + } + CSR[mnstatus].MNPP = implemented?(ExtensionName::U) ? 2'b00 : 2'b11; + $pc = $bits(CSR[mnepc]); diff --git a/pkg/ifuzz/riscv64/gen/inst/Svinval/hinval.gvma.yaml b/pkg/ifuzz/riscv64/gen/inst/Svinval/hinval.gvma.yaml new file mode 100644 index 000000000000..6cbc765a5b00 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Svinval/hinval.gvma.yaml @@ -0,0 +1,91 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: hinval.gvma +long_name: Invalidate cached address translations +definedBy: + extension: + allOf: + - name: Svinval + - name: H +encoding: + match: 0110011----------000000001110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +description: | + `hinval.gvma` has the same semantics as `sinval.vma` except that it combines with + `sfence.w.inval` and `sfence.inval.ir` to replace `hfence.gvma` and uses VMID instead of ASID. +access: + s: sometimes + u: never + vs: never + vu: never +assembly: xs1, xs2 +operation(): | + XReg gpa = X[xs1]; + Bits vmid = X[xs2][VMID_WIDTH-1:0]; + + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (CSR[mstatus].TVM == 1 && mode() == PrivilegeMode::S) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if ((mode() == PrivilegeMode::VS) || (mode() == PrivilegeMode::VU)) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + + # note: this will default to "all" + VmaOrderType vma_type; + vma_type.gstage = true; + + if ((xs1 == 0) && (xs2 == 0)) { + # invalidate all G-stage translations, from all addresses and all VMIDs + # includes global mappings + vma_type.global = true; + + invalidate_translations(vma_type); + + } else if ((xs1 == 0) && (xs2 != 0)) { + # invalidates all G-stage translations from VMID 'vmid' + # does not affect global mappings + vma_type.single_vmid = true; + vma_type.vmid = vmid; + + invalidate_translations(vma_type); + + } else if ((xs1 != 0) && (xs2 == 0)) { + # invalidate all G-stage translations from leaf page tables containing 'vaddr' + # does not affect global mappings + if (canonical_gpaddr?(gpa)) { + vma_type.single_gpaddr = true; + vma_type.gpaddr = gpa; + + invalidate_translations(vma_type); + + } + # else, silently do nothing + + } else { + # invalidate all G-stage translations from leaf page tables for virtual machine 'vmid' containing 'vaddr' + # does not affect global mappings + if (canonical_gpaddr?(gpa)) { + vma_type.single_vmid = true; + vma_type.vmid = vmid; + vma_type.single_gpaddr = true; + vma_type.gpaddr = gpa; + + invalidate_translations(vma_type); + + } + # else, silently do nothing + } diff --git a/pkg/ifuzz/riscv64/gen/inst/Svinval/hinval.vvma.yaml b/pkg/ifuzz/riscv64/gen/inst/Svinval/hinval.vvma.yaml new file mode 100644 index 000000000000..0291ee1165c4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Svinval/hinval.vvma.yaml @@ -0,0 +1,91 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: hinval.vvma +long_name: Invalidate cached address translations +definedBy: + extension: + allOf: + - name: Svinval + - name: H +encoding: + match: 0010011----------000000001110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +description: | + `hinval.vvma` has the same semantics as `sinval.vma` except that it combines with + `sfence.w.inval` and `sfence.inval.ir` to replace `hfence.vvma`. +access: + s: always + u: never + vs: never + vu: never +assembly: xs1, xs2 +operation(): | + XReg vaddr = X[xs1]; + Bits asid = X[xs2][ASID_WIDTH-1:0]; + Bits vmid = CSR[hgatp].VMID; + + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if ((CSR[misa].H == 1) && + (mode() == PrivilegeMode::VS || mode() == PrivilegeMode::VU)) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + + # note: this will default to "all" + VmaOrderType vma_type; + vma_type.vsmode = true; + vma_type.single_vmid = true; + vma_type.vmid = vmid; + + if ((xs1 == 0) && (xs2 == 0)) { + # invalidate all translations, from all addresses and all ASIDs + # includes global mappings + vma_type.global = true; + + invalidate_translations(vma_type); + + } else if ((xs1 == 0) && (xs2 != 0)) { + # invalidates all translations from ASID 'asid' + # does not affect global mappings + vma_type.single_asid = true; + vma_type.asid = asid; + + invalidate_translations(vma_type); + + } else if ((xs1 != 0) && (xs2 == 0)) { + # invalidate all translations from leaf page tables containing 'vaddr' + # does not affect global mappings + if (canonical_vaddr?(vaddr)) { + vma_type.single_vaddr = true; + vma_type.vaddr = vaddr; + + invalidate_translations(vma_type); + + } + # else, silently do nothing + + } else { + # invalidate all translations from leaf page tables for address space 'asid' containing 'vaddr' + # does not affect global mappings + if (canonical_vaddr?(vaddr)) { + vma_type.single_asid = true; + vma_type.asid = asid; + vma_type.single_vaddr = true; + vma_type.vaddr = vaddr; + + invalidate_translations(vma_type); + + } + # else, silently do nothing + } diff --git a/pkg/ifuzz/riscv64/gen/inst/Svinval/sfence.inval.ir.yaml b/pkg/ifuzz/riscv64/gen/inst/Svinval/sfence.inval.ir.yaml new file mode 100644 index 000000000000..a2f76807d298 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Svinval/sfence.inval.ir.yaml @@ -0,0 +1,44 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sfence.inval.ir +long_name: Order implicit page table reads after invalidation +definedBy: + extension: + name: Svinval +encoding: + match: "00011000000100000000000001110011" +description: | + The `sfence.inval.ir` instruction guarantees that any previous `sinval.vma` + instructions executed by the current hart are ordered before subsequent implicit references by + that hart to the memory-management data structures. +access: + s: sometimes + u: never + vs: sometimes + vu: never +assembly: "" +operation(): | + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (CSR[misa].H == 1 && mode() == PrivilegeMode::VU) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + + # order all subsequent (implicit) loads after an sfence/hfence invalidation + # Unlike SFENCE.VMA/HFENCE.[GV]VMA, SFENCE.W.INVAL is indiscriminate; + # it orders all reads after all page tables + VmaOrderType vma_type; + vma_type.global = true; + vma_type.smode = true; + if (CSR[misa].H == 1) { + vma_type.vsmode = true; + vma_type.gstage = true; + } + order_pgtbl_reads_after_vmafence(vma_type); diff --git a/pkg/ifuzz/riscv64/gen/inst/Svinval/sfence.w.inval.yaml b/pkg/ifuzz/riscv64/gen/inst/Svinval/sfence.w.inval.yaml new file mode 100644 index 000000000000..7b6bf12ce41f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Svinval/sfence.w.inval.yaml @@ -0,0 +1,45 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sfence.w.inval +long_name: Order writes before sfence +definedBy: + extension: + name: Svinval +encoding: + match: "00011000000000000000000001110011" +description: | + The `sfence.w.inval` instruction guarantees that any previous stores already visible to the + current RISC-V hart are ordered before subsequent `sinval.vma` instructions executed by the + same hart. +access: + s: sometimes + u: never + vs: sometimes + vu: never +assembly: "" +operation(): | + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (CSR[misa].H == 1 && mode() == PrivilegeMode::VU) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + + # order all prior stores already visible to the current hart + # before any following sfence + # Unlike SFENCE.VMA/HFENCE.[GV]VMA, SFENCE.W.INVAL is indiscriminate; + # it orders all writes before all page tables + VmaOrderType vma_type; + vma_type.global = true; + vma_type.smode = true; + if (CSR[misa].H == 1) { + vma_type.vsmode = true; + vma_type.gstage = true; + } + order_pgtbl_writes_before_vmafence(vma_type); diff --git a/pkg/ifuzz/riscv64/gen/inst/Svinval/sinval.vma.yaml b/pkg/ifuzz/riscv64/gen/inst/Svinval/sinval.vma.yaml new file mode 100644 index 000000000000..4bc70fd57423 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Svinval/sinval.vma.yaml @@ -0,0 +1,102 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sinval.vma +long_name: Invalidate cached address translations +definedBy: + extension: + name: Svinval +encoding: + match: 0001011----------000000001110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +description: + The `sinval.vma` instruction invalidates any address-translation cache entries that an + `sfence.vma` instruction with the same values of xs1 and xs2 would invalidate. + However, unlike `sfence.vma`, `sinval.vma` instructions are only ordered with respect to + `sfence.vma`, `sfence.w.inval`, and `sfence.inval.ir` instructions as defined below. +access: + s: sometimes + u: never + vs: sometimes + vu: never +assembly: xs1, xs2 +operation(): | + XReg vaddr = X[xs1]; + Bits asid = X[xs2][ASID_WIDTH-1:0]; + + if (CSR[mstatus].TVM == 1 && + ((mode() == PrivilegeMode::S) || (mode() == PrivilegeMode::VS))) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (CSR[misa].H == 1 && CSR[hstatus].VTVM == 1 && mode() == PrivilegeMode::VS) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (CSR[misa].H == 1 && mode() == PrivilegeMode::VU) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + + # note: this will default to "all" + VmaOrderType vma_type; + if (CSR[misa].H == 1 && mode() == PrivilegeMode::VS) { + vma_type.vsmode = true; + vma_type.single_vmid = true; + vma_type.vmid = CSR[hgatp].VMID; + } else { + vma_type.smode = true; + } + + if ((xs1 == 0) && (xs2 == 0)) { + # invalidate all translations, from all addresses and all ASIDs + # includes global mappings + vma_type.global = true; + + invalidate_translations(vma_type); + + } else if ((xs1 == 0) && (xs2 != 0)) { + # invalidates all translations from ASID 'asid' + # does not affect global mappings + vma_type.single_asid = true; + vma_type.asid = asid; + + invalidate_translations(vma_type); + + } else if ((xs1 != 0) && (xs2 == 0)) { + # invalidate all translations from leaf page tables containing 'vaddr' + # does not affect global mappings + if (canonical_vaddr?(vaddr)) { + vma_type.single_vaddr = true; + vma_type.vaddr = vaddr; + + invalidate_translations(vma_type); + + } + # else, silently do nothing + + } else { + # invalidate all translations from leaf page tables for address space 'asid' containing 'vaddr' + # does not affect global mappings + if (canonical_vaddr?(vaddr)) { + vma_type.single_asid = true; + vma_type.asid = asid; + vma_type.single_vaddr = true; + vma_type.vaddr = vaddr; + + invalidate_translations(vma_type); + + } + # else, silently do nothing + } diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vaadd.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vaadd.vv.yaml new file mode 100644 index 000000000000..4cd90fab363b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vaadd.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaadd.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001001-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vaadd.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vaadd.vx.yaml new file mode 100644 index 000000000000..92fa7a02399e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vaadd.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaadd.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001001-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vaaddu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vaaddu.vv.yaml new file mode 100644 index 000000000000..2eef699140ff --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vaaddu.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaaddu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001000-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vaaddu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vaaddu.vx.yaml new file mode 100644 index 000000000000..2c5810942384 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vaaddu.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaaddu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001000-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vadc.vim.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vadc.vim.yaml new file mode 100644 index 000000000000..1e39d611ac1b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vadc.vim.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vadc.vim +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, v0 +encoding: + match: 0100000----------011-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + /* for bypassing normal masking in init_masked_result */ + vec_trues : vector('n, dec, bool) = undefined; + foreach (i from 0 to (num_elem - 1)) { + vec_trues[i] = true + }; + + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VIMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(imm_val) + unsigned(bool_to_bits(vm_val[i]))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vadc.vvm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vadc.vvm.yaml new file mode 100644 index 000000000000..8d36df7950cd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vadc.vvm.yaml @@ -0,0 +1,76 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vadc.vvm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, v0 +encoding: + match: 0100000----------000-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + /* for bypassing normal masking in init_masked_result */ + vec_trues : vector('n, dec, bool) = undefined; + foreach (i from 0 to (num_elem - 1)) { + vec_trues[i] = true + }; + + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VVMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(vs1_val[i]) + unsigned(bool_to_bits(vm_val[i]))), + VVMS_VSBC => to_bits(SEW, unsigned(vs2_val[i]) - unsigned(vs1_val[i]) - unsigned(bool_to_bits(vm_val[i]))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vadc.vxm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vadc.vxm.yaml new file mode 100644 index 000000000000..be0490b44454 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vadc.vxm.yaml @@ -0,0 +1,76 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vadc.vxm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, v0 +encoding: + match: 0100000----------100-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + /* for bypassing normal masking in init_masked_result */ + vec_trues : vector('n, dec, bool) = undefined; + foreach (i from 0 to (num_elem - 1)) { + vec_trues[i] = true + }; + + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VXMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(rs1_val) + unsigned(bool_to_bits(vm_val[i]))), + VXMS_VSBC => to_bits(SEW, unsigned(vs2_val[i]) - unsigned(rs1_val) - unsigned(bool_to_bits(vm_val[i]))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vadd.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vadd.vi.yaml new file mode 100644 index 000000000000..abe8fb380e0b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vadd.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vadd.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 000000-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vadd.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vadd.vv.yaml new file mode 100644 index 000000000000..addc9cb9bb4a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vadd.vv.yaml @@ -0,0 +1,158 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vadd.vv +long_name: Vector-vector integer addition +description: | + Add source vector register groups from vs1 and vs2 according to mask vm and store results in vd. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000000-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + VectorState state = vector_state(); + VectorLmulType lmul_type = state.lmul_type; + + XReg vlen = VLEN; + XReg vlmax; + if (lmul_type == VectorLmulType::Multiply) { + vlmax = (vlen << state.log2_lmul) >> state.log2_sew; + } else { + # (lmul_type == VectorLmulType::Divide) + vlmax = (vlen >> state.log2_lmul) >> state.log2_sew; + } + + for (U32 i = CSR[vstart].VALUE; i < vlmax; i++) { + U32 start_bit_pos = i * state.sew; + U32 end_bit_pos = start_bit_pos + state.sew - 1; + v[vd] = { + v[vd][VLEN-1:end_bit_pos + 1], + (v[vs2])[end_bit_pos:start_bit_pos] + (v[vs1])[end_bit_pos:start_bit_pos], + v[vd][start_bit_pos-1:0] + }; + } + + CSR[vstart].VALUE = 0; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vadd.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vadd.vx.yaml new file mode 100644 index 000000000000..b38229500545 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vadd.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vadd.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 000000-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vand.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vand.vi.yaml new file mode 100644 index 000000000000..15fe9d162103 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vand.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vand.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 001001-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vand.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vand.vv.yaml new file mode 100644 index 000000000000..34637351c40b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vand.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vand.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001001-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vand.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vand.vx.yaml new file mode 100644 index 000000000000..93532b42a838 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vand.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vand.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001001-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vasub.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vasub.vv.yaml new file mode 100644 index 000000000000..727b2cd10de5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vasub.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vasub.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001011-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vasub.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vasub.vx.yaml new file mode 100644 index 000000000000..0b3d687f43b9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vasub.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vasub.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001011-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vasubu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vasubu.vv.yaml new file mode 100644 index 000000000000..f698427c2e7a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vasubu.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vasubu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001010-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vasubu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vasubu.vx.yaml new file mode 100644 index 000000000000..58a306db1810 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vasubu.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vasubu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001010-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vcompress.vm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vcompress.vm.yaml new file mode 100644 index 000000000000..b595b87a69fe --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vcompress.vm.yaml @@ -0,0 +1,85 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vcompress.vm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0101111----------010-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let start_element = get_start_element(); + let end_element = get_end_element(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + /* vcompress should always be executed with a vstart of 0 */ + if start_element != 0 | vs1 == vd | vs2 == vd | illegal_vd_unmasked() + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + + /* body elements */ + vd_idx : nat = 0; + foreach (i from 0 to (num_elem - 1)) { + if i <= end_element then { + if vs1_val[i] then { + let 'p = vd_idx; + assert('p < 'n); + result['p] = vs2_val[i]; + vd_idx = vd_idx + 1; + } + } + }; + /* tail elements */ + if vd_idx < num_elem then { + let tail_ag : agtype = get_vtype_vta(); + let 'p = vd_idx; + foreach (i from 'p to (num_elem - 1)) { + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vcpop.m.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vcpop.m.yaml new file mode 100644 index 000000000000..9dc313485e6e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vcpop.m.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vcpop.m +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: xd, vs2, vm +encoding: + match: 010000------10000010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vdiv.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vdiv.vv.yaml new file mode 100644 index 000000000000..6e09653b752d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vdiv.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vdiv.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100001-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vdiv.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vdiv.vx.yaml new file mode 100644 index 000000000000..b254c61cd9d2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vdiv.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vdiv.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100001-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vdivu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vdivu.vv.yaml new file mode 100644 index 000000000000..68d99ced3f13 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vdivu.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vdivu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100000-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vdivu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vdivu.vx.yaml new file mode 100644 index 000000000000..9c523ea94b6d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vdivu.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vdivu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100000-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfadd.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfadd.vf.yaml new file mode 100644 index 000000000000..18ac9c5cbf31 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfadd.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfadd.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 000000-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfadd.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfadd.vv.yaml new file mode 100644 index 000000000000..fe873cc83f99 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfadd.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfadd.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000000-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]), + FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]), + FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0], + FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0], + FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0] + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfclass.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfclass.v.yaml new file mode 100644 index 000000000000..51e9bfeac81e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfclass.v.yaml @@ -0,0 +1,97 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfclass.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010011------10000001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfunary1 { + FVV_VSQRT => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Sqrt(rm_3b, vs2_val[i]), + 32 => riscv_f32Sqrt(rm_3b, vs2_val[i]), + 64 => riscv_f64Sqrt(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VRSQRT7 => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Rsqrte7(rm_3b, vs2_val[i]), + 32 => riscv_f32Rsqrte7(rm_3b, vs2_val[i]), + 64 => riscv_f64Rsqrte7(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VREC7 => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Recip7(rm_3b, vs2_val[i]), + 32 => riscv_f32Recip7(rm_3b, vs2_val[i]), + 64 => riscv_f64Recip7(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VCLASS => fp_class(vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.f.x.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.f.x.v.yaml new file mode 100644 index 000000000000..411b49661d70 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.f.x.v.yaml @@ -0,0 +1,122 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfcvt.f.x.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00011001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfunary0 { + FV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_ui64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_i64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(0b001, vs2_val[i]), + 32 => riscv_f32ToUi32(0b001, vs2_val[i]), + 64 => riscv_f64ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(0b001, vs2_val[i]), + 32 => riscv_f32ToI32(0b001, vs2_val[i]), + 64 => riscv_f64ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.f.xu.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.f.xu.v.yaml new file mode 100644 index 000000000000..6641d15db927 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.f.xu.v.yaml @@ -0,0 +1,122 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfcvt.f.xu.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00010001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfunary0 { + FV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_ui64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_i64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(0b001, vs2_val[i]), + 32 => riscv_f32ToUi32(0b001, vs2_val[i]), + 64 => riscv_f64ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(0b001, vs2_val[i]), + 32 => riscv_f32ToI32(0b001, vs2_val[i]), + 64 => riscv_f64ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.rtz.x.f.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.rtz.x.f.v.yaml new file mode 100644 index 000000000000..b2406a081d0c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.rtz.x.f.v.yaml @@ -0,0 +1,122 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfcvt.rtz.x.f.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00111001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfunary0 { + FV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_ui64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_i64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(0b001, vs2_val[i]), + 32 => riscv_f32ToUi32(0b001, vs2_val[i]), + 64 => riscv_f64ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(0b001, vs2_val[i]), + 32 => riscv_f32ToI32(0b001, vs2_val[i]), + 64 => riscv_f64ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.rtz.xu.f.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.rtz.xu.f.v.yaml new file mode 100644 index 000000000000..c1357af666ee --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.rtz.xu.f.v.yaml @@ -0,0 +1,122 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfcvt.rtz.xu.f.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00110001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfunary0 { + FV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_ui64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_i64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(0b001, vs2_val[i]), + 32 => riscv_f32ToUi32(0b001, vs2_val[i]), + 64 => riscv_f64ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(0b001, vs2_val[i]), + 32 => riscv_f32ToI32(0b001, vs2_val[i]), + 64 => riscv_f64ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.x.f.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.x.f.v.yaml new file mode 100644 index 000000000000..0e3c2635c6c1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.x.f.v.yaml @@ -0,0 +1,122 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfcvt.x.f.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00001001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfunary0 { + FV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_ui64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_i64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(0b001, vs2_val[i]), + 32 => riscv_f32ToUi32(0b001, vs2_val[i]), + 64 => riscv_f64ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(0b001, vs2_val[i]), + 32 => riscv_f32ToI32(0b001, vs2_val[i]), + 64 => riscv_f64ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.xu.f.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.xu.f.v.yaml new file mode 100644 index 000000000000..f3414bde2db2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfcvt.xu.f.v.yaml @@ -0,0 +1,122 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfcvt.xu.f.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00000001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfunary0 { + FV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI32(rm_3b, vs2_val[i]), + 64 => riscv_f64ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_ui64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF32(rm_3b, vs2_val[i]), + 64 => riscv_i64ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToUi16(0b001, vs2_val[i]), + 32 => riscv_f32ToUi32(0b001, vs2_val[i]), + 64 => riscv_f64ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16ToI16(0b001, vs2_val[i]), + 32 => riscv_f32ToI32(0b001, vs2_val[i]), + 64 => riscv_f64ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfdiv.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfdiv.vf.yaml new file mode 100644 index 000000000000..e3704be51c67 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfdiv.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfdiv.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 100000-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfdiv.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfdiv.vv.yaml new file mode 100644 index 000000000000..5da10233cdc7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfdiv.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfdiv.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100000-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]), + FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]), + FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0], + FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0], + FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0] + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfirst.m.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfirst.m.yaml new file mode 100644 index 000000000000..c93eae0cd18f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfirst.m.yaml @@ -0,0 +1,66 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfirst.m +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: xd, vs2, vm +encoding: + match: 010000------10001010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = unsigned(vlenb) * 8; + + if illegal_vd_unmasked() | not(assert_vstart(0)) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vs2_val, vm_val); + + index : int = -1; + foreach (i from 0 to (num_elem - 1)) { + if index == -1 then { + if mask[i] & vs2_val[i] then index = i; + }; + }; + + X(rd) = to_bits(sizeof(xlen), index); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmacc.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmacc.vf.yaml new file mode 100644 index 000000000000..2f0ba867780a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmacc.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmacc.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 101100-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VMACC => fp_muladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMACC => fp_nmulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMSAC => fp_mulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMSAC => fp_nmuladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMADD => fp_muladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMADD => fp_nmulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VMSUB => fp_mulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMSUB => fp_nmuladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmacc.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmacc.vv.yaml new file mode 100644 index 000000000000..3e958e484977 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmacc.vv.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmacc.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101100-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VMACC => fp_muladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMACC => fp_nmulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMSAC => fp_mulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMSAC => fp_nmuladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMADD => fp_muladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmadd.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmadd.vf.yaml new file mode 100644 index 000000000000..dff262615c9e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmadd.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmadd.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 101000-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VMACC => fp_muladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMACC => fp_nmulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMSAC => fp_mulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMSAC => fp_nmuladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMADD => fp_muladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMADD => fp_nmulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VMSUB => fp_mulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMSUB => fp_nmuladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmadd.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmadd.vv.yaml new file mode 100644 index 000000000000..298bbfe46323 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmadd.vv.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmadd.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101000-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VMACC => fp_muladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMACC => fp_nmulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMSAC => fp_mulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMSAC => fp_nmuladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMADD => fp_muladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmax.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmax.vf.yaml new file mode 100644 index 000000000000..475925961dcf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmax.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmax.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 000110-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmax.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmax.vv.yaml new file mode 100644 index 000000000000..e2e34d8f2b3c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmax.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmax.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000110-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]), + FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]), + FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0], + FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0], + FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0] + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmerge.vfm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmerge.vfm.yaml new file mode 100644 index 000000000000..5ccec9a2ec4d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmerge.vfm.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmerge.vfm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, v0 +encoding: + match: 0101110----------101-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let start_element = get_start_element(); + let end_element = get_end_element(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ + let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ + + if illegal_fp_vd_masked(vd, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + + let tail_ag : agtype = get_vtype_vta(); + foreach (i from 0 to (num_elem - 1)) { + if i < start_element then { + result[i] = vd_val[i] + } else if i > end_element | i >= real_num_elem then { + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ + } + } else { + /* the merge operates on all body elements */ + result[i] = if vm_val[i] then rs1_val else vs2_val[i] + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmin.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmin.vf.yaml new file mode 100644 index 000000000000..69e0801cc3db --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmin.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmin.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 000100-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmin.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmin.vv.yaml new file mode 100644 index 000000000000..1b79279567cd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmin.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmin.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000100-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]), + FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]), + FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0], + FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0], + FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0] + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmsac.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmsac.vf.yaml new file mode 100644 index 000000000000..b1b43e9956fd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmsac.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmsac.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 101110-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VMACC => fp_muladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMACC => fp_nmulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMSAC => fp_mulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMSAC => fp_nmuladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMADD => fp_muladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMADD => fp_nmulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VMSUB => fp_mulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMSUB => fp_nmuladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmsac.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmsac.vv.yaml new file mode 100644 index 000000000000..95b4206e8b1b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmsac.vv.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmsac.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101110-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VMACC => fp_muladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMACC => fp_nmulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMSAC => fp_mulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMSAC => fp_nmuladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMADD => fp_muladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmsub.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmsub.vf.yaml new file mode 100644 index 000000000000..b550cf8f1239 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmsub.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmsub.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 101010-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VMACC => fp_muladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMACC => fp_nmulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMSAC => fp_mulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMSAC => fp_nmuladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMADD => fp_muladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMADD => fp_nmulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VMSUB => fp_mulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMSUB => fp_nmuladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmsub.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmsub.vv.yaml new file mode 100644 index 000000000000..cb7b68595d82 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmsub.vv.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmsub.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101010-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VMACC => fp_muladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMACC => fp_nmulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMSAC => fp_mulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMSAC => fp_nmuladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMADD => fp_muladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmul.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmul.vf.yaml new file mode 100644 index 000000000000..89ef10329046 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmul.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmul.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 100100-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmul.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmul.vv.yaml new file mode 100644 index 000000000000..75c23f622f62 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmul.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmul.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100100-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]), + FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]), + FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0], + FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0], + FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0] + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmv.f.s.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmv.f.s.yaml new file mode 100644 index 000000000000..a7210c9e0206 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmv.f.s.yaml @@ -0,0 +1,58 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmv.f.s +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: fd, vs2 +encoding: + match: 0100001-----00000001-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let num_elem = get_num_elem(0, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) | SEW > sizeof(flen) + then { handle_illegal(); return RETIRE_FAIL }; + assert(num_elem > 0 & SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2); + match 'm { + 16 => F_H(rd) = vs2_val[0], + 32 => F_S(rd) = vs2_val[0], + 64 => F_D(rd) = vs2_val[0] + }; + vstart = zeros(); + + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmv.s.f.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmv.s.f.yaml new file mode 100644 index 000000000000..e5db5eec5efc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmv.s.f.yaml @@ -0,0 +1,71 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmv.s.f +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1 +encoding: + match: 010000100000-----101-----1010111 + variables: + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let num_elem = get_num_elem(0, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(num_elem > 0 & SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, 0, vd_val, vm_val); + + /* one body element */ + if mask[0] then result[0] = rs1_val; + + /* others treated as tail elements */ + let tail_ag : agtype = get_vtype_vta(); + foreach (i from 1 to (num_elem - 1)) { + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ + } + }; + + write_vreg(num_elem, SEW, 0, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfmv.v.f.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfmv.v.f.yaml new file mode 100644 index 000000000000..32c24992a1fe --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfmv.v.f.yaml @@ -0,0 +1,64 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfmv.v.f +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1 +encoding: + match: 010111100000-----101-----1010111 + variables: + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then result[i] = rs1_val + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.f.f.w.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.f.f.w.yaml new file mode 100644 index 000000000000..85befc7daf6f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.f.f.w.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfncvt.f.f.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------10100001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfnunary0 { + FNV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToUi32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToI32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_ui32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_ui64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_i32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_i64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_ROD_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(0b110, vs2_val[i]), + 32 => riscv_f64ToF32(0b110, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(0b001, vs2_val[i]), + 16 => riscv_f32ToUi16(0b001, vs2_val[i]), + 32 => riscv_f64ToUi32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(0b001, vs2_val[i]), + 16 => riscv_f32ToI16(0b001, vs2_val[i]), + 32 => riscv_f64ToI32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.f.x.w.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.f.x.w.yaml new file mode 100644 index 000000000000..f54ebc2e1917 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.f.x.w.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfncvt.f.x.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------10011001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfnunary0 { + FNV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToUi32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToI32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_ui32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_ui64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_i32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_i64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_ROD_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(0b110, vs2_val[i]), + 32 => riscv_f64ToF32(0b110, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(0b001, vs2_val[i]), + 16 => riscv_f32ToUi16(0b001, vs2_val[i]), + 32 => riscv_f64ToUi32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(0b001, vs2_val[i]), + 16 => riscv_f32ToI16(0b001, vs2_val[i]), + 32 => riscv_f64ToI32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.f.xu.w.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.f.xu.w.yaml new file mode 100644 index 000000000000..31e3b36a498b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.f.xu.w.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfncvt.f.xu.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------10010001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfnunary0 { + FNV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToUi32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToI32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_ui32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_ui64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_i32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_i64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_ROD_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(0b110, vs2_val[i]), + 32 => riscv_f64ToF32(0b110, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(0b001, vs2_val[i]), + 16 => riscv_f32ToUi16(0b001, vs2_val[i]), + 32 => riscv_f64ToUi32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(0b001, vs2_val[i]), + 16 => riscv_f32ToI16(0b001, vs2_val[i]), + 32 => riscv_f64ToI32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.rod.f.f.w.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.rod.f.f.w.yaml new file mode 100644 index 000000000000..237751eff54c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.rod.f.f.w.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfncvt.rod.f.f.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------10101001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfnunary0 { + FNV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToUi32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToI32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_ui32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_ui64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_i32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_i64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_ROD_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(0b110, vs2_val[i]), + 32 => riscv_f64ToF32(0b110, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(0b001, vs2_val[i]), + 16 => riscv_f32ToUi16(0b001, vs2_val[i]), + 32 => riscv_f64ToUi32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(0b001, vs2_val[i]), + 16 => riscv_f32ToI16(0b001, vs2_val[i]), + 32 => riscv_f64ToI32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.rtz.x.f.w.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.rtz.x.f.w.yaml new file mode 100644 index 000000000000..fb0ed7cde24c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.rtz.x.f.w.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfncvt.rtz.x.f.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------10111001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfnunary0 { + FNV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToUi32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToI32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_ui32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_ui64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_i32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_i64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_ROD_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(0b110, vs2_val[i]), + 32 => riscv_f64ToF32(0b110, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(0b001, vs2_val[i]), + 16 => riscv_f32ToUi16(0b001, vs2_val[i]), + 32 => riscv_f64ToUi32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(0b001, vs2_val[i]), + 16 => riscv_f32ToI16(0b001, vs2_val[i]), + 32 => riscv_f64ToI32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.rtz.xu.f.w.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.rtz.xu.f.w.yaml new file mode 100644 index 000000000000..1aa5a08ee842 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.rtz.xu.f.w.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfncvt.rtz.xu.f.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------10110001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfnunary0 { + FNV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToUi32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToI32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_ui32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_ui64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_i32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_i64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_ROD_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(0b110, vs2_val[i]), + 32 => riscv_f64ToF32(0b110, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(0b001, vs2_val[i]), + 16 => riscv_f32ToUi16(0b001, vs2_val[i]), + 32 => riscv_f64ToUi32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(0b001, vs2_val[i]), + 16 => riscv_f32ToI16(0b001, vs2_val[i]), + 32 => riscv_f64ToI32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.x.f.w.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.x.f.w.yaml new file mode 100644 index 000000000000..cd4941b16e6b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.x.f.w.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfncvt.x.f.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------10001001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfnunary0 { + FNV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToUi32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToI32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_ui32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_ui64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_i32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_i64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_ROD_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(0b110, vs2_val[i]), + 32 => riscv_f64ToF32(0b110, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(0b001, vs2_val[i]), + 16 => riscv_f32ToUi16(0b001, vs2_val[i]), + 32 => riscv_f64ToUi32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(0b001, vs2_val[i]), + 16 => riscv_f32ToI16(0b001, vs2_val[i]), + 32 => riscv_f64ToI32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.xu.f.w.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.xu.f.w.yaml new file mode 100644 index 000000000000..447e81084e8a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfncvt.xu.f.w.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfncvt.xu.f.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------10000001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfnunary0 { + FNV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToUi16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToUi32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(rm_3b, vs2_val[i]), + 16 => riscv_f32ToI16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToI32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_ui32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_ui64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_i32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_i64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(rm_3b, vs2_val[i]), + 32 => riscv_f64ToF32(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_ROD_F_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f32ToF16(0b110, vs2_val[i]), + 32 => riscv_f64ToF32(0b110, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToUi8(0b001, vs2_val[i]), + 16 => riscv_f32ToUi16(0b001, vs2_val[i]), + 32 => riscv_f64ToUi32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FNV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 8 => riscv_f16ToI8(0b001, vs2_val[i]), + 16 => riscv_f32ToI16(0b001, vs2_val[i]), + 32 => riscv_f64ToI32(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfnmacc.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfnmacc.vf.yaml new file mode 100644 index 000000000000..9d280cf496c3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfnmacc.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfnmacc.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 101101-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VMACC => fp_muladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMACC => fp_nmulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMSAC => fp_mulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMSAC => fp_nmuladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMADD => fp_muladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMADD => fp_nmulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VMSUB => fp_mulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMSUB => fp_nmuladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfnmacc.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfnmacc.vv.yaml new file mode 100644 index 000000000000..103f932ed9a2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfnmacc.vv.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfnmacc.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101101-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VMACC => fp_muladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMACC => fp_nmulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMSAC => fp_mulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMSAC => fp_nmuladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMADD => fp_muladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfnmadd.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfnmadd.vf.yaml new file mode 100644 index 000000000000..710840f647af --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfnmadd.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfnmadd.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 101001-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VMACC => fp_muladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMACC => fp_nmulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMSAC => fp_mulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMSAC => fp_nmuladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMADD => fp_muladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMADD => fp_nmulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VMSUB => fp_mulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMSUB => fp_nmuladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfnmadd.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfnmadd.vv.yaml new file mode 100644 index 000000000000..37ff3fc23c79 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfnmadd.vv.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfnmadd.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101001-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VMACC => fp_muladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMACC => fp_nmulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMSAC => fp_mulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMSAC => fp_nmuladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMADD => fp_muladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfnmsac.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfnmsac.vf.yaml new file mode 100644 index 000000000000..c00b1e4f8e35 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfnmsac.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfnmsac.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 101111-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VMACC => fp_muladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMACC => fp_nmulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMSAC => fp_mulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMSAC => fp_nmuladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMADD => fp_muladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMADD => fp_nmulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VMSUB => fp_mulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMSUB => fp_nmuladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfnmsac.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfnmsac.vv.yaml new file mode 100644 index 000000000000..4a2dfbb2d1cc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfnmsac.vv.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfnmsac.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101111-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VMACC => fp_muladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMACC => fp_nmulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMSAC => fp_mulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMSAC => fp_nmuladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMADD => fp_muladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfnmsub.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfnmsub.vf.yaml new file mode 100644 index 000000000000..8fbdc0c79b62 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfnmsub.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfnmsub.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 101011-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VMACC => fp_muladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMACC => fp_nmulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMSAC => fp_mulsub(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VNMSAC => fp_nmuladd(rm_3b, rs1_val, vs2_val[i], vd_val[i]), + VF_VMADD => fp_muladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMADD => fp_nmulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VMSUB => fp_mulsub(rm_3b, rs1_val, vd_val[i], vs2_val[i]), + VF_VNMSUB => fp_nmuladd(rm_3b, rs1_val, vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfnmsub.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfnmsub.vv.yaml new file mode 100644 index 000000000000..e62e646dff27 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfnmsub.vv.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfnmsub.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101011-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VMACC => fp_muladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMACC => fp_nmulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMSAC => fp_mulsub(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VNMSAC => fp_nmuladd(rm_3b, vs1_val[i], vs2_val[i], vd_val[i]), + FVV_VMADD => fp_muladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMADD => fp_nmulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VMSUB => fp_mulsub(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]), + FVV_VNMSUB => fp_nmuladd(rm_3b, vs1_val[i], vd_val[i], vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfrdiv.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfrdiv.vf.yaml new file mode 100644 index 000000000000..f2b25fb19230 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfrdiv.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfrdiv.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 100001-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfrec7.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfrec7.v.yaml new file mode 100644 index 000000000000..1c302462607c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfrec7.v.yaml @@ -0,0 +1,97 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfrec7.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010011------00101001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfunary1 { + FVV_VSQRT => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Sqrt(rm_3b, vs2_val[i]), + 32 => riscv_f32Sqrt(rm_3b, vs2_val[i]), + 64 => riscv_f64Sqrt(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VRSQRT7 => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Rsqrte7(rm_3b, vs2_val[i]), + 32 => riscv_f32Rsqrte7(rm_3b, vs2_val[i]), + 64 => riscv_f64Rsqrte7(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VREC7 => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Recip7(rm_3b, vs2_val[i]), + 32 => riscv_f32Recip7(rm_3b, vs2_val[i]), + 64 => riscv_f64Recip7(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VCLASS => fp_class(vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfredmax.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfredmax.vs.yaml new file mode 100644 index 000000000000..4068453dd75c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfredmax.vs.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfredmax.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000111-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then + process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + else + process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfredmin.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfredmin.vs.yaml new file mode 100644 index 000000000000..9c0669ed51b3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfredmin.vs.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfredmin.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000101-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then + process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + else + process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfredosum.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfredosum.vs.yaml new file mode 100644 index 000000000000..8809787772c7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfredosum.vs.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfredosum.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000011-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then + process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + else + process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfredusum.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfredusum.vs.yaml new file mode 100644 index 000000000000..b4c0ae0327ec --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfredusum.vs.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfredusum.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000001-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then + process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + else + process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfrsqrt7.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfrsqrt7.v.yaml new file mode 100644 index 000000000000..aa191fcaf1d7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfrsqrt7.v.yaml @@ -0,0 +1,97 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfrsqrt7.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010011------00100001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfunary1 { + FVV_VSQRT => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Sqrt(rm_3b, vs2_val[i]), + 32 => riscv_f32Sqrt(rm_3b, vs2_val[i]), + 64 => riscv_f64Sqrt(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VRSQRT7 => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Rsqrte7(rm_3b, vs2_val[i]), + 32 => riscv_f32Rsqrte7(rm_3b, vs2_val[i]), + 64 => riscv_f64Rsqrte7(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VREC7 => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Recip7(rm_3b, vs2_val[i]), + 32 => riscv_f32Recip7(rm_3b, vs2_val[i]), + 64 => riscv_f64Recip7(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VCLASS => fp_class(vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfrsub.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfrsub.vf.yaml new file mode 100644 index 000000000000..509252e46153 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfrsub.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfrsub.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 100111-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfsgnj.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnj.vf.yaml new file mode 100644 index 000000000000..33bf00cc6009 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnj.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfsgnj.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 001000-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfsgnj.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnj.vv.yaml new file mode 100644 index 000000000000..426f92bdf690 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnj.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfsgnj.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001000-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]), + FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]), + FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0], + FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0], + FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0] + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjn.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjn.vf.yaml new file mode 100644 index 000000000000..d3f767613ea4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjn.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfsgnjn.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 001001-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjn.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjn.vv.yaml new file mode 100644 index 000000000000..179028b8c71c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjn.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfsgnjn.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001001-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]), + FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]), + FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0], + FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0], + FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0] + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjx.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjx.vf.yaml new file mode 100644 index 000000000000..46d4e752300a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjx.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfsgnjx.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 001010-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjx.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjx.vv.yaml new file mode 100644 index 000000000000..2b7221c1a903 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfsgnjx.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfsgnjx.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001010-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]), + FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]), + FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0], + FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0], + FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0] + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfslide1down.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfslide1down.vf.yaml new file mode 100644 index 000000000000..df621ea0ac48 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfslide1down.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfslide1down.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 001111-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfslide1up.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfslide1up.vf.yaml new file mode 100644 index 000000000000..30f50fa3f7eb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfslide1up.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfslide1up.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 001110-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfsqrt.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfsqrt.v.yaml new file mode 100644 index 000000000000..b59940c48831 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfsqrt.v.yaml @@ -0,0 +1,97 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfsqrt.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010011------00000001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfunary1 { + FVV_VSQRT => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Sqrt(rm_3b, vs2_val[i]), + 32 => riscv_f32Sqrt(rm_3b, vs2_val[i]), + 64 => riscv_f64Sqrt(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VRSQRT7 => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Rsqrte7(rm_3b, vs2_val[i]), + 32 => riscv_f32Rsqrte7(rm_3b, vs2_val[i]), + 64 => riscv_f64Rsqrte7(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VREC7 => { + let (fflags, elem) : (bits_fflags, bits('m)) = match 'm { + 16 => riscv_f16Recip7(rm_3b, vs2_val[i]), + 32 => riscv_f32Recip7(rm_3b, vs2_val[i]), + 64 => riscv_f64Recip7(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FVV_VCLASS => fp_class(vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfsub.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfsub.vf.yaml new file mode 100644 index 000000000000..63d3bb902be9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfsub.vf.yaml @@ -0,0 +1,92 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfsub.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 000010-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VF_VADD => fp_add(rm_3b, vs2_val[i], rs1_val), + VF_VSUB => fp_sub(rm_3b, vs2_val[i], rs1_val), + VF_VRSUB => fp_sub(rm_3b, rs1_val, vs2_val[i]), + VF_VMIN => fp_min(vs2_val[i], rs1_val), + VF_VMAX => fp_max(vs2_val[i], rs1_val), + VF_VMUL => fp_mul(rm_3b, vs2_val[i], rs1_val), + VF_VDIV => fp_div(rm_3b, vs2_val[i], rs1_val), + VF_VRDIV => fp_div(rm_3b, rs1_val, vs2_val[i]), + VF_VSGNJ => [rs1_val['m - 1]] @ vs2_val[i][('m - 2)..0], + VF_VSGNJN => (0b1 ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSGNJX => ([vs2_val[i]['m - 1]] ^ [rs1_val['m - 1]]) @ vs2_val[i][('m - 2)..0], + VF_VSLIDE1UP => { + if vs2 == vd then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + VF_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfsub.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfsub.vv.yaml new file mode 100644 index 000000000000..bf99fdf7198a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfsub.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfsub.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000010-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FVV_VADD => fp_add(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSUB => fp_sub(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VMIN => fp_min(vs2_val[i], vs1_val[i]), + FVV_VMAX => fp_max(vs2_val[i], vs1_val[i]), + FVV_VMUL => fp_mul(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VDIV => fp_div(rm_3b, vs2_val[i], vs1_val[i]), + FVV_VSGNJ => [vs1_val[i]['m - 1]] @ vs2_val[i][('m - 2)..0], + FVV_VSGNJN => (0b1 ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0], + FVV_VSGNJX => ([vs2_val[i]['m - 1]] ^ [vs1_val[i]['m - 1]]) @ vs2_val[i][('m - 2)..0] + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.vf.yaml new file mode 100644 index 000000000000..89ec5b87a192 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwadd.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 110000-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVF_VADD => fp_add(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)), + FWVF_VSUB => fp_sub(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)), + FWVF_VMUL => fp_mul(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.vv.yaml new file mode 100644 index 000000000000..541ace2b3d15 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwadd.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110000-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVV_VADD => fp_add(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])), + FWVV_VSUB => fp_sub(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])), + FWVV_VMUL => fp_mul(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.wf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.wf.yaml new file mode 100644 index 000000000000..6e48e1162546 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.wf.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwadd.wf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 110100-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWF_VADD => fp_add(rm_3b, vs2_val[i], fp_widen(rs1_val)), + FWF_VSUB => fp_sub(rm_3b, vs2_val[i], fp_widen(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.wv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.wv.yaml new file mode 100644 index 000000000000..5d37ce7d7585 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwadd.wv.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwadd.wv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110100-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWV_VADD => fp_add(rm_3b, vs2_val[i], fp_widen(vs1_val[i])), + FWV_VSUB => fp_sub(rm_3b, vs2_val[i], fp_widen(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.f.f.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.f.f.v.yaml new file mode 100644 index 000000000000..8934a4509bbb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.f.f.v.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwcvt.f.f.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------01100001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 8 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfwunary0 { + FWV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 16 => riscv_ui32ToF32(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 16 => riscv_i32ToF32(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToF32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(0b001, vs2_val[i]), + 32 => riscv_f32ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(0b001, vs2_val[i]), + 32 => riscv_f32ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.f.x.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.f.x.v.yaml new file mode 100644 index 000000000000..0435283628e2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.f.x.v.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwcvt.f.x.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------01011001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 8 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfwunary0 { + FWV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 16 => riscv_ui32ToF32(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 16 => riscv_i32ToF32(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToF32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(0b001, vs2_val[i]), + 32 => riscv_f32ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(0b001, vs2_val[i]), + 32 => riscv_f32ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.f.xu.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.f.xu.v.yaml new file mode 100644 index 000000000000..8972e68888a2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.f.xu.v.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwcvt.f.xu.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------01010001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 8 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfwunary0 { + FWV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 16 => riscv_ui32ToF32(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 16 => riscv_i32ToF32(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToF32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(0b001, vs2_val[i]), + 32 => riscv_f32ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(0b001, vs2_val[i]), + 32 => riscv_f32ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.rtz.x.f.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.rtz.x.f.v.yaml new file mode 100644 index 000000000000..169886975771 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.rtz.x.f.v.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwcvt.rtz.x.f.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------01111001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 8 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfwunary0 { + FWV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 16 => riscv_ui32ToF32(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 16 => riscv_i32ToF32(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToF32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(0b001, vs2_val[i]), + 32 => riscv_f32ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(0b001, vs2_val[i]), + 32 => riscv_f32ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.rtz.xu.f.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.rtz.xu.f.v.yaml new file mode 100644 index 000000000000..d58c0a6c23f7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.rtz.xu.f.v.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwcvt.rtz.xu.f.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------01110001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 8 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfwunary0 { + FWV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 16 => riscv_ui32ToF32(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 16 => riscv_i32ToF32(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToF32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(0b001, vs2_val[i]), + 32 => riscv_f32ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(0b001, vs2_val[i]), + 32 => riscv_f32ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.x.f.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.x.f.v.yaml new file mode 100644 index 000000000000..a25ca7d977c9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.x.f.v.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwcvt.x.f.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------01001001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 8 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfwunary0 { + FWV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 16 => riscv_ui32ToF32(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 16 => riscv_i32ToF32(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToF32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(0b001, vs2_val[i]), + 32 => riscv_f32ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(0b001, vs2_val[i]), + 32 => riscv_f32ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.xu.f.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.xu.f.v.yaml new file mode 100644 index 000000000000..edb8a94fe25e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwcvt.xu.f.v.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwcvt.xu.f.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------01000001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 8 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match vfwunary0 { + FWV_CVT_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToUi64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToI64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_XU => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])), + 16 => riscv_ui32ToF32(rm_3b, zero_extend(vs2_val[i])), + 32 => riscv_ui32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_X => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])), + 16 => riscv_i32ToF32(rm_3b, sign_extend(vs2_val[i])), + 32 => riscv_i32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_F_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToF32(rm_3b, vs2_val[i]), + 32 => riscv_f32ToF64(rm_3b, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_XU_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToUi32(0b001, vs2_val[i]), + 32 => riscv_f32ToUi64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + }, + FWV_CVT_RTZ_X_F => { + let (fflags, elem) : (bits_fflags, bits('o)) = match 'm { + 8 => { handle_illegal(); return RETIRE_FAIL }, + 16 => riscv_f16ToI32(0b001, vs2_val[i]), + 32 => riscv_f32ToI64(0b001, vs2_val[i]) + }; + accrue_fflags(fflags); + elem + } + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwmacc.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwmacc.vf.yaml new file mode 100644 index 000000000000..d30c8551d6d3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwmacc.vf.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwmacc.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 111100-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVF_VMACC => fp_muladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VNMACC => fp_nmulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VMSAC => fp_mulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VNMSAC => fp_nmuladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwmacc.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwmacc.vv.yaml new file mode 100644 index 000000000000..092beadc1545 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwmacc.vv.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwmacc.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 111100-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVV_VMACC => fp_muladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VNMACC => fp_nmulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VMSAC => fp_mulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VNMSAC => fp_nmuladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwmsac.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwmsac.vf.yaml new file mode 100644 index 000000000000..4f0a47eb127c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwmsac.vf.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwmsac.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 111110-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVF_VMACC => fp_muladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VNMACC => fp_nmulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VMSAC => fp_mulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VNMSAC => fp_nmuladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwmsac.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwmsac.vv.yaml new file mode 100644 index 000000000000..c2eb04d53560 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwmsac.vv.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwmsac.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 111110-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVV_VMACC => fp_muladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VNMACC => fp_nmulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VMSAC => fp_mulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VNMSAC => fp_nmuladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwmul.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwmul.vf.yaml new file mode 100644 index 000000000000..c562458c3423 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwmul.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwmul.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 111000-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVF_VADD => fp_add(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)), + FWVF_VSUB => fp_sub(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)), + FWVF_VMUL => fp_mul(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwmul.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwmul.vv.yaml new file mode 100644 index 000000000000..6f96075a58d9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwmul.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwmul.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 111000-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVV_VADD => fp_add(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])), + FWVV_VSUB => fp_sub(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])), + FWVV_VMUL => fp_mul(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwnmacc.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwnmacc.vf.yaml new file mode 100644 index 000000000000..dd3e02887190 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwnmacc.vf.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwnmacc.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 111101-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVF_VMACC => fp_muladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VNMACC => fp_nmulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VMSAC => fp_mulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VNMSAC => fp_nmuladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwnmacc.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwnmacc.vv.yaml new file mode 100644 index 000000000000..e2113f82f416 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwnmacc.vv.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwnmacc.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 111101-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVV_VMACC => fp_muladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VNMACC => fp_nmulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VMSAC => fp_mulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VNMSAC => fp_nmuladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwnmsac.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwnmsac.vf.yaml new file mode 100644 index 000000000000..707e5b499bbb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwnmsac.vf.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwnmsac.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, fs1, vs2, vm +encoding: + match: 111111-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVF_VMACC => fp_muladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VNMACC => fp_nmulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VMSAC => fp_mulsub(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]), + FWVF_VNMSAC => fp_nmuladd(rm_3b, fp_widen(rs1_val), fp_widen(vs2_val[i]), vd_val[i]) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwnmsac.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwnmsac.vv.yaml new file mode 100644 index 000000000000..713bca589a0b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwnmsac.vv.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwnmsac.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 111111-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVV_VMACC => fp_muladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VNMACC => fp_nmulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VMSAC => fp_mulsub(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]), + FWVV_VNMSAC => fp_nmuladd(rm_3b, fp_widen(vs1_val[i]), fp_widen(vs2_val[i]), vd_val[i]) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwredosum.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwredosum.vs.yaml new file mode 100644 index 000000000000..0a7423d92951 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwredosum.vs.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwredosum.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110011-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then + process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + else + process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwredusum.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwredusum.vs.yaml new file mode 100644 index 000000000000..db22c74c3754 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwredusum.vs.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwredusum.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110001-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + + if funct6 == FVV_VFWREDOSUM | funct6 == FVV_VFWREDUSUM then + process_rfvv_widen(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + else + process_rfvv_single(funct6, vm, vs2, vs1, vd, num_elem_vs, SEW, LMUL_pow) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.vf.yaml new file mode 100644 index 000000000000..e394f140a906 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.vf.yaml @@ -0,0 +1,80 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwsub.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 110010-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVF_VADD => fp_add(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)), + FWVF_VSUB => fp_sub(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)), + FWVF_VMUL => fp_mul(rm_3b, fp_widen(vs2_val[i]), fp_widen(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.vv.yaml new file mode 100644 index 000000000000..d3e353632a6a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.vv.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwsub.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110010-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWVV_VADD => fp_add(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])), + FWVV_VSUB => fp_sub(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])), + FWVV_VMUL => fp_mul(rm_3b, fp_widen(vs2_val[i]), fp_widen(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.wf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.wf.yaml new file mode 100644 index 000000000000..82f686b879e8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.wf.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwsub.wf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 110110-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWF_VADD => fp_add(rm_3b, vs2_val[i], fp_widen(rs1_val)), + FWF_VSUB => fp_sub(rm_3b, vs2_val[i], fp_widen(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.wv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.wv.yaml new file mode 100644 index 000000000000..bbb638054e7c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vfwsub.wv.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwsub.wv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110110-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW >= 16 & SEW_widen <= 64); + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + FWV_VADD => fp_add(rm_3b, vs2_val[i], fp_widen(vs1_val[i])), + FWV_VSUB => fp_sub(rm_3b, vs2_val[i], fp_widen(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vid.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vid.v.yaml new file mode 100644 index 000000000000..42f606f62130 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vid.v.yaml @@ -0,0 +1,61 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vid.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vm +encoding: + match: 010100-0000010001010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then result[i] = to_bits(SEW, i) + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/viota.m.yaml b/pkg/ifuzz/riscv64/gen/inst/V/viota.m.yaml new file mode 100644 index 000000000000..69695e0b49b3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/viota.m.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: viota.m +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010100------10000010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + sum : int = 0; + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = to_bits(SEW, sum); + if vs2_val[i] then sum = sum + 1 + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl1re16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl1re16.v.yaml new file mode 100644 index 000000000000..96d00cc215ce --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl1re16.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl1re16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 000000101000-----101-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl1re32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl1re32.v.yaml new file mode 100644 index 000000000000..fc7b160eede2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl1re32.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl1re32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 000000101000-----110-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl1re64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl1re64.v.yaml new file mode 100644 index 000000000000..21761558f677 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl1re64.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl1re64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 000000101000-----111-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl1re8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl1re8.v.yaml new file mode 100644 index 000000000000..a2286db70d18 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl1re8.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl1re8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 000000101000-----000-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl2re16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl2re16.v.yaml new file mode 100644 index 000000000000..0e719f3f5b9c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl2re16.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl2re16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 001000101000-----101-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl2re32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl2re32.v.yaml new file mode 100644 index 000000000000..c20729dd8f36 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl2re32.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl2re32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 001000101000-----110-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl2re64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl2re64.v.yaml new file mode 100644 index 000000000000..6b78573362a9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl2re64.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl2re64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 001000101000-----111-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl2re8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl2re8.v.yaml new file mode 100644 index 000000000000..0131d3a374d0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl2re8.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl2re8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 001000101000-----000-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl4re16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl4re16.v.yaml new file mode 100644 index 000000000000..89dec8cf6d20 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl4re16.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl4re16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 011000101000-----101-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl4re32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl4re32.v.yaml new file mode 100644 index 000000000000..d9492ec88bb3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl4re32.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl4re32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 011000101000-----110-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl4re64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl4re64.v.yaml new file mode 100644 index 000000000000..e3bc0b80118f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl4re64.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl4re64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 011000101000-----111-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl4re8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl4re8.v.yaml new file mode 100644 index 000000000000..cf1646114873 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl4re8.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl4re8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 011000101000-----000-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl8re16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl8re16.v.yaml new file mode 100644 index 000000000000..fe7e89c2f1a5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl8re16.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl8re16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 111000101000-----101-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl8re32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl8re32.v.yaml new file mode 100644 index 000000000000..414a4125f229 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl8re32.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl8re32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 111000101000-----110-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl8re64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl8re64.v.yaml new file mode 100644 index 000000000000..bd469a8682c7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl8re64.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl8re64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 111000101000-----111-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vl8re8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vl8re8.v.yaml new file mode 100644 index 000000000000..ba6e87d24bc9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vl8re8.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vl8re8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 111000101000-----000-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vle16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vle16.v.yaml new file mode 100644 index 000000000000..029611d50a48 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vle16.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vle16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 000000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vle16ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vle16ff.v.yaml new file mode 100644 index 000000000000..8b5c20b2cf56 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vle16ff.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vle16ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 000000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vle32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vle32.v.yaml new file mode 100644 index 000000000000..42e613452169 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vle32.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vle32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 000000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vle32ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vle32ff.v.yaml new file mode 100644 index 000000000000..5a64b83da5c8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vle32ff.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vle32ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 000000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vle64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vle64.v.yaml new file mode 100644 index 000000000000..7349a3c493ef --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vle64.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vle64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 000000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vle64ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vle64ff.v.yaml new file mode 100644 index 000000000000..37ba1b21a21e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vle64ff.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vle64ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 000000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vle8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vle8.v.yaml new file mode 100644 index 000000000000..c89381665818 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vle8.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vle8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 000000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); /* # of element of each register group */ + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlseg(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vle8ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vle8ff.v.yaml new file mode 100644 index 000000000000..a4bf19a70de9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vle8ff.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vle8ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 000000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlsegff(nf_int, vm, vd, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlm.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlm.v.yaml new file mode 100644 index 000000000000..a99e396c7786 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlm.v.yaml @@ -0,0 +1,48 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vlm.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1) +encoding: + match: 000000101011-----000-----0000111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW = 8; + let EMUL_pow = 0; + let vl_val = unsigned(vl); + let evl : int = if vl_val % 8 == 0 then vl_val / 8 else vl_val / 8 + 1; /* the effective vector length is evl=ceil(vl/8) */ + let num_elem = get_num_elem(EMUL_pow, EEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + assert(evl >= 0); + process_vm(vd_or_vs3, rs1, num_elem, evl, op) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxei16.v.yaml new file mode 100644 index 000000000000..0a3593cccef4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxei16.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vloxei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 000011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); + let nf_int = nfields_int(nf); + + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxei32.v.yaml new file mode 100644 index 000000000000..c01b4e521c31 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxei32.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vloxei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 000011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); + let nf_int = nfields_int(nf); + + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxei64.v.yaml new file mode 100644 index 000000000000..d13d987ccb92 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxei64.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vloxei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 000011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); + let nf_int = nfields_int(nf); + + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxei8.v.yaml new file mode 100644 index 000000000000..3f0f1a8f2de8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxei8.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vloxei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 000011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); + let nf_int = nfields_int(nf); + + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 3) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei16.v.yaml new file mode 100644 index 000000000000..2b476300fa60 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg2ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 001011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei32.v.yaml new file mode 100644 index 000000000000..6c71fd72b701 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg2ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 001011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei64.v.yaml new file mode 100644 index 000000000000..d9d229d60160 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg2ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 001011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei8.v.yaml new file mode 100644 index 000000000000..785ddffedd37 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg2ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg2ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 001011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei16.v.yaml new file mode 100644 index 000000000000..ec919edb6762 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg3ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 010011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei32.v.yaml new file mode 100644 index 000000000000..038291a873c4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg3ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 010011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei64.v.yaml new file mode 100644 index 000000000000..d3074d8b558b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg3ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 010011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei8.v.yaml new file mode 100644 index 000000000000..5d0e262fc76b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg3ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg3ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 010011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei16.v.yaml new file mode 100644 index 000000000000..e8377ae56733 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg4ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 011011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei32.v.yaml new file mode 100644 index 000000000000..d2b782c1dc48 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg4ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 011011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei64.v.yaml new file mode 100644 index 000000000000..99d0571e8440 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg4ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 011011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei8.v.yaml new file mode 100644 index 000000000000..c4f6f6b9767b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg4ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg4ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 011011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei16.v.yaml new file mode 100644 index 000000000000..7710f10af435 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg5ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 100011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei32.v.yaml new file mode 100644 index 000000000000..3e328187c905 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg5ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 100011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei64.v.yaml new file mode 100644 index 000000000000..ffbe5565384a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg5ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 100011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei8.v.yaml new file mode 100644 index 000000000000..3e9b10c7463a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg5ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg5ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 100011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei16.v.yaml new file mode 100644 index 000000000000..47e0629bac9f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg6ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 101011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei32.v.yaml new file mode 100644 index 000000000000..bea17c5715c9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg6ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 101011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei64.v.yaml new file mode 100644 index 000000000000..961f8cb039ee --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg6ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 101011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei8.v.yaml new file mode 100644 index 000000000000..d763a68ebb2d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg6ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg6ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 101011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei16.v.yaml new file mode 100644 index 000000000000..30b5ef9889ca --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg7ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 110011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei32.v.yaml new file mode 100644 index 000000000000..8c6dc7537966 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg7ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 110011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei64.v.yaml new file mode 100644 index 000000000000..e7cc7552dcaa --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg7ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 110011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei8.v.yaml new file mode 100644 index 000000000000..44a74dadca51 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg7ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg7ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 110011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei16.v.yaml new file mode 100644 index 000000000000..278912047362 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg8ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 111011-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei32.v.yaml new file mode 100644 index 000000000000..0c03d65927c8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg8ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 111011-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei64.v.yaml new file mode 100644 index 000000000000..2edaee6c5a70 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg8ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 111011-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei8.v.yaml new file mode 100644 index 000000000000..3bbe4fdec90f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vloxseg8ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vloxseg8ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 111011-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlse16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlse16.v.yaml new file mode 100644 index 000000000000..bf356868cf2c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlse16.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vlse16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 000010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlse32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlse32.v.yaml new file mode 100644 index 000000000000..aae67946a00b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlse32.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vlse32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 000010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlse64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlse64.v.yaml new file mode 100644 index 000000000000..5fe71ba7d31a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlse64.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vlse64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 000010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlse8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlse8.v.yaml new file mode 100644 index 000000000000..7af170ffd5da --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlse8.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vlse8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 000010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_load(vd, vm, nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlsseg(nf_int, vm, vd, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e16.v.yaml new file mode 100644 index 000000000000..d310b4937612 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 001000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e16ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e16ff.v.yaml new file mode 100644 index 000000000000..0657f7a228a6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e16ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e16ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 001000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e32.v.yaml new file mode 100644 index 000000000000..cfe75093e9b6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 001000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e32ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e32ff.v.yaml new file mode 100644 index 000000000000..2cbb52f2fe52 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e32ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e32ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 001000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e64.v.yaml new file mode 100644 index 000000000000..1e5745961ad1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 001000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e64ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e64ff.v.yaml new file mode 100644 index 000000000000..aa80544555df --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e64ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e64ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 001000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e8.v.yaml new file mode 100644 index 000000000000..33eee00ae983 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 001000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e8ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e8ff.v.yaml new file mode 100644 index 000000000000..69c2621f8467 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg2e8ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg2e8ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 001000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e16.v.yaml new file mode 100644 index 000000000000..60818aa0b412 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 010000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e16ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e16ff.v.yaml new file mode 100644 index 000000000000..381f5e11c6e3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e16ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e16ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 010000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e32.v.yaml new file mode 100644 index 000000000000..6885cc106cf1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 010000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e32ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e32ff.v.yaml new file mode 100644 index 000000000000..db09bd05934c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e32ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e32ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 010000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e64.v.yaml new file mode 100644 index 000000000000..a09f410c65b2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 010000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e64ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e64ff.v.yaml new file mode 100644 index 000000000000..2de52f7da921 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e64ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e64ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 010000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e8.v.yaml new file mode 100644 index 000000000000..019946822222 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 010000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e8ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e8ff.v.yaml new file mode 100644 index 000000000000..1e14babcaf72 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg3e8ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg3e8ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 010000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e16.v.yaml new file mode 100644 index 000000000000..ee5d268764d0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 011000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e16ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e16ff.v.yaml new file mode 100644 index 000000000000..9d0297cacb12 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e16ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e16ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 011000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e32.v.yaml new file mode 100644 index 000000000000..84b15d4cc6ca --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 011000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e32ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e32ff.v.yaml new file mode 100644 index 000000000000..645f55361414 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e32ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e32ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 011000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e64.v.yaml new file mode 100644 index 000000000000..907bf4799b96 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 011000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e64ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e64ff.v.yaml new file mode 100644 index 000000000000..5803a12e7ddb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e64ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e64ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 011000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e8.v.yaml new file mode 100644 index 000000000000..f29f7259f795 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 011000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e8ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e8ff.v.yaml new file mode 100644 index 000000000000..93e85b58553e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg4e8ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg4e8ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 011000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e16.v.yaml new file mode 100644 index 000000000000..fa3826ea16c9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 100000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e16ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e16ff.v.yaml new file mode 100644 index 000000000000..53759cce2fe0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e16ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e16ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 100000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e32.v.yaml new file mode 100644 index 000000000000..eb3e0b4d4b82 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 100000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e32ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e32ff.v.yaml new file mode 100644 index 000000000000..6bb33fe1a7f5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e32ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e32ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 100000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e64.v.yaml new file mode 100644 index 000000000000..8d2b9175a1c5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 100000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e64ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e64ff.v.yaml new file mode 100644 index 000000000000..dea413b063b8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e64ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e64ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 100000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e8.v.yaml new file mode 100644 index 000000000000..5d0173fccc2d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 100000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e8ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e8ff.v.yaml new file mode 100644 index 000000000000..5ca75c73dd57 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg5e8ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg5e8ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 100000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e16.v.yaml new file mode 100644 index 000000000000..a1d59d10b46b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 101000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e16ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e16ff.v.yaml new file mode 100644 index 000000000000..78cd500f7b0b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e16ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e16ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 101000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e32.v.yaml new file mode 100644 index 000000000000..6ba4fbdb576a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 101000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e32ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e32ff.v.yaml new file mode 100644 index 000000000000..865c200a7cda --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e32ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e32ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 101000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e64.v.yaml new file mode 100644 index 000000000000..44f50f3ae13e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 101000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e64ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e64ff.v.yaml new file mode 100644 index 000000000000..c340b7ea30e9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e64ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e64ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 101000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e8.v.yaml new file mode 100644 index 000000000000..ce97b636630b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 101000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e8ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e8ff.v.yaml new file mode 100644 index 000000000000..6f6217cf8f1d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg6e8ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg6e8ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 101000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e16.v.yaml new file mode 100644 index 000000000000..ce6ca238bdcd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 110000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e16ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e16ff.v.yaml new file mode 100644 index 000000000000..3a986107efae --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e16ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e16ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 110000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e32.v.yaml new file mode 100644 index 000000000000..2d0f78f302f2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 110000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e32ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e32ff.v.yaml new file mode 100644 index 000000000000..79b8e6931c5b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e32ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e32ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 110000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e64.v.yaml new file mode 100644 index 000000000000..dec9d06a7f53 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 110000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e64ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e64ff.v.yaml new file mode 100644 index 000000000000..b986afece279 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e64ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e64ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 110000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e8.v.yaml new file mode 100644 index 000000000000..14f23094a217 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 110000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e8ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e8ff.v.yaml new file mode 100644 index 000000000000..b5c581ff5bd8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg7e8ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg7e8ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 110000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e16.v.yaml new file mode 100644 index 000000000000..c19b2acfc6ac --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 111000-00000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e16ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e16ff.v.yaml new file mode 100644 index 000000000000..0b60634a7e7a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e16ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e16ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 111000-10000-----101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e32.v.yaml new file mode 100644 index 000000000000..6c15f740bac1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 111000-00000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e32ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e32ff.v.yaml new file mode 100644 index 000000000000..b4f336cd6aa9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e32ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e32ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 111000-10000-----110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e64.v.yaml new file mode 100644 index 000000000000..87d8a62cd3a4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 111000-00000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e64ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e64ff.v.yaml new file mode 100644 index 000000000000..7b83d6a2de12 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e64ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e64ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 111000-10000-----111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e8.v.yaml new file mode 100644 index 000000000000..a02bcf310d75 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 111000-00000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e8ff.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e8ff.v.yaml new file mode 100644 index 000000000000..bbd059e9e085 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlseg8e8ff.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlseg8e8ff.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vm +encoding: + match: 111000-10000-----000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e16.v.yaml new file mode 100644 index 000000000000..7a4cc2451161 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg2e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 001010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e32.v.yaml new file mode 100644 index 000000000000..3a00aba60ec2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg2e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 001010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e64.v.yaml new file mode 100644 index 000000000000..ab14de130eec --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg2e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 001010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e8.v.yaml new file mode 100644 index 000000000000..0d8a0e399b6d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg2e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg2e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 001010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e16.v.yaml new file mode 100644 index 000000000000..149edd0d7fd0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg3e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 010010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e32.v.yaml new file mode 100644 index 000000000000..19c70900cf62 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg3e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 010010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e64.v.yaml new file mode 100644 index 000000000000..d8c8e0fd32d2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg3e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 010010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e8.v.yaml new file mode 100644 index 000000000000..8da7c76db3f9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg3e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg3e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 010010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e16.v.yaml new file mode 100644 index 000000000000..d0fb232c2c6d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg4e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 011010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e32.v.yaml new file mode 100644 index 000000000000..b72056a43a16 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg4e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 011010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e64.v.yaml new file mode 100644 index 000000000000..5960084a0ce9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg4e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 011010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e8.v.yaml new file mode 100644 index 000000000000..1b1c3d362fbd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg4e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg4e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 011010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e16.v.yaml new file mode 100644 index 000000000000..ccf8a2388d08 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg5e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 100010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e32.v.yaml new file mode 100644 index 000000000000..1605dd5d58f7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg5e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 100010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e64.v.yaml new file mode 100644 index 000000000000..c896adbd693f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg5e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 100010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e8.v.yaml new file mode 100644 index 000000000000..6c18a1014773 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg5e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg5e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 100010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e16.v.yaml new file mode 100644 index 000000000000..2b3de7231194 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg6e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 101010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e32.v.yaml new file mode 100644 index 000000000000..4b0a69e9081f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg6e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 101010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e64.v.yaml new file mode 100644 index 000000000000..8d12ac318140 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg6e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 101010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e8.v.yaml new file mode 100644 index 000000000000..fd18bfb0c14d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg6e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg6e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 101010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e16.v.yaml new file mode 100644 index 000000000000..6de6d2033948 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg7e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 110010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e32.v.yaml new file mode 100644 index 000000000000..1c45d9d48a60 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg7e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 110010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e64.v.yaml new file mode 100644 index 000000000000..12f56b2aa93d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg7e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 110010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e8.v.yaml new file mode 100644 index 000000000000..a68266a010a6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg7e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg7e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 110010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e16.v.yaml new file mode 100644 index 000000000000..2e9491116de0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg8e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 111010-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e32.v.yaml new file mode 100644 index 000000000000..5bd855c12446 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg8e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 111010-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e64.v.yaml new file mode 100644 index 000000000000..35ccc9804c5d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg8e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 111010-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e8.v.yaml new file mode 100644 index 000000000000..6a762a92c95c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vlsseg8e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vlsseg8e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), xs2, vm +encoding: + match: 111010-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxei16.v.yaml new file mode 100644 index 000000000000..0a35b69d2b50 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxei16.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vluxei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 000001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); + let nf_int = nfields_int(nf); + + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxei32.v.yaml new file mode 100644 index 000000000000..362b1f5507ea --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxei32.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vluxei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 000001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); + let nf_int = nfields_int(nf); + + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxei64.v.yaml new file mode 100644 index 000000000000..8e562446b03f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxei64.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vluxei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 000001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); + let nf_int = nfields_int(nf); + + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxei8.v.yaml new file mode 100644 index 000000000000..b49bbd357591 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxei8.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vluxei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 000001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); + let nf_int = nfields_int(nf); + + if illegal_indexed_load(vd, vm, nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vlxseg(nf_int, vm, vd, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei16.v.yaml new file mode 100644 index 000000000000..caa2c6faef9c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg2ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 001001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei32.v.yaml new file mode 100644 index 000000000000..56238c550504 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg2ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 001001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei64.v.yaml new file mode 100644 index 000000000000..da05330d9bcc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg2ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 001001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei8.v.yaml new file mode 100644 index 000000000000..9ec87469a838 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg2ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg2ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 001001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei16.v.yaml new file mode 100644 index 000000000000..bae8a80fda21 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg3ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 010001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei32.v.yaml new file mode 100644 index 000000000000..cbaef53f295b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg3ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 010001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei64.v.yaml new file mode 100644 index 000000000000..c7d76eeb7714 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg3ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 010001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei8.v.yaml new file mode 100644 index 000000000000..34b7bfdec92a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg3ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg3ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 010001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei16.v.yaml new file mode 100644 index 000000000000..2043a4812c09 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg4ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 011001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei32.v.yaml new file mode 100644 index 000000000000..af545d85f9ad --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg4ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 011001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei64.v.yaml new file mode 100644 index 000000000000..cf5c8cf68266 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg4ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 011001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei8.v.yaml new file mode 100644 index 000000000000..f13713f2342c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg4ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg4ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 011001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei16.v.yaml new file mode 100644 index 000000000000..48d6a449c37d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg5ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 100001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei32.v.yaml new file mode 100644 index 000000000000..836aa896072d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg5ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 100001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei64.v.yaml new file mode 100644 index 000000000000..675f38f4400f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg5ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 100001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei8.v.yaml new file mode 100644 index 000000000000..a1ae0a97e638 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg5ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg5ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 100001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei16.v.yaml new file mode 100644 index 000000000000..8d01adf10aeb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg6ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 101001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei32.v.yaml new file mode 100644 index 000000000000..f3a8fd717b00 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg6ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 101001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei64.v.yaml new file mode 100644 index 000000000000..2661bbef1df3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg6ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 101001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei8.v.yaml new file mode 100644 index 000000000000..3b9e85876c14 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg6ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg6ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 101001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei16.v.yaml new file mode 100644 index 000000000000..ccc6e8e73f99 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg7ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 110001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei32.v.yaml new file mode 100644 index 000000000000..940d1dd7ec4c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg7ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 110001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei64.v.yaml new file mode 100644 index 000000000000..039dc05237a7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg7ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 110001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei8.v.yaml new file mode 100644 index 000000000000..62a5cc231ead --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg7ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg7ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 110001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei16.v.yaml new file mode 100644 index 000000000000..ff211d56ddc1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg8ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 111001-----------101-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei32.v.yaml new file mode 100644 index 000000000000..c56e421ec326 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg8ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 111001-----------110-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei64.v.yaml new file mode 100644 index 000000000000..6f453a044ace --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg8ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 111001-----------111-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei8.v.yaml new file mode 100644 index 000000000000..a4ac8ad5bf18 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vluxseg8ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vluxseg8ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, (xs1), vs2, vm +encoding: + match: 111001-----------000-----0000111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmacc.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmacc.vv.yaml new file mode 100644 index 000000000000..88b5ce43992e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmacc.vv.yaml @@ -0,0 +1,74 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmacc.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101101-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VMACC => get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0) + vd_val[i], + MVV_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0), + MVV_VMADD => get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0) + vs2_val[i], + MVV_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmacc.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmacc.vx.yaml new file mode 100644 index 000000000000..b4291054ab24 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmacc.vx.yaml @@ -0,0 +1,74 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmacc.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, xs1, vs2, vm +encoding: + match: 101101-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VMACC => get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0) + vd_val[i], + MVX_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0), + MVX_VMADD => get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0) + vs2_val[i], + MVX_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vi.yaml new file mode 100644 index 000000000000..e9c8877f63ed --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vi.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmadc.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm +encoding: + match: 0100011----------011-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VIMC_VMADC => unsigned(vs2_val[i]) + unsigned(imm_val) > 2 ^ SEW - 1 + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vim.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vim.yaml new file mode 100644 index 000000000000..d3c899059021 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vim.yaml @@ -0,0 +1,70 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmadc.vim +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, v0 +encoding: + match: 0100010----------011-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VIM_VMADC => unsigned(vs2_val[i]) + unsigned(imm_val) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1 + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vv.yaml new file mode 100644 index 000000000000..8484a878a040 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vv.yaml @@ -0,0 +1,70 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmadc.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0100011----------000-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VVMC_VMADC => unsigned(vs2_val[i]) + unsigned(vs1_val[i]) > 2 ^ SEW - 1, + VVMC_VMSBC => unsigned(vs2_val[i]) - unsigned(vs1_val[i]) < 0 + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vvm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vvm.yaml new file mode 100644 index 000000000000..9357c7a9f71f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vvm.yaml @@ -0,0 +1,71 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmadc.vvm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, v0 +encoding: + match: 0100010----------000-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VVM_VMADC => unsigned(vs2_val[i]) + unsigned(vs1_val[i]) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1, + VVM_VMSBC => unsigned(vs2_val[i]) - unsigned(vs1_val[i]) - unsigned(bool_to_bits(vm_val[i])) < 0 + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vx.yaml new file mode 100644 index 000000000000..c2074b2ffbd8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vx.yaml @@ -0,0 +1,70 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmadc.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1 +encoding: + match: 0100011----------100-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXMC_VMADC => unsigned(vs2_val[i]) + unsigned(rs1_val) > 2 ^ SEW - 1, + VXMC_VMSBC => unsigned(vs2_val[i]) - unsigned(rs1_val) < 0 + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vxm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vxm.yaml new file mode 100644 index 000000000000..a1a9ab9ddbd1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmadc.vxm.yaml @@ -0,0 +1,71 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmadc.vxm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, v0 +encoding: + match: 0100010----------100-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXM_VMADC => unsigned(vs2_val[i]) + unsigned(rs1_val) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1, + VXM_VMSBC => unsigned(vs2_val[i]) - unsigned(rs1_val) - unsigned(bool_to_bits(vm_val[i])) < 0 + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmadd.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmadd.vv.yaml new file mode 100644 index 000000000000..9279393af4ce --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmadd.vv.yaml @@ -0,0 +1,74 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmadd.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101001-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VMACC => get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0) + vd_val[i], + MVV_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0), + MVV_VMADD => get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0) + vs2_val[i], + MVV_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmadd.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmadd.vx.yaml new file mode 100644 index 000000000000..e3346d33b6d8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmadd.vx.yaml @@ -0,0 +1,74 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmadd.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, xs1, vs2, vm +encoding: + match: 101001-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VMACC => get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0) + vd_val[i], + MVX_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0), + MVX_VMADD => get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0) + vs2_val[i], + MVX_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmand.mm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmand.mm.yaml new file mode 100644 index 000000000000..57b397addd19 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmand.mm.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmand.mm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0110011----------010-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = unsigned(vlenb) * 8; + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MM_VMAND => vs2_val[i] & vs1_val[i], + MM_VMNAND => not(vs2_val[i] & vs1_val[i]), + MM_VMANDNOT => vs2_val[i] & not(vs1_val[i]), + MM_VMXOR => vs2_val[i] != vs1_val[i], + MM_VMOR => vs2_val[i] | vs1_val[i], + MM_VMNOR => not(vs2_val[i] | vs1_val[i]), + MM_VMORNOT => vs2_val[i] | not(vs1_val[i]), + MM_VMXNOR => vs2_val[i] == vs1_val[i] + } + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmandn.mm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmandn.mm.yaml new file mode 100644 index 000000000000..8e338e2ec54e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmandn.mm.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmandn.mm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0110001----------010-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmax.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmax.vv.yaml new file mode 100644 index 000000000000..c74e6001443a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmax.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmax.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000111-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmax.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmax.vx.yaml new file mode 100644 index 000000000000..62768d4d6fe0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmax.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmax.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 000111-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmaxu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmaxu.vv.yaml new file mode 100644 index 000000000000..ba52439e8962 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmaxu.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmaxu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000110-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmaxu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmaxu.vx.yaml new file mode 100644 index 000000000000..f800a36da5cd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmaxu.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmaxu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 000110-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmerge.vim.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmerge.vim.yaml new file mode 100644 index 000000000000..886e703b2acf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmerge.vim.yaml @@ -0,0 +1,76 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmerge.vim +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, v0 +encoding: + match: 0101110----------011-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let start_element = get_start_element(); + let end_element = get_end_element(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ + let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ + + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + + let tail_ag : agtype = get_vtype_vta(); + foreach (i from 0 to (num_elem - 1)) { + if i < start_element then { + result[i] = vd_val[i] + } else if i > end_element | i >= real_num_elem then { + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ + } + } else { + /* the merge operates on all body elements */ + result[i] = if vm_val[i] then imm_val else vs2_val[i] + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmerge.vvm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmerge.vvm.yaml new file mode 100644 index 000000000000..c057e844701b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmerge.vvm.yaml @@ -0,0 +1,76 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmerge.vvm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, v0 +encoding: + match: 0101110----------000-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let start_element = get_start_element(); + let end_element = get_end_element(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ + let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ + + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + + let tail_ag : agtype = get_vtype_vta(); + foreach (i from 0 to (num_elem - 1)) { + if i < start_element then { + result[i] = vd_val[i] + } else if i > end_element | i >= real_num_elem then { + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ + } + } else { + /* the merge operates on all body elements */ + result[i] = if vm_val[i] then vs1_val[i] else vs2_val[i] + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmerge.vxm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmerge.vxm.yaml new file mode 100644 index 000000000000..f97e4d046eb7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmerge.vxm.yaml @@ -0,0 +1,76 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmerge.vxm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, v0 +encoding: + match: 0101110----------100-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let start_element = get_start_element(); + let end_element = get_end_element(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); /* max(VLMAX,VLEN/SEW)) */ + let real_num_elem = if LMUL_pow >= 0 then num_elem else num_elem / (0 - LMUL_pow); /* VLMAX */ + + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + + let tail_ag : agtype = get_vtype_vta(); + foreach (i from 0 to (num_elem - 1)) { + if i < start_element then { + result[i] = vd_val[i] + } else if i > end_element | i >= real_num_elem then { + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ + } + } else { + /* the merge operates on all body elements */ + result[i] = if vm_val[i] then rs1_val else vs2_val[i] + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmfeq.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmfeq.vf.yaml new file mode 100644 index 000000000000..122c964c2330 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmfeq.vf.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmfeq.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 011000-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VFM_VMFEQ => fp_eq(vs2_val[i], rs1_val), + VFM_VMFNE => ~(fp_eq(vs2_val[i], rs1_val)), + VFM_VMFLE => fp_le(vs2_val[i], rs1_val), + VFM_VMFLT => fp_lt(vs2_val[i], rs1_val), + VFM_VMFGE => fp_ge(vs2_val[i], rs1_val), + VFM_VMFGT => fp_gt(vs2_val[i], rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmfeq.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmfeq.vv.yaml new file mode 100644 index 000000000000..09001e3c83dd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmfeq.vv.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmfeq.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 011000-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + FVVM_VMFEQ => fp_eq(vs2_val[i], vs1_val[i]), + FVVM_VMFNE => ~(fp_eq(vs2_val[i], vs1_val[i])), + FVVM_VMFLE => fp_le(vs2_val[i], vs1_val[i]), + FVVM_VMFLT => fp_lt(vs2_val[i], vs1_val[i]) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmfge.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmfge.vf.yaml new file mode 100644 index 000000000000..ff24ef498fd2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmfge.vf.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmfge.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 011111-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VFM_VMFEQ => fp_eq(vs2_val[i], rs1_val), + VFM_VMFNE => ~(fp_eq(vs2_val[i], rs1_val)), + VFM_VMFLE => fp_le(vs2_val[i], rs1_val), + VFM_VMFLT => fp_lt(vs2_val[i], rs1_val), + VFM_VMFGE => fp_ge(vs2_val[i], rs1_val), + VFM_VMFGT => fp_gt(vs2_val[i], rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmfgt.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmfgt.vf.yaml new file mode 100644 index 000000000000..b3faebc1c13c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmfgt.vf.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmfgt.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 011101-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VFM_VMFEQ => fp_eq(vs2_val[i], rs1_val), + VFM_VMFNE => ~(fp_eq(vs2_val[i], rs1_val)), + VFM_VMFLE => fp_le(vs2_val[i], rs1_val), + VFM_VMFLT => fp_lt(vs2_val[i], rs1_val), + VFM_VMFGE => fp_ge(vs2_val[i], rs1_val), + VFM_VMFGT => fp_gt(vs2_val[i], rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmfle.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmfle.vf.yaml new file mode 100644 index 000000000000..1cb1fb3b5d35 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmfle.vf.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmfle.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 011001-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VFM_VMFEQ => fp_eq(vs2_val[i], rs1_val), + VFM_VMFNE => ~(fp_eq(vs2_val[i], rs1_val)), + VFM_VMFLE => fp_le(vs2_val[i], rs1_val), + VFM_VMFLT => fp_lt(vs2_val[i], rs1_val), + VFM_VMFGE => fp_ge(vs2_val[i], rs1_val), + VFM_VMFGT => fp_gt(vs2_val[i], rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmfle.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmfle.vv.yaml new file mode 100644 index 000000000000..db6f014e2d2f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmfle.vv.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmfle.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 011001-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + FVVM_VMFEQ => fp_eq(vs2_val[i], vs1_val[i]), + FVVM_VMFNE => ~(fp_eq(vs2_val[i], vs1_val[i])), + FVVM_VMFLE => fp_le(vs2_val[i], vs1_val[i]), + FVVM_VMFLT => fp_lt(vs2_val[i], vs1_val[i]) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmflt.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmflt.vf.yaml new file mode 100644 index 000000000000..8dae5ece151c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmflt.vf.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmflt.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 011011-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VFM_VMFEQ => fp_eq(vs2_val[i], rs1_val), + VFM_VMFNE => ~(fp_eq(vs2_val[i], rs1_val)), + VFM_VMFLE => fp_le(vs2_val[i], rs1_val), + VFM_VMFLT => fp_lt(vs2_val[i], rs1_val), + VFM_VMFGE => fp_ge(vs2_val[i], rs1_val), + VFM_VMFGT => fp_gt(vs2_val[i], rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmflt.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmflt.vv.yaml new file mode 100644 index 000000000000..ebc23a47b8e5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmflt.vv.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmflt.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 011011-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + FVVM_VMFEQ => fp_eq(vs2_val[i], vs1_val[i]), + FVVM_VMFNE => ~(fp_eq(vs2_val[i], vs1_val[i])), + FVVM_VMFLE => fp_le(vs2_val[i], vs1_val[i]), + FVVM_VMFLT => fp_lt(vs2_val[i], vs1_val[i]) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmfne.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmfne.vf.yaml new file mode 100644 index 000000000000..e8bdf20f42f0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmfne.vf.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmfne.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, fs1, vm +encoding: + match: 011100-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar_fp(rs1, 'm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VFM_VMFEQ => fp_eq(vs2_val[i], rs1_val), + VFM_VMFNE => ~(fp_eq(vs2_val[i], rs1_val)), + VFM_VMFLE => fp_le(vs2_val[i], rs1_val), + VFM_VMFLT => fp_lt(vs2_val[i], rs1_val), + VFM_VMFGE => fp_ge(vs2_val[i], rs1_val), + VFM_VMFGT => fp_gt(vs2_val[i], rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmfne.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmfne.vv.yaml new file mode 100644 index 000000000000..97a21aed9976 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmfne.vv.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmfne.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 011100-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rm_3b = fcsr.FRM(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_fp_vd_unmasked(SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL }; + assert(SEW != 8); + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + FVVM_VMFEQ => fp_eq(vs2_val[i], vs1_val[i]), + FVVM_VMFNE => ~(fp_eq(vs2_val[i], vs1_val[i])), + FVVM_VMFLE => fp_le(vs2_val[i], vs1_val[i]), + FVVM_VMFLT => fp_lt(vs2_val[i], vs1_val[i]) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmin.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmin.vv.yaml new file mode 100644 index 000000000000..5c5cd72166d5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmin.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmin.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000101-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmin.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmin.vx.yaml new file mode 100644 index 000000000000..12e528bf1731 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmin.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmin.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 000101-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vminu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vminu.vv.yaml new file mode 100644 index 000000000000..d4e0cfae1d80 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vminu.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vminu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000100-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vminu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vminu.vx.yaml new file mode 100644 index 000000000000..e4145670ec0b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vminu.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vminu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 000100-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmnand.mm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmnand.mm.yaml new file mode 100644 index 000000000000..6bf7c42c7aac --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmnand.mm.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmnand.mm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0111011----------010-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = unsigned(vlenb) * 8; + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MM_VMAND => vs2_val[i] & vs1_val[i], + MM_VMNAND => not(vs2_val[i] & vs1_val[i]), + MM_VMANDNOT => vs2_val[i] & not(vs1_val[i]), + MM_VMXOR => vs2_val[i] != vs1_val[i], + MM_VMOR => vs2_val[i] | vs1_val[i], + MM_VMNOR => not(vs2_val[i] | vs1_val[i]), + MM_VMORNOT => vs2_val[i] | not(vs1_val[i]), + MM_VMXNOR => vs2_val[i] == vs1_val[i] + } + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmnor.mm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmnor.mm.yaml new file mode 100644 index 000000000000..83634004fdd2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmnor.mm.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmnor.mm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0111101----------010-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = unsigned(vlenb) * 8; + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MM_VMAND => vs2_val[i] & vs1_val[i], + MM_VMNAND => not(vs2_val[i] & vs1_val[i]), + MM_VMANDNOT => vs2_val[i] & not(vs1_val[i]), + MM_VMXOR => vs2_val[i] != vs1_val[i], + MM_VMOR => vs2_val[i] | vs1_val[i], + MM_VMNOR => not(vs2_val[i] | vs1_val[i]), + MM_VMORNOT => vs2_val[i] | not(vs1_val[i]), + MM_VMXNOR => vs2_val[i] == vs1_val[i] + } + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmor.mm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmor.mm.yaml new file mode 100644 index 000000000000..c94cd7f83d21 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmor.mm.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmor.mm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0110101----------010-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = unsigned(vlenb) * 8; + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MM_VMAND => vs2_val[i] & vs1_val[i], + MM_VMNAND => not(vs2_val[i] & vs1_val[i]), + MM_VMANDNOT => vs2_val[i] & not(vs1_val[i]), + MM_VMXOR => vs2_val[i] != vs1_val[i], + MM_VMOR => vs2_val[i] | vs1_val[i], + MM_VMNOR => not(vs2_val[i] | vs1_val[i]), + MM_VMORNOT => vs2_val[i] | not(vs1_val[i]), + MM_VMXNOR => vs2_val[i] == vs1_val[i] + } + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmorn.mm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmorn.mm.yaml new file mode 100644 index 000000000000..42050aea761d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmorn.mm.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmorn.mm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0111001----------010-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vv.yaml new file mode 100644 index 000000000000..e2c5466b554a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vv.yaml @@ -0,0 +1,70 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsbc.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0100111----------000-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VVMC_VMADC => unsigned(vs2_val[i]) + unsigned(vs1_val[i]) > 2 ^ SEW - 1, + VVMC_VMSBC => unsigned(vs2_val[i]) - unsigned(vs1_val[i]) < 0 + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vvm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vvm.yaml new file mode 100644 index 000000000000..ed5c4abaccc8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vvm.yaml @@ -0,0 +1,71 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsbc.vvm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, v0 +encoding: + match: 0100110----------000-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VVM_VMADC => unsigned(vs2_val[i]) + unsigned(vs1_val[i]) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1, + VVM_VMSBC => unsigned(vs2_val[i]) - unsigned(vs1_val[i]) - unsigned(bool_to_bits(vm_val[i])) < 0 + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vx.yaml new file mode 100644 index 000000000000..e03cec896446 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vx.yaml @@ -0,0 +1,70 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsbc.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1 +encoding: + match: 0100111----------100-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXMC_VMADC => unsigned(vs2_val[i]) + unsigned(rs1_val) > 2 ^ SEW - 1, + VXMC_VMSBC => unsigned(vs2_val[i]) - unsigned(rs1_val) < 0 + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vxm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vxm.yaml new file mode 100644 index 000000000000..467ba270bd6f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsbc.vxm.yaml @@ -0,0 +1,71 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsbc.vxm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, v0 +encoding: + match: 0100110----------100-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, LMUL_pow, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXM_VMADC => unsigned(vs2_val[i]) + unsigned(rs1_val) + unsigned(bool_to_bits(vm_val[i])) > 2 ^ SEW - 1, + VXM_VMSBC => unsigned(vs2_val[i]) - unsigned(rs1_val) - unsigned(bool_to_bits(vm_val[i])) < 0 + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsbf.m.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsbf.m.yaml new file mode 100644 index 000000000000..4e21912769e2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsbf.m.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsbf.m +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010100------00001010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = unsigned(vlenb) * 8; + + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val); + + found_elem : bool = false; + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + if vs2_val[i] then found_elem = true; + result[i] = if found_elem then false else true + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmseq.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmseq.vi.yaml new file mode 100644 index 000000000000..bc6a77dbf737 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmseq.vi.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmseq.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 011000-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VICMP_VMSEQ => vs2_val[i] == imm_val, + VICMP_VMSNE => vs2_val[i] != imm_val, + VICMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(imm_val), + VICMP_VMSLE => signed(vs2_val[i]) <= signed(imm_val), + VICMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(imm_val), + VICMP_VMSGT => signed(vs2_val[i]) > signed(imm_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmseq.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmseq.vv.yaml new file mode 100644 index 000000000000..199b3667656d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmseq.vv.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmseq.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 011000-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VVCMP_VMSEQ => vs2_val[i] == vs1_val[i], + VVCMP_VMSNE => vs2_val[i] != vs1_val[i], + VVCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(vs1_val[i]), + VVCMP_VMSLT => signed(vs2_val[i]) < signed(vs1_val[i]), + VVCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]), + VVCMP_VMSLE => signed(vs2_val[i]) <= signed(vs1_val[i]) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmseq.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmseq.vx.yaml new file mode 100644 index 000000000000..1e9de9742388 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmseq.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmseq.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 011000-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXCMP_VMSEQ => vs2_val[i] == rs1_val, + VXCMP_VMSNE => vs2_val[i] != rs1_val, + VXCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(rs1_val), + VXCMP_VMSLT => signed(vs2_val[i]) < signed(rs1_val), + VXCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(rs1_val), + VXCMP_VMSLE => signed(vs2_val[i]) <= signed(rs1_val), + VXCMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(rs1_val), + VXCMP_VMSGT => signed(vs2_val[i]) > signed(rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsgt.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsgt.vi.yaml new file mode 100644 index 000000000000..bc9a8a31edb0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsgt.vi.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsgt.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 011111-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VICMP_VMSEQ => vs2_val[i] == imm_val, + VICMP_VMSNE => vs2_val[i] != imm_val, + VICMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(imm_val), + VICMP_VMSLE => signed(vs2_val[i]) <= signed(imm_val), + VICMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(imm_val), + VICMP_VMSGT => signed(vs2_val[i]) > signed(imm_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsgt.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsgt.vx.yaml new file mode 100644 index 000000000000..0056485182cd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsgt.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsgt.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 011111-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXCMP_VMSEQ => vs2_val[i] == rs1_val, + VXCMP_VMSNE => vs2_val[i] != rs1_val, + VXCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(rs1_val), + VXCMP_VMSLT => signed(vs2_val[i]) < signed(rs1_val), + VXCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(rs1_val), + VXCMP_VMSLE => signed(vs2_val[i]) <= signed(rs1_val), + VXCMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(rs1_val), + VXCMP_VMSGT => signed(vs2_val[i]) > signed(rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsgtu.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsgtu.vi.yaml new file mode 100644 index 000000000000..fd7c8e949260 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsgtu.vi.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsgtu.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 011110-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VICMP_VMSEQ => vs2_val[i] == imm_val, + VICMP_VMSNE => vs2_val[i] != imm_val, + VICMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(imm_val), + VICMP_VMSLE => signed(vs2_val[i]) <= signed(imm_val), + VICMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(imm_val), + VICMP_VMSGT => signed(vs2_val[i]) > signed(imm_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsgtu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsgtu.vx.yaml new file mode 100644 index 000000000000..238ae044b4f7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsgtu.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsgtu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 011110-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXCMP_VMSEQ => vs2_val[i] == rs1_val, + VXCMP_VMSNE => vs2_val[i] != rs1_val, + VXCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(rs1_val), + VXCMP_VMSLT => signed(vs2_val[i]) < signed(rs1_val), + VXCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(rs1_val), + VXCMP_VMSLE => signed(vs2_val[i]) <= signed(rs1_val), + VXCMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(rs1_val), + VXCMP_VMSGT => signed(vs2_val[i]) > signed(rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsif.m.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsif.m.yaml new file mode 100644 index 000000000000..a122f970a334 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsif.m.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsif.m +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010100------00011010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = unsigned(vlenb) * 8; + + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val); + + found_elem : bool = false; + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = if found_elem then false else true; + if vs2_val[i] then found_elem = true + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsle.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsle.vi.yaml new file mode 100644 index 000000000000..7a797d21afbc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsle.vi.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsle.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 011101-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VICMP_VMSEQ => vs2_val[i] == imm_val, + VICMP_VMSNE => vs2_val[i] != imm_val, + VICMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(imm_val), + VICMP_VMSLE => signed(vs2_val[i]) <= signed(imm_val), + VICMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(imm_val), + VICMP_VMSGT => signed(vs2_val[i]) > signed(imm_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsle.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsle.vv.yaml new file mode 100644 index 000000000000..ab03adc5a846 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsle.vv.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsle.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 011101-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VVCMP_VMSEQ => vs2_val[i] == vs1_val[i], + VVCMP_VMSNE => vs2_val[i] != vs1_val[i], + VVCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(vs1_val[i]), + VVCMP_VMSLT => signed(vs2_val[i]) < signed(vs1_val[i]), + VVCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]), + VVCMP_VMSLE => signed(vs2_val[i]) <= signed(vs1_val[i]) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsle.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsle.vx.yaml new file mode 100644 index 000000000000..fe2f4ccb63c3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsle.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsle.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 011101-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXCMP_VMSEQ => vs2_val[i] == rs1_val, + VXCMP_VMSNE => vs2_val[i] != rs1_val, + VXCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(rs1_val), + VXCMP_VMSLT => signed(vs2_val[i]) < signed(rs1_val), + VXCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(rs1_val), + VXCMP_VMSLE => signed(vs2_val[i]) <= signed(rs1_val), + VXCMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(rs1_val), + VXCMP_VMSGT => signed(vs2_val[i]) > signed(rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsleu.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsleu.vi.yaml new file mode 100644 index 000000000000..475e7d23ccde --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsleu.vi.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsleu.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 011100-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VICMP_VMSEQ => vs2_val[i] == imm_val, + VICMP_VMSNE => vs2_val[i] != imm_val, + VICMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(imm_val), + VICMP_VMSLE => signed(vs2_val[i]) <= signed(imm_val), + VICMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(imm_val), + VICMP_VMSGT => signed(vs2_val[i]) > signed(imm_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsleu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsleu.vv.yaml new file mode 100644 index 000000000000..ad30a1c9d144 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsleu.vv.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsleu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 011100-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VVCMP_VMSEQ => vs2_val[i] == vs1_val[i], + VVCMP_VMSNE => vs2_val[i] != vs1_val[i], + VVCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(vs1_val[i]), + VVCMP_VMSLT => signed(vs2_val[i]) < signed(vs1_val[i]), + VVCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]), + VVCMP_VMSLE => signed(vs2_val[i]) <= signed(vs1_val[i]) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsleu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsleu.vx.yaml new file mode 100644 index 000000000000..619ae698bed6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsleu.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsleu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 011100-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXCMP_VMSEQ => vs2_val[i] == rs1_val, + VXCMP_VMSNE => vs2_val[i] != rs1_val, + VXCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(rs1_val), + VXCMP_VMSLT => signed(vs2_val[i]) < signed(rs1_val), + VXCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(rs1_val), + VXCMP_VMSLE => signed(vs2_val[i]) <= signed(rs1_val), + VXCMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(rs1_val), + VXCMP_VMSGT => signed(vs2_val[i]) > signed(rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmslt.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmslt.vv.yaml new file mode 100644 index 000000000000..96111c9dcd81 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmslt.vv.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmslt.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 011011-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VVCMP_VMSEQ => vs2_val[i] == vs1_val[i], + VVCMP_VMSNE => vs2_val[i] != vs1_val[i], + VVCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(vs1_val[i]), + VVCMP_VMSLT => signed(vs2_val[i]) < signed(vs1_val[i]), + VVCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]), + VVCMP_VMSLE => signed(vs2_val[i]) <= signed(vs1_val[i]) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmslt.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmslt.vx.yaml new file mode 100644 index 000000000000..57276a1514b9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmslt.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmslt.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 011011-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXCMP_VMSEQ => vs2_val[i] == rs1_val, + VXCMP_VMSNE => vs2_val[i] != rs1_val, + VXCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(rs1_val), + VXCMP_VMSLT => signed(vs2_val[i]) < signed(rs1_val), + VXCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(rs1_val), + VXCMP_VMSLE => signed(vs2_val[i]) <= signed(rs1_val), + VXCMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(rs1_val), + VXCMP_VMSGT => signed(vs2_val[i]) > signed(rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsltu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsltu.vv.yaml new file mode 100644 index 000000000000..bcf14681bd25 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsltu.vv.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsltu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 011010-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VVCMP_VMSEQ => vs2_val[i] == vs1_val[i], + VVCMP_VMSNE => vs2_val[i] != vs1_val[i], + VVCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(vs1_val[i]), + VVCMP_VMSLT => signed(vs2_val[i]) < signed(vs1_val[i]), + VVCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]), + VVCMP_VMSLE => signed(vs2_val[i]) <= signed(vs1_val[i]) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsltu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsltu.vx.yaml new file mode 100644 index 000000000000..223521d5765b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsltu.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsltu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 011010-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXCMP_VMSEQ => vs2_val[i] == rs1_val, + VXCMP_VMSNE => vs2_val[i] != rs1_val, + VXCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(rs1_val), + VXCMP_VMSLT => signed(vs2_val[i]) < signed(rs1_val), + VXCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(rs1_val), + VXCMP_VMSLE => signed(vs2_val[i]) <= signed(rs1_val), + VXCMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(rs1_val), + VXCMP_VMSGT => signed(vs2_val[i]) > signed(rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsne.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsne.vi.yaml new file mode 100644 index 000000000000..daf0c3efd2ac --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsne.vi.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsne.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 011001-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VICMP_VMSEQ => vs2_val[i] == imm_val, + VICMP_VMSNE => vs2_val[i] != imm_val, + VICMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(imm_val), + VICMP_VMSLE => signed(vs2_val[i]) <= signed(imm_val), + VICMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(imm_val), + VICMP_VMSGT => signed(vs2_val[i]) > signed(imm_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsne.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsne.vv.yaml new file mode 100644 index 000000000000..7d8ea9051004 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsne.vv.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsne.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 011001-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VVCMP_VMSEQ => vs2_val[i] == vs1_val[i], + VVCMP_VMSNE => vs2_val[i] != vs1_val[i], + VVCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(vs1_val[i]), + VVCMP_VMSLT => signed(vs2_val[i]) < signed(vs1_val[i]), + VVCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(vs1_val[i]), + VVCMP_VMSLE => signed(vs2_val[i]) <= signed(vs1_val[i]) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsne.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsne.vx.yaml new file mode 100644 index 000000000000..3ac01df91a05 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsne.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsne.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 011001-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let res : bool = match funct6 { + VXCMP_VMSEQ => vs2_val[i] == rs1_val, + VXCMP_VMSNE => vs2_val[i] != rs1_val, + VXCMP_VMSLTU => unsigned(vs2_val[i]) < unsigned(rs1_val), + VXCMP_VMSLT => signed(vs2_val[i]) < signed(rs1_val), + VXCMP_VMSLEU => unsigned(vs2_val[i]) <= unsigned(rs1_val), + VXCMP_VMSLE => signed(vs2_val[i]) <= signed(rs1_val), + VXCMP_VMSGTU => unsigned(vs2_val[i]) > unsigned(rs1_val), + VXCMP_VMSGT => signed(vs2_val[i]) > signed(rs1_val) + }; + result[i] = res + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmsof.m.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmsof.m.yaml new file mode 100644 index 000000000000..33c4e724fd77 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmsof.m.yaml @@ -0,0 +1,73 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmsof.m +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010100------00010010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = unsigned(vlenb) * 8; + + if illegal_normal(vd, vm) | not(assert_vstart(0)) | vd == vs2 + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_cmp(num_elem, SEW, 0, vd_val, vm_val); + + found_elem : bool = false; + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + if vs2_val[i] & not(found_elem) then { + result[i] = true; + found_elem = true + } else { + result[i] = false + } + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmul.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmul.vv.yaml new file mode 100644 index 000000000000..a302db571bb9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmul.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmul.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100101-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmul.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmul.vx.yaml new file mode 100644 index 000000000000..517ce0712665 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmul.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmul.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100101-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmulh.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmulh.vv.yaml new file mode 100644 index 000000000000..4acd8916997e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmulh.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmulh.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100111-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmulh.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmulh.vx.yaml new file mode 100644 index 000000000000..60d4572c8743 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmulh.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmulh.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100111-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmulhsu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmulhsu.vv.yaml new file mode 100644 index 000000000000..a4d480da1ccd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmulhsu.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmulhsu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100110-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmulhsu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmulhsu.vx.yaml new file mode 100644 index 000000000000..16bb241d178a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmulhsu.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmulhsu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100110-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmulhu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmulhu.vv.yaml new file mode 100644 index 000000000000..8da5f426d87b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmulhu.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmulhu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100100-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmulhu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmulhu.vx.yaml new file mode 100644 index 000000000000..b45f69533fe9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmulhu.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmulhu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100100-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmv.s.x.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmv.s.x.yaml new file mode 100644 index 000000000000..d4ee59a1e617 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmv.s.x.yaml @@ -0,0 +1,70 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmv.s.x +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, xs1 +encoding: + match: 010000100000-----110-----1010111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let num_elem = get_num_elem(0, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + assert(num_elem > 0); + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, 'm); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, 0, vd_val, vm_val); + + /* one body element */ + if mask[0] then result[0] = rs1_val; + + /* others treated as tail elements */ + let tail_ag : agtype = get_vtype_vta(); + foreach (i from 1 to (num_elem - 1)) { + result[i] = match tail_ag { + UNDISTURBED => vd_val[i], + AGNOSTIC => vd_val[i] /* TODO: configuration support */ + } + }; + + write_vreg(num_elem, SEW, 0, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmv.v.i.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmv.v.i.yaml new file mode 100644 index 000000000000..51f799f66ad9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmv.v.i.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmv.v.i +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, imm +encoding: + match: 010111100000-----011-----1010111 + variables: + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then result[i] = imm_val + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmv.v.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmv.v.v.yaml new file mode 100644 index 000000000000..99cc3c4a6429 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmv.v.v.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmv.v.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1 +encoding: + match: 010111100000-----000-----1010111 + variables: + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then result[i] = vs1_val[i] + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmv.v.x.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmv.v.x.yaml new file mode 100644 index 000000000000..1a66e8e0c0ed --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmv.v.x.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmv.v.x +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, xs1 +encoding: + match: 010111100000-----100-----1010111 + variables: + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let rs1_val : bits('m) = get_scalar(rs1, 'm); + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then result[i] = rs1_val + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmv.x.s.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmv.x.s.yaml new file mode 100644 index 000000000000..23bfc9aac799 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmv.x.s.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmv.x.s +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: xd, vs2 +encoding: + match: 0100001-----00000010-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let num_elem = get_num_elem(0, SEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + assert(num_elem > 0); + let 'n = num_elem; + let 'm = SEW; + + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, 0, vs2); + X(rd) = if sizeof(xlen) < SEW then slice(vs2_val[0], 0, sizeof(xlen)) + else if sizeof(xlen) > SEW then sign_extend(vs2_val[0]) + else vs2_val[0]; + vstart = zeros(); + + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmv1r.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmv1r.v.yaml new file mode 100644 index 000000000000..ba2e04ef5ebc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmv1r.v.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmv1r.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2 +encoding: + match: 1001111-----00000011-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let start_element = get_start_element(); + let SEW = get_sew(); + let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); + let EMUL = imm_val + 1; + + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; + + let EMUL_pow = log2(EMUL); + let num_elem = get_num_elem(EMUL_pow, SEW); + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + + foreach (i from 0 to (num_elem - 1)) { + result[i] = if i < start_element then vd_val[i] else vs2_val[i] + }; + + write_vreg(num_elem, SEW, EMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmv2r.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmv2r.v.yaml new file mode 100644 index 000000000000..1f3ad2b9d6c9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmv2r.v.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmv2r.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2 +encoding: + match: 1001111-----00001011-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let start_element = get_start_element(); + let SEW = get_sew(); + let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); + let EMUL = imm_val + 1; + + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; + + let EMUL_pow = log2(EMUL); + let num_elem = get_num_elem(EMUL_pow, SEW); + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + + foreach (i from 0 to (num_elem - 1)) { + result[i] = if i < start_element then vd_val[i] else vs2_val[i] + }; + + write_vreg(num_elem, SEW, EMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmv4r.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmv4r.v.yaml new file mode 100644 index 000000000000..01e331685775 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmv4r.v.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmv4r.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2 +encoding: + match: 1001111-----00011011-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let start_element = get_start_element(); + let SEW = get_sew(); + let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); + let EMUL = imm_val + 1; + + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; + + let EMUL_pow = log2(EMUL); + let num_elem = get_num_elem(EMUL_pow, SEW); + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + + foreach (i from 0 to (num_elem - 1)) { + result[i] = if i < start_element then vd_val[i] else vs2_val[i] + }; + + write_vreg(num_elem, SEW, EMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmv8r.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmv8r.v.yaml new file mode 100644 index 000000000000..04131f65c1b6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmv8r.v.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmv8r.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2 +encoding: + match: 1001111-----00111011-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let start_element = get_start_element(); + let SEW = get_sew(); + let imm_val = unsigned(zero_extend(sizeof(xlen), simm)); + let EMUL = imm_val + 1; + + if not(EMUL == 1 | EMUL == 2 | EMUL == 4 | EMUL == 8) then { handle_illegal(); return RETIRE_FAIL }; + + let EMUL_pow = log2(EMUL); + let num_elem = get_num_elem(EMUL_pow, SEW); + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, 0b1, 0b00000); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, EMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + + foreach (i from 0 to (num_elem - 1)) { + result[i] = if i < start_element then vd_val[i] else vs2_val[i] + }; + + write_vreg(num_elem, SEW, EMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmxnor.mm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmxnor.mm.yaml new file mode 100644 index 000000000000..deb8658277fc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmxnor.mm.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmxnor.mm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0111111----------010-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = unsigned(vlenb) * 8; + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MM_VMAND => vs2_val[i] & vs1_val[i], + MM_VMNAND => not(vs2_val[i] & vs1_val[i]), + MM_VMANDNOT => vs2_val[i] & not(vs1_val[i]), + MM_VMXOR => vs2_val[i] != vs1_val[i], + MM_VMOR => vs2_val[i] | vs1_val[i], + MM_VMNOR => not(vs2_val[i] | vs1_val[i]), + MM_VMORNOT => vs2_val[i] | not(vs1_val[i]), + MM_VMXNOR => vs2_val[i] == vs1_val[i] + } + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vmxor.mm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vmxor.mm.yaml new file mode 100644 index 000000000000..d2a3ace2e935 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vmxor.mm.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vmxor.mm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1 +encoding: + match: 0110111----------010-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = unsigned(vlenb) * 8; + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vs1_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs1); + let vs2_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vs2); + let vd_val : vector('n, dec, bool) = read_vmask(num_elem, 0b0, vd); + result : vector('n, dec, bool) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result_carry(num_elem, SEW, 0, vd_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MM_VMAND => vs2_val[i] & vs1_val[i], + MM_VMNAND => not(vs2_val[i] & vs1_val[i]), + MM_VMANDNOT => vs2_val[i] & not(vs1_val[i]), + MM_VMXOR => vs2_val[i] != vs1_val[i], + MM_VMOR => vs2_val[i] | vs1_val[i], + MM_VMNOR => not(vs2_val[i] | vs1_val[i]), + MM_VMORNOT => vs2_val[i] | not(vs1_val[i]), + MM_VMXNOR => vs2_val[i] == vs1_val[i] + } + } + }; + + write_vmask(num_elem, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnclip.wi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnclip.wi.yaml new file mode 100644 index 000000000000..2a95b0917b25 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnclip.wi.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnclip.wi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 101111-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let shift_amount = get_shift_amount(imm_val, SEW_widen); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + result[i] = match funct6 { + NI_VNCLIPU => { + let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr); + unsigned_saturation('m, result_wide) + }, + NI_VNCLIP => { + let v_double : bits('m * 4) = sign_extend(vs2_val[i]); + let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr); + signed_saturation('m, result_wide) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnclip.wv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnclip.wv.yaml new file mode 100644 index 000000000000..d3ad53d6edd1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnclip.wv.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnclip.wv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 101111-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let shift_amount = get_shift_amount(vs1_val[i], SEW_widen); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + result[i] = match funct6 { + NV_VNCLIPU => { + let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr); + unsigned_saturation('m, result_wide); + }, + NV_VNCLIP => { + let v_double : bits('m * 4) = sign_extend(vs2_val[i]); + let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr); + signed_saturation('m, result_wide); + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnclip.wx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnclip.wx.yaml new file mode 100644 index 000000000000..db64b746c4ca --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnclip.wx.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnclip.wx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 101111-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let shift_amount = get_shift_amount(rs1_val, SEW_widen); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + result[i] = match funct6 { + NX_VNCLIPU => { + let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr); + unsigned_saturation('m, result_wide) + }, + NX_VNCLIP => { + let v_double : bits('m * 4) = sign_extend(vs2_val[i]); + let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr); + signed_saturation('m, result_wide) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnclipu.wi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnclipu.wi.yaml new file mode 100644 index 000000000000..c2616b301c24 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnclipu.wi.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnclipu.wi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 101110-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let shift_amount = get_shift_amount(imm_val, SEW_widen); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + result[i] = match funct6 { + NI_VNCLIPU => { + let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr); + unsigned_saturation('m, result_wide) + }, + NI_VNCLIP => { + let v_double : bits('m * 4) = sign_extend(vs2_val[i]); + let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr); + signed_saturation('m, result_wide) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnclipu.wv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnclipu.wv.yaml new file mode 100644 index 000000000000..2d674722ef6e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnclipu.wv.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnclipu.wv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 101110-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let shift_amount = get_shift_amount(vs1_val[i], SEW_widen); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + result[i] = match funct6 { + NV_VNCLIPU => { + let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr); + unsigned_saturation('m, result_wide); + }, + NV_VNCLIP => { + let v_double : bits('m * 4) = sign_extend(vs2_val[i]); + let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr); + signed_saturation('m, result_wide); + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnclipu.wx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnclipu.wx.yaml new file mode 100644 index 000000000000..95521674aa7c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnclipu.wx.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnclipu.wx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 101110-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + let shift_amount = get_shift_amount(rs1_val, SEW_widen); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + result[i] = match funct6 { + NX_VNCLIPU => { + let result_wide = (vs2_val[i] >> shift_amount) + zero_extend('o, rounding_incr); + unsigned_saturation('m, result_wide) + }, + NX_VNCLIP => { + let v_double : bits('m * 4) = sign_extend(vs2_val[i]); + let result_wide = slice(v_double >> shift_amount, 0, 'o) + zero_extend('o, rounding_incr); + signed_saturation('m, result_wide) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnmsac.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnmsac.vv.yaml new file mode 100644 index 000000000000..32cab884ae80 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnmsac.vv.yaml @@ -0,0 +1,74 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnmsac.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101111-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VMACC => get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0) + vd_val[i], + MVV_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0), + MVV_VMADD => get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0) + vs2_val[i], + MVV_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnmsac.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnmsac.vx.yaml new file mode 100644 index 000000000000..388c8d8c5e97 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnmsac.vx.yaml @@ -0,0 +1,74 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnmsac.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, xs1, vs2, vm +encoding: + match: 101111-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VMACC => get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0) + vd_val[i], + MVX_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0), + MVX_VMADD => get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0) + vs2_val[i], + MVX_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnmsub.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnmsub.vv.yaml new file mode 100644 index 000000000000..3d6d446d9c79 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnmsub.vv.yaml @@ -0,0 +1,74 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnmsub.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 101011-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VMACC => get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0) + vd_val[i], + MVV_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vs2_val[i]), 0), + MVV_VMADD => get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0) + vs2_val[i], + MVV_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(vs1_val[i]) * signed(vd_val[i]), 0) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnmsub.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnmsub.vx.yaml new file mode 100644 index 000000000000..2a09c2caadcd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnmsub.vx.yaml @@ -0,0 +1,74 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnmsub.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, xs1, vs2, vm +encoding: + match: 101011-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VMACC => get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0) + vd_val[i], + MVX_VNMSAC => vd_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vs2_val[i]), 0), + MVX_VMADD => get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0) + vs2_val[i], + MVX_VNMSUB => vs2_val[i] - get_slice_int(SEW, signed(rs1_val) * signed(vd_val[i]), 0) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnsra.wi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnsra.wi.yaml new file mode 100644 index 000000000000..f5ef2e01b827 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnsra.wi.yaml @@ -0,0 +1,86 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnsra.wi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 101101-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + NIS_VNSRL => { + let shift_amount = get_shift_amount(imm_val, SEW_widen); + slice(vs2_val[i] >> shift_amount, 0, SEW) + }, + NIS_VNSRA => { + let shift_amount = get_shift_amount(imm_val, SEW_widen); + let v_double : bits('o * 2) = sign_extend(vs2_val[i]); + let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen); + slice(arith_shifted, 0, SEW) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnsra.wv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnsra.wv.yaml new file mode 100644 index 000000000000..77ef0a419431 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnsra.wv.yaml @@ -0,0 +1,86 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnsra.wv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 101101-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + NVS_VNSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW_widen); + slice(vs2_val[i] >> shift_amount, 0, SEW) + }, + NVS_VNSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW_widen); + let v_double : bits('o * 2) = sign_extend(vs2_val[i]); + let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen); + slice(arith_shifted, 0, SEW) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnsra.wx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnsra.wx.yaml new file mode 100644 index 000000000000..0fe44155ffe4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnsra.wx.yaml @@ -0,0 +1,86 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnsra.wx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 101101-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + NXS_VNSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW_widen); + slice(vs2_val[i] >> shift_amount, 0, SEW) + }, + NXS_VNSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW_widen); + let v_double : bits('o * 2) = sign_extend(vs2_val[i]); + let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen); + slice(arith_shifted, 0, SEW) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnsrl.wi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnsrl.wi.yaml new file mode 100644 index 000000000000..e5e5ad66dd96 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnsrl.wi.yaml @@ -0,0 +1,86 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnsrl.wi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 101100-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + NIS_VNSRL => { + let shift_amount = get_shift_amount(imm_val, SEW_widen); + slice(vs2_val[i] >> shift_amount, 0, SEW) + }, + NIS_VNSRA => { + let shift_amount = get_shift_amount(imm_val, SEW_widen); + let v_double : bits('o * 2) = sign_extend(vs2_val[i]); + let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen); + slice(arith_shifted, 0, SEW) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnsrl.wv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnsrl.wv.yaml new file mode 100644 index 000000000000..12d3d2b0aba2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnsrl.wv.yaml @@ -0,0 +1,86 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnsrl.wv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 101100-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + NVS_VNSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW_widen); + slice(vs2_val[i] >> shift_amount, 0, SEW) + }, + NVS_VNSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW_widen); + let v_double : bits('o * 2) = sign_extend(vs2_val[i]); + let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen); + slice(arith_shifted, 0, SEW) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vnsrl.wx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vnsrl.wx.yaml new file mode 100644 index 000000000000..421b42503742 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vnsrl.wx.yaml @@ -0,0 +1,86 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vnsrl.wx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 101100-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW_widen <= 64); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + NXS_VNSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW_widen); + slice(vs2_val[i] >> shift_amount, 0, SEW) + }, + NXS_VNSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW_widen); + let v_double : bits('o * 2) = sign_extend(vs2_val[i]); + let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen); + slice(arith_shifted, 0, SEW) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vor.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vor.vi.yaml new file mode 100644 index 000000000000..65f1b0946f7b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vor.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vor.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 001010-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vor.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vor.vv.yaml new file mode 100644 index 000000000000..73dfb60ee04f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vor.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vor.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001010-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vor.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vor.vx.yaml new file mode 100644 index 000000000000..254334fa49d7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vor.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vor.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001010-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vredand.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vredand.vs.yaml new file mode 100644 index 000000000000..2e073109bfb5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vredand.vs.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vredand.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000001-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ + + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; + + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ + + let 'n = num_elem_vs; + let 'd = num_elem_vd; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ + foreach (i from 0 to (num_elem_vs - 1)) { + if mask[i] then { + sum = match funct6 { + MVV_VREDSUM => sum + vs2_val[i], + MVV_VREDAND => sum & vs2_val[i], + MVV_VREDOR => sum | vs2_val[i], + MVV_VREDXOR => sum ^ vs2_val[i], + MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))), + MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))), + MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))), + MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum))) + } + } + }; + + write_single_element(SEW, 0, vd, sum); + /* other elements in vd are treated as tail elements, currently remain unchanged */ + /* TODO: configuration support for agnostic behavior */ + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vredmax.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vredmax.vs.yaml new file mode 100644 index 000000000000..d62b4943dd20 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vredmax.vs.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vredmax.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000111-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ + + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; + + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ + + let 'n = num_elem_vs; + let 'd = num_elem_vd; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ + foreach (i from 0 to (num_elem_vs - 1)) { + if mask[i] then { + sum = match funct6 { + MVV_VREDSUM => sum + vs2_val[i], + MVV_VREDAND => sum & vs2_val[i], + MVV_VREDOR => sum | vs2_val[i], + MVV_VREDXOR => sum ^ vs2_val[i], + MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))), + MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))), + MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))), + MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum))) + } + } + }; + + write_single_element(SEW, 0, vd, sum); + /* other elements in vd are treated as tail elements, currently remain unchanged */ + /* TODO: configuration support for agnostic behavior */ + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vredmaxu.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vredmaxu.vs.yaml new file mode 100644 index 000000000000..7af4e2aa6b6a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vredmaxu.vs.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vredmaxu.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000110-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ + + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; + + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ + + let 'n = num_elem_vs; + let 'd = num_elem_vd; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ + foreach (i from 0 to (num_elem_vs - 1)) { + if mask[i] then { + sum = match funct6 { + MVV_VREDSUM => sum + vs2_val[i], + MVV_VREDAND => sum & vs2_val[i], + MVV_VREDOR => sum | vs2_val[i], + MVV_VREDXOR => sum ^ vs2_val[i], + MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))), + MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))), + MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))), + MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum))) + } + } + }; + + write_single_element(SEW, 0, vd, sum); + /* other elements in vd are treated as tail elements, currently remain unchanged */ + /* TODO: configuration support for agnostic behavior */ + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vredmin.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vredmin.vs.yaml new file mode 100644 index 000000000000..2e7c3e3d1106 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vredmin.vs.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vredmin.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000101-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ + + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; + + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ + + let 'n = num_elem_vs; + let 'd = num_elem_vd; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ + foreach (i from 0 to (num_elem_vs - 1)) { + if mask[i] then { + sum = match funct6 { + MVV_VREDSUM => sum + vs2_val[i], + MVV_VREDAND => sum & vs2_val[i], + MVV_VREDOR => sum | vs2_val[i], + MVV_VREDXOR => sum ^ vs2_val[i], + MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))), + MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))), + MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))), + MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum))) + } + } + }; + + write_single_element(SEW, 0, vd, sum); + /* other elements in vd are treated as tail elements, currently remain unchanged */ + /* TODO: configuration support for agnostic behavior */ + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vredminu.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vredminu.vs.yaml new file mode 100644 index 000000000000..e037ab34e156 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vredminu.vs.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vredminu.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000100-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ + + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; + + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ + + let 'n = num_elem_vs; + let 'd = num_elem_vd; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ + foreach (i from 0 to (num_elem_vs - 1)) { + if mask[i] then { + sum = match funct6 { + MVV_VREDSUM => sum + vs2_val[i], + MVV_VREDAND => sum & vs2_val[i], + MVV_VREDOR => sum | vs2_val[i], + MVV_VREDXOR => sum ^ vs2_val[i], + MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))), + MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))), + MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))), + MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum))) + } + } + }; + + write_single_element(SEW, 0, vd, sum); + /* other elements in vd are treated as tail elements, currently remain unchanged */ + /* TODO: configuration support for agnostic behavior */ + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vredor.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vredor.vs.yaml new file mode 100644 index 000000000000..22b12c14aafb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vredor.vs.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vredor.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000010-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ + + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; + + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ + + let 'n = num_elem_vs; + let 'd = num_elem_vd; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ + foreach (i from 0 to (num_elem_vs - 1)) { + if mask[i] then { + sum = match funct6 { + MVV_VREDSUM => sum + vs2_val[i], + MVV_VREDAND => sum & vs2_val[i], + MVV_VREDOR => sum | vs2_val[i], + MVV_VREDXOR => sum ^ vs2_val[i], + MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))), + MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))), + MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))), + MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum))) + } + } + }; + + write_single_element(SEW, 0, vd, sum); + /* other elements in vd are treated as tail elements, currently remain unchanged */ + /* TODO: configuration support for agnostic behavior */ + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vredsum.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vredsum.vs.yaml new file mode 100644 index 000000000000..a69d263f0034 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vredsum.vs.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vredsum.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000000-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ + + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; + + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ + + let 'n = num_elem_vs; + let 'd = num_elem_vd; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ + foreach (i from 0 to (num_elem_vs - 1)) { + if mask[i] then { + sum = match funct6 { + MVV_VREDSUM => sum + vs2_val[i], + MVV_VREDAND => sum & vs2_val[i], + MVV_VREDOR => sum | vs2_val[i], + MVV_VREDXOR => sum ^ vs2_val[i], + MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))), + MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))), + MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))), + MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum))) + } + } + }; + + write_single_element(SEW, 0, vd, sum); + /* other elements in vd are treated as tail elements, currently remain unchanged */ + /* TODO: configuration support for agnostic behavior */ + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vredxor.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vredxor.vs.yaml new file mode 100644 index 000000000000..c96d30e39aae --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vredxor.vs.yaml @@ -0,0 +1,81 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vredxor.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000011-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */ + + if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL }; + + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ + + let 'n = num_elem_vs; + let 'd = num_elem_vd; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + + sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */ + foreach (i from 0 to (num_elem_vs - 1)) { + if mask[i] then { + sum = match funct6 { + MVV_VREDSUM => sum + vs2_val[i], + MVV_VREDAND => sum & vs2_val[i], + MVV_VREDOR => sum | vs2_val[i], + MVV_VREDXOR => sum ^ vs2_val[i], + MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))), + MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))), + MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))), + MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum))) + } + } + }; + + write_single_element(SEW, 0, vd, sum); + /* other elements in vd are treated as tail elements, currently remain unchanged */ + /* TODO: configuration support for agnostic behavior */ + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vrem.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vrem.vv.yaml new file mode 100644 index 000000000000..cdab37157ce7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vrem.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrem.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100011-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vrem.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vrem.vx.yaml new file mode 100644 index 000000000000..24f77098dc1d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vrem.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrem.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100011-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vremu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vremu.vv.yaml new file mode 100644 index 000000000000..66f2104c1397 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vremu.vv.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vremu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100010-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVV_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0), + MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW), + MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW), + MVV_VDIVU => { + let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + to_bits(SEW, q) + }, + MVV_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVV_VREMU => { + let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVV_VREM => { + let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i])); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vremu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vremu.vx.yaml new file mode 100644 index 000000000000..2ac68cc95fbc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vremu.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vremu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100010-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vrgather.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vrgather.vi.yaml new file mode 100644 index 000000000000..fcee2685abeb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vrgather.vi.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrgather.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 001100-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm)); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VSLIDEUP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i >= imm_val then vs2_val[i - imm_val] else vd_val[i] + }, + VI_VSLIDEDOWN => { + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if i + imm_val < VLMAX then vs2_val[i + imm_val] else zeros() + }, + VI_VRGATHER => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if imm_val < VLMAX then vs2_val[imm_val] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vrgather.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vrgather.vv.yaml new file mode 100644 index 000000000000..b3aba6c1a8e0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vrgather.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrgather.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001100-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vrgather.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vrgather.vx.yaml new file mode 100644 index 000000000000..85c7c8897bdd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vrgather.vx.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrgather.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001100-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : nat = unsigned(X(rs1)); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VSLIDEUP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i >= rs1_val then vs2_val[i - rs1_val] else vd_val[i] + }, + VX_VSLIDEDOWN => { + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if i + rs1_val < VLMAX then vs2_val[i + rs1_val] else zeros() + }, + VX_VRGATHER => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if rs1_val < VLMAX then vs2_val[rs1_val] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vrgatherei16.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vrgatherei16.vv.yaml new file mode 100644 index 000000000000..cf1604ad79a6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vrgatherei16.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrgatherei16.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001110-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vrsub.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vrsub.vi.yaml new file mode 100644 index 000000000000..9bf9e32d0798 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vrsub.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrsub.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 000011-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vrsub.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vrsub.vx.yaml new file mode 100644 index 000000000000..a881436a5aa2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vrsub.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrsub.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 000011-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vs1r.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vs1r.v.yaml new file mode 100644 index 000000000000..36e88c526c11 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vs1r.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vs1r.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1) +encoding: + match: 000000101000-----000-----0100111 + variables: + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vs2r.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vs2r.v.yaml new file mode 100644 index 000000000000..646fcf6611c3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vs2r.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vs2r.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1) +encoding: + match: 001000101000-----000-----0100111 + variables: + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vs4r.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vs4r.v.yaml new file mode 100644 index 000000000000..08b8787f7d9f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vs4r.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vs4r.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1) +encoding: + match: 011000101000-----000-----0100111 + variables: + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vs8r.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vs8r.v.yaml new file mode 100644 index 000000000000..de52ac17f139 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vs8r.v.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vs8r.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1) +encoding: + match: 111000101000-----000-----0100111 + variables: + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsadd.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsadd.vi.yaml new file mode 100644 index 000000000000..e8a65bdf5ff5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsadd.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsadd.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 100001-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsadd.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsadd.vv.yaml new file mode 100644 index 000000000000..fce943cdf96d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsadd.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsadd.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100001-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsadd.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsadd.vx.yaml new file mode 100644 index 000000000000..2d7789264729 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsadd.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsadd.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100001-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsaddu.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsaddu.vi.yaml new file mode 100644 index 000000000000..d9fd7e0205ec --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsaddu.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsaddu.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 100000-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsaddu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsaddu.vv.yaml new file mode 100644 index 000000000000..7412c3909e21 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsaddu.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsaddu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100000-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsaddu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsaddu.vx.yaml new file mode 100644 index 000000000000..79bfac15a906 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsaddu.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsaddu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100000-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsbc.vvm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsbc.vvm.yaml new file mode 100644 index 000000000000..f68fd5816926 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsbc.vvm.yaml @@ -0,0 +1,76 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsbc.vvm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, v0 +encoding: + match: 0100100----------000-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + /* for bypassing normal masking in init_masked_result */ + vec_trues : vector('n, dec, bool) = undefined; + foreach (i from 0 to (num_elem - 1)) { + vec_trues[i] = true + }; + + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VVMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(vs1_val[i]) + unsigned(bool_to_bits(vm_val[i]))), + VVMS_VSBC => to_bits(SEW, unsigned(vs2_val[i]) - unsigned(vs1_val[i]) - unsigned(bool_to_bits(vm_val[i]))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsbc.vxm.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsbc.vxm.yaml new file mode 100644 index 000000000000..4c1d5abf5add --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsbc.vxm.yaml @@ -0,0 +1,76 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsbc.vxm +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, v0 +encoding: + match: 0100100----------100-----1010111 + variables: + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_vd_masked(vd) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + /* for bypassing normal masking in init_masked_result */ + vec_trues : vector('n, dec, bool) = undefined; + foreach (i from 0 to (num_elem - 1)) { + vec_trues[i] = true + }; + + let vm_val : vector('n, dec, bool) = read_vmask_carry(num_elem, 0b0, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vec_trues); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VXMS_VADC => to_bits(SEW, unsigned(vs2_val[i]) + unsigned(rs1_val) + unsigned(bool_to_bits(vm_val[i]))), + VXMS_VSBC => to_bits(SEW, unsigned(vs2_val[i]) - unsigned(rs1_val) - unsigned(bool_to_bits(vm_val[i]))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vse16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vse16.v.yaml new file mode 100644 index 000000000000..7934810ed3bf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vse16.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vse16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 000000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vse32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vse32.v.yaml new file mode 100644 index 000000000000..0eaf2636e3fa --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vse32.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vse32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 000000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vse64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vse64.v.yaml new file mode 100644 index 000000000000..888f5c2aef41 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vse64.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vse64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 000000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vse8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vse8.v.yaml new file mode 100644 index 000000000000..e3d77fc5da78 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vse8.v.yaml @@ -0,0 +1,52 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vse8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 000000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsseg(nf_int, vm, vs3, load_width_bytes, rs1, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsetivli.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsetivli.yaml new file mode 100644 index 000000000000..6471d88e8125 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsetivli.yaml @@ -0,0 +1,122 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsetivli +long_name: Vector Set Vector Type Immediate and Vector Length Immediate +description: Set the vtype and vl CSRs, and write the new value of vl into rd. +definedBy: + extension: + name: V +assembly: xd, uimm, vtypei +encoding: + match: 11---------------111-----1010111 + variables: + - name: vtypei + location: 29-20 + - name: uimm + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg new_vtype = vtypei; + if ((new_vtype[xlen() - 1] == 1'b1) # software is setting the illegal bit + || ((new_vtype & 8'd0) != 0) # reserved bits + || (new_vtype[5] == 1) # reserved vsew encoding + || (new_vtype[2:0] == 3'b100) # reserved vlmul encoding + || (xlen() == 32 && new_vtype[2:0] == 3'b101)) # reserved LMUL in RV32 + { + CSR[vtype].VILL = 1; + CSR[vtype].VMA = 0; + CSR[vtype].VTA = 0; + CSR[vtype].VSEW = 0; + CSR[vtype].VLMUL = 0; + } else { + # valid, do the write + CSR[vtype].VILL = 0; + CSR[vtype].VMA = new_vtype[7]; + CSR[vtype].VTA = new_vtype[6]; + CSR[vtype].VSEW = new_vtype[5:3]; + CSR[vtype].VLMUL = new_vtype[2:0]; + } + + VectorState state = vector_state(); + XReg vlen = VLEN; + XReg vlmax = (vlen << state.log2_lmul) >> state.log2_sew; + XReg AVL = uimm; + XReg CEIL_AVL_OVER_TWO = (AVL + 1) / 2; + if (AVL < vlmax) { + CSR[vl].VALUE = AVL; + } else if (AVL < 2*vlmax) { + if (RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX == "ceil(AVL/2)") { + CSR[vl].VALUE = CEIL_AVL_OVER_TWO; + } else if (RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX == "VLMAX") { + CSR[vl].VALUE = vlmax; + } else { + unpredictable("Implementations may choose a custom value for vl in the case AVL < (2*VLMAX), so long as ceil(AVL/2) <= vl <= VLMAX"); + } + } else { + CSR[vl].VALUE = vlmax; + } + + X[xd] = CSR[vl].VALUE; + CSR[vstart].VALUE = 0; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let VLEN_pow = get_vlen_pow(); + let ELEN_pow = get_elen_pow(); + let LMUL_pow_ori = get_lmul_pow(); + let SEW_pow_ori = get_sew_pow(); + let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori; + + /* set vtype */ + vtype->bits() = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul; + + /* check legal SEW and LMUL and calculate VLMAX */ + let LMUL_pow_new = get_lmul_pow(); + let SEW_pow_new = get_sew_pow(); + if SEW_pow_new > LMUL_pow_new + ELEN_pow then { + /* Note: Implementations can set vill or trap if the vtype setting is not supported. + * TODO: configuration support for both solutions + */ + vtype->bits() = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */ + vl = zeros(); + print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); + print_reg("CSR vl <- " ^ BitStr(vl)); + return RETIRE_SUCCESS + }; + let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new); + let AVL = unsigned(uimm); /* AVL is encoded as 5-bit zero-extended imm in the rs1 field */ + + /* set vl according to VLMAX and AVL */ + vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL) + else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2) + else to_bits(sizeof(xlen), VLMAX); + /* Note: ceil(AVL / 2) <= vl <= VLMAX when VLMAX < AVL < (2 * VLMAX) + * TODO: configuration support for either using ceil(AVL / 2) or VLMAX + */ + X(rd) = vl; + print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); + print_reg("CSR vl <- " ^ BitStr(vl)); + + /* reset vstart to 0 */ + vstart = zeros(); + print_reg("CSR vstart <- " ^ BitStr(vstart)); + + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsetvl.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsetvl.yaml new file mode 100644 index 000000000000..aea633f9c21c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsetvl.yaml @@ -0,0 +1,147 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsetvl +long_name: Vector Set Vector Type and Vector Length +description: Set the vtype and vl CSRs, and write the new value of vl into rd. +definedBy: + extension: + name: V +assembly: xd, xs1, xs2 +encoding: + match: 1000000----------111-----1010111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg new_vtype = X[xs2]; + if ((new_vtype[xlen() - 1] == 1'b1) # software is setting the illegal bit + || ((new_vtype & 8'd0) != 0) # reserved bits + || (new_vtype[5] == 1) # reserved vsew encoding + || (new_vtype[2:0] == 3'b100) # reserved vlmul encoding + || (xlen() == 32 && new_vtype[2:0] == 3'b101)) # reserved LMUL in RV32 + { + CSR[vtype].VILL = 1; + CSR[vtype].VMA = 0; + CSR[vtype].VTA = 0; + CSR[vtype].VSEW = 0; + CSR[vtype].VLMUL = 0; + } else { + # valid, do the write + CSR[vtype].VILL = 0; + CSR[vtype].VMA = new_vtype[7]; + CSR[vtype].VTA = new_vtype[6]; + CSR[vtype].VSEW = new_vtype[5:3]; + CSR[vtype].VLMUL = new_vtype[2:0]; + } + + VectorState state = vector_state(); + XReg vlen = VLEN; + XReg vlmax = (vlen << state.log2_lmul) >> state.log2_sew; + XReg avl = X[xs1]; + XReg ceil_avl_over_two = (avl + 1) / 2; + if (avl < vlmax) { + CSR[vl].VALUE = avl; + } else if (avl < 2*vlmax) { + if (RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX == "ceil(AVL/2)") { + CSR[vl].VALUE = ceil_avl_over_two; + } else if (RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX == "VLMAX") { + CSR[vl].VALUE = vlmax; + } else { + unpredictable("Implementations may choose a custom value for vl in the case AVL < (2*VLMAX), so long as ceil(AVL/2) <= vl <= VLMAX"); + } + } else { + CSR[vl].VALUE = vlmax; + } + + X[xd] = CSR[vl].VALUE; + CSR[vstart].VALUE = 0; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let VLEN_pow = get_vlen_pow(); + let ELEN_pow = get_elen_pow(); + let LMUL_pow_ori = get_lmul_pow(); + let SEW_pow_ori = get_sew_pow(); + let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori; + + /* set vtype */ + match op { + VSETVLI => { + vtype->bits() = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul + }, + VSETVL => { + let rs2 : regidx = sew[1 .. 0] @ lmul; + vtype->bits() = X(rs2) + } + }; + + /* check legal SEW and LMUL and calculate VLMAX */ + let LMUL_pow_new = get_lmul_pow(); + let SEW_pow_new = get_sew_pow(); + if SEW_pow_new > LMUL_pow_new + ELEN_pow then { + /* Note: Implementations can set vill or trap if the vtype setting is not supported. + * TODO: configuration support for both solutions + */ + vtype->bits() = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */ + vl = zeros(); + print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); + print_reg("CSR vl <- " ^ BitStr(vl)); + return RETIRE_SUCCESS + }; + let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new); + + /* set vl according to VLMAX and AVL */ + if (rs1 != 0b00000) then { /* normal stripmining */ + let rs1_val = X(rs1); + let AVL = unsigned(rs1_val); + vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL) + else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2) + else to_bits(sizeof(xlen), VLMAX); + /* Note: ceil(AVL / 2) <= vl <= VLMAX when VLMAX < AVL < (2 * VLMAX) + * TODO: configuration support for either using ceil(AVL / 2) or VLMAX + */ + X(rd) = vl; + } else if (rd != 0b00000) then { /* set vl to VLMAX */ + let AVL = unsigned(ones(sizeof(xlen))); + vl = to_bits(sizeof(xlen), VLMAX); + X(rd) = vl; + } else { /* keep existing vl */ + let AVL = unsigned(vl); + let ratio_pow_new = SEW_pow_new - LMUL_pow_new; + if (ratio_pow_new != ratio_pow_ori) then { + /* Note: Implementations can set vill or trap if the vtype setting is not supported. + * TODO: configuration support for both solutions + */ + vtype->bits() = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */ + vl = zeros(); + } + }; + print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); + print_reg("CSR vl <- " ^ BitStr(vl)); + + /* reset vstart to 0 */ + vstart = zeros(); + print_reg("CSR vstart <- " ^ BitStr(vstart)); + + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsetvli.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsetvli.yaml new file mode 100644 index 000000000000..b2302d9bd51b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsetvli.yaml @@ -0,0 +1,162 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsetvli +long_name: Vector Set Vector Type and Vector Length Immediate +description: Set the vtype and vl CSRs, and write the new value of vl into rd. +definedBy: + extension: + name: V +assembly: xd, xs1, vtypei +encoding: + match: 0----------------111-----1010111 + variables: + - name: vtypei + location: 30-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg new_vtype = vtypei; + if ((new_vtype[xlen() - 1] == 1'b1) # software is setting the illegal bit + || ((new_vtype & 8'd0) != 0) # reserved bits + || (new_vtype[5] == 1) # reserved vsew encoding + || (new_vtype[2:0] == 3'b100) # reserved vlmul encoding + # || (xlen() == 32 && new_vtype[2:0] == 3'b101) # reserved LMUL in RV32 + ) + { + CSR[vtype].VILL = 1; + CSR[vtype].VMA = 0; + CSR[vtype].VTA = 0; + CSR[vtype].VSEW = 0; + CSR[vtype].VLMUL = 0; + CSR[vl].VALUE = 0; + } else + { + # valid, do the write + CSR[vtype].VILL = 0; + CSR[vtype].VMA = new_vtype[7]; + CSR[vtype].VTA = new_vtype[6]; + CSR[vtype].VSEW = new_vtype[5:3]; + CSR[vtype].VLMUL = new_vtype[2:0]; + + VectorState state = vector_state(); + XReg vlen = VLEN; + XReg vlmax = (vlen << state.log2_lmul) >> state.log2_sew; + XReg avl = X[xs1]; + XReg ceil_avl_over_two = (avl + 1) / 2; + + if (xs1 == 0) + { + CSR[vl].VALUE = vlmax; + } else + { + if (avl <= vlmax) + { + CSR[vl].VALUE = avl; + } else if (avl < 2*vlmax) + { + if (RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX == "ceil(AVL/2)") + { + CSR[vl].VALUE = ceil_avl_over_two; + } else if (RVV_VL_WHEN_AVL_LT_DOUBLE_VLMAX == "VLMAX") + { + CSR[vl].VALUE = vlmax; + } else + { + unpredictable("Implementations may choose a custom value for vl in the case AVL < (2*VLMAX), so long as ceil(AVL/2) <= vl <= VLMAX"); + } + } else + { + CSR[vl].VALUE = vlmax; + } + } + } + X[xd] = CSR[vl].VALUE; + CSR[vstart].VALUE = 0; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let VLEN_pow = get_vlen_pow(); + let ELEN_pow = get_elen_pow(); + let LMUL_pow_ori = get_lmul_pow(); + let SEW_pow_ori = get_sew_pow(); + let ratio_pow_ori = SEW_pow_ori - LMUL_pow_ori; + + /* set vtype */ + match op { + VSETVLI => { + vtype->bits() = 0b0 @ zeros(sizeof(xlen) - 9) @ ma @ ta @ sew @ lmul + }, + VSETVL => { + let rs2 : regidx = sew[1 .. 0] @ lmul; + vtype->bits() = X(rs2) + } + }; + + /* check legal SEW and LMUL and calculate VLMAX */ + let LMUL_pow_new = get_lmul_pow(); + let SEW_pow_new = get_sew_pow(); + if SEW_pow_new > LMUL_pow_new + ELEN_pow then { + /* Note: Implementations can set vill or trap if the vtype setting is not supported. + * TODO: configuration support for both solutions + */ + vtype->bits() = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */ + vl = zeros(); + print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); + print_reg("CSR vl <- " ^ BitStr(vl)); + return RETIRE_SUCCESS + }; + let VLMAX = int_power(2, VLEN_pow + LMUL_pow_new - SEW_pow_new); + + /* set vl according to VLMAX and AVL */ + if (rs1 != 0b00000) then { /* normal stripmining */ + let rs1_val = X(rs1); + let AVL = unsigned(rs1_val); + vl = if AVL <= VLMAX then to_bits(sizeof(xlen), AVL) + else if AVL < 2 * VLMAX then to_bits(sizeof(xlen), (AVL + 1) / 2) + else to_bits(sizeof(xlen), VLMAX); + /* Note: ceil(AVL / 2) <= vl <= VLMAX when VLMAX < AVL < (2 * VLMAX) + * TODO: configuration support for either using ceil(AVL / 2) or VLMAX + */ + X(rd) = vl; + } else if (rd != 0b00000) then { /* set vl to VLMAX */ + let AVL = unsigned(ones(sizeof(xlen))); + vl = to_bits(sizeof(xlen), VLMAX); + X(rd) = vl; + } else { /* keep existing vl */ + let AVL = unsigned(vl); + let ratio_pow_new = SEW_pow_new - LMUL_pow_new; + if (ratio_pow_new != ratio_pow_ori) then { + /* Note: Implementations can set vill or trap if the vtype setting is not supported. + * TODO: configuration support for both solutions + */ + vtype->bits() = 0b1 @ zeros(sizeof(xlen) - 1); /* set vtype.vill */ + vl = zeros(); + } + }; + print_reg("CSR vtype <- " ^ BitStr(vtype.bits())); + print_reg("CSR vl <- " ^ BitStr(vl)); + + /* reset vstart to 0 */ + vstart = zeros(); + print_reg("CSR vstart <- " ^ BitStr(vstart)); + + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsext.vf2.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsext.vf2.yaml new file mode 100644 index 000000000000..be143b5b9762 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsext.vf2.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsext.vf2 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00111010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_half = SEW / 2; + let LMUL_pow_half = LMUL_pow - 1; + + if illegal_variable_width(vd, vm, SEW_half, LMUL_pow_half) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_half, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_half; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_half, LMUL_pow_half, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW > SEW_half); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VEXT2_ZVF2 => zero_extend(vs2_val[i]), + VEXT2_SVF2 => sign_extend(vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsext.vf4.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsext.vf4.yaml new file mode 100644 index 000000000000..41447245f2f1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsext.vf4.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsext.vf4 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00101010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_quart = SEW / 4; + let LMUL_pow_quart = LMUL_pow - 2; + + if illegal_variable_width(vd, vm, SEW_quart, LMUL_pow_quart) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_quart, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_quart; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_quart, LMUL_pow_quart, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW > SEW_quart); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VEXT4_ZVF4 => zero_extend(vs2_val[i]), + VEXT4_SVF4 => sign_extend(vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsext.vf8.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsext.vf8.yaml new file mode 100644 index 000000000000..079e791d858f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsext.vf8.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsext.vf8 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00011010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_eighth = SEW / 8; + let LMUL_pow_eighth = LMUL_pow - 3; + + if illegal_variable_width(vd, vm, SEW_eighth, LMUL_pow_eighth) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_eighth, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_eighth; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_eighth, LMUL_pow_eighth, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW > SEW_eighth); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VEXT8_ZVF8 => zero_extend(vs2_val[i]), + VEXT8_SVF8 => sign_extend(vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vslide1down.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vslide1down.vx.yaml new file mode 100644 index 000000000000..7d026ce2b5dd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vslide1down.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vslide1down.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001111-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vslide1up.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vslide1up.vx.yaml new file mode 100644 index 000000000000..dd650ec14b79 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vslide1up.vx.yaml @@ -0,0 +1,125 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vslide1up.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001110-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + MVX_VAADDU => { + let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VAADD => { + let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_add, 1); + slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUBU => { + let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VASUB => { + let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val); + let rounding_incr = get_fixed_rounding_incr(result_sub, 1); + slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr) + }, + MVX_VSLIDE1UP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i == 0 then rs1_val else vs2_val[i - 1] + }, + MVX_VSLIDE1DOWN => { + let last_elem = get_end_element(); + assert(last_elem < num_elem); + if i < last_elem then vs2_val[i + 1] else rs1_val + }, + MVX_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), 0), + MVX_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(rs1_val), SEW), + MVX_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(rs1_val), SEW), + MVX_VDIVU => { + let q : int = if unsigned(rs1_val) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(rs1_val)); + to_bits(SEW, q) + }, + MVX_VDIV => { + let elem_max : int = 2 ^ (SEW - 1) - 1; + let elem_min : int = 0 - 2 ^ (SEW - 1); + let q : int = if signed(rs1_val) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* check for signed overflow */ + let q' : int = if q > elem_max then elem_min else q; + to_bits(SEW, q') + }, + MVX_VREMU => { + let r : int = if unsigned(rs1_val) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned (rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + }, + MVX_VREM => { + let r : int = if signed(rs1_val) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(rs1_val)); + /* signed overflow case returns zero naturally as required due to -1 divisor */ + to_bits(SEW, r) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vslidedown.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vslidedown.vi.yaml new file mode 100644 index 000000000000..46535feab0e0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vslidedown.vi.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vslidedown.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 001111-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm)); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VSLIDEUP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i >= imm_val then vs2_val[i - imm_val] else vd_val[i] + }, + VI_VSLIDEDOWN => { + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if i + imm_val < VLMAX then vs2_val[i + imm_val] else zeros() + }, + VI_VRGATHER => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if imm_val < VLMAX then vs2_val[imm_val] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vslidedown.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vslidedown.vx.yaml new file mode 100644 index 000000000000..f69025a3d37e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vslidedown.vx.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vslidedown.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001111-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : nat = unsigned(X(rs1)); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VSLIDEUP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i >= rs1_val then vs2_val[i - rs1_val] else vd_val[i] + }, + VX_VSLIDEDOWN => { + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if i + rs1_val < VLMAX then vs2_val[i + rs1_val] else zeros() + }, + VX_VRGATHER => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if rs1_val < VLMAX then vs2_val[rs1_val] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vslideup.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vslideup.vi.yaml new file mode 100644 index 000000000000..8dafdb42c3f4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vslideup.vi.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vslideup.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 001110-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : nat = unsigned(zero_extend(sizeof(xlen), simm)); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VSLIDEUP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i >= imm_val then vs2_val[i - imm_val] else vd_val[i] + }, + VI_VSLIDEDOWN => { + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if i + imm_val < VLMAX then vs2_val[i + imm_val] else zeros() + }, + VI_VRGATHER => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if imm_val < VLMAX then vs2_val[imm_val] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vslideup.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vslideup.vx.yaml new file mode 100644 index 000000000000..67e4c57beaa7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vslideup.vx.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vslideup.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001110-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : nat = unsigned(X(rs1)); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VSLIDEUP => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + if i >= rs1_val then vs2_val[i - rs1_val] else vd_val[i] + }, + VX_VSLIDEDOWN => { + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if i + rs1_val < VLMAX then vs2_val[i + rs1_val] else zeros() + }, + VX_VRGATHER => { + if (vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX > 0 & VLMAX <= 'n); + if rs1_val < VLMAX then vs2_val[rs1_val] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsll.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsll.vi.yaml new file mode 100644 index 000000000000..cca96cab6648 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsll.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsll.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 100101-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsll.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsll.vv.yaml new file mode 100644 index 000000000000..f738d234b48b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsll.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsll.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100101-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsll.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsll.vx.yaml new file mode 100644 index 000000000000..73634bb70211 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsll.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsll.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100101-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsm.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsm.v.yaml new file mode 100644 index 000000000000..377833f10840 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsm.v.yaml @@ -0,0 +1,48 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsm.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1) +encoding: + match: 000000101011-----000-----0100111 + variables: + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW = 8; + let EMUL_pow = 0; + let vl_val = unsigned(vl); + let evl : int = if vl_val % 8 == 0 then vl_val / 8 else vl_val / 8 + 1; /* the effective vector length is evl=ceil(vl/8) */ + let num_elem = get_num_elem(EMUL_pow, EEW); + + if illegal_vd_unmasked() then { handle_illegal(); return RETIRE_FAIL }; + + assert(evl >= 0); + process_vm(vd_or_vs3, rs1, num_elem, evl, op) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsmul.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsmul.vv.yaml new file mode 100644 index 000000000000..cc0c269173e6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsmul.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsmul.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100111-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsmul.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsmul.vx.yaml new file mode 100644 index 000000000000..58fa0524bdf1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsmul.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsmul.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100111-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxei16.v.yaml new file mode 100644 index 000000000000..13a360bbea1c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxei16.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsoxei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 000011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ + let nf_int = nfields_int(nf); + + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxei32.v.yaml new file mode 100644 index 000000000000..0dbcf62a3d79 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxei32.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsoxei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 000011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ + let nf_int = nfields_int(nf); + + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxei64.v.yaml new file mode 100644 index 000000000000..3725e879800c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxei64.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsoxei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 000011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ + let nf_int = nfields_int(nf); + + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxei8.v.yaml new file mode 100644 index 000000000000..d3d7a84639c4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxei8.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsoxei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 000011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ + let nf_int = nfields_int(nf); + + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei16.v.yaml new file mode 100644 index 000000000000..b15e97d5d6a8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg2ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 001011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei32.v.yaml new file mode 100644 index 000000000000..cafa479de834 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg2ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 001011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei64.v.yaml new file mode 100644 index 000000000000..0f7b9c993d2b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg2ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 001011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei8.v.yaml new file mode 100644 index 000000000000..62e0e4de3d5e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg2ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg2ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 001011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei16.v.yaml new file mode 100644 index 000000000000..b37bc4aaa7b0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg3ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 010011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei32.v.yaml new file mode 100644 index 000000000000..94497d2dff23 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg3ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 010011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei64.v.yaml new file mode 100644 index 000000000000..5e2e1f772ad9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg3ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 010011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei8.v.yaml new file mode 100644 index 000000000000..aa6a55892ced --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg3ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg3ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 010011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei16.v.yaml new file mode 100644 index 000000000000..4277a65b84cd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg4ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 011011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei32.v.yaml new file mode 100644 index 000000000000..27efc7d0c1d9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg4ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 011011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei64.v.yaml new file mode 100644 index 000000000000..d4fe987b30ef --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg4ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 011011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei8.v.yaml new file mode 100644 index 000000000000..d25003713b90 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg4ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg4ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 011011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei16.v.yaml new file mode 100644 index 000000000000..dc56cb320be8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg5ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 100011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei32.v.yaml new file mode 100644 index 000000000000..20945e6699cd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg5ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 100011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei64.v.yaml new file mode 100644 index 000000000000..03a7da9f0aea --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg5ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 100011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei8.v.yaml new file mode 100644 index 000000000000..b062edfe4152 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg5ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg5ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 100011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei16.v.yaml new file mode 100644 index 000000000000..592d6e0315c6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg6ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 101011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei32.v.yaml new file mode 100644 index 000000000000..b5e1827cd1d9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg6ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 101011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei64.v.yaml new file mode 100644 index 000000000000..75cce93ca0fa --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg6ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 101011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei8.v.yaml new file mode 100644 index 000000000000..2713ac2425c4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg6ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg6ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 101011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei16.v.yaml new file mode 100644 index 000000000000..99fb4aa37888 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg7ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 110011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei32.v.yaml new file mode 100644 index 000000000000..b68b2490d012 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg7ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 110011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei64.v.yaml new file mode 100644 index 000000000000..761ed9634d56 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg7ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 110011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei8.v.yaml new file mode 100644 index 000000000000..9a28aec5bed0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg7ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg7ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 110011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei16.v.yaml new file mode 100644 index 000000000000..11d7632cf7c7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg8ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 111011-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei32.v.yaml new file mode 100644 index 000000000000..a46e33fa1a19 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg8ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 111011-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei64.v.yaml new file mode 100644 index 000000000000..a67e235c1384 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg8ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 111011-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei8.v.yaml new file mode 100644 index 000000000000..0474b8a826a8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsoxseg8ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsoxseg8ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 111011-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsra.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsra.vi.yaml new file mode 100644 index 000000000000..616eef4e02cd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsra.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsra.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 101001-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsra.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsra.vv.yaml new file mode 100644 index 000000000000..ffded09ae266 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsra.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsra.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 101001-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsra.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsra.vx.yaml new file mode 100644 index 000000000000..6b71f1445b34 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsra.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsra.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 101001-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsrl.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsrl.vi.yaml new file mode 100644 index 000000000000..3022a52b8074 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsrl.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsrl.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 101000-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsrl.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsrl.vv.yaml new file mode 100644 index 000000000000..2cda65546c15 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsrl.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsrl.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 101000-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsrl.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsrl.vx.yaml new file mode 100644 index 000000000000..5336f6660e05 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsrl.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsrl.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 101000-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsse16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsse16.v.yaml new file mode 100644 index 000000000000..cdc8da229231 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsse16.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsse16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 000010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsse32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsse32.v.yaml new file mode 100644 index 000000000000..4a905e9dd114 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsse32.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsse32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 000010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsse64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsse64.v.yaml new file mode 100644 index 000000000000..4451ba68991c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsse64.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsse64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 000010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsse8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsse8.v.yaml new file mode 100644 index 000000000000..4651c43fc0bf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsse8.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsse8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 000010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let load_width_bytes = vlewidth_bytesnumber(width); + let EEW = load_width_bytes * 8; + let EEW_pow = vlewidth_pow(width); + let SEW_pow = get_sew_pow(); + let LMUL_pow = get_lmul_pow(); + let EMUL_pow = EEW_pow - SEW_pow + LMUL_pow; + let num_elem = get_num_elem(EMUL_pow, EEW); + let nf_int = nfields_int(nf); + + if illegal_store(nf_int, EEW, EMUL_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vssseg(nf_int, vm, vs3, load_width_bytes, rs1, rs2, EMUL_pow, num_elem) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e16.v.yaml new file mode 100644 index 000000000000..c68b3569f459 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg2e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 001000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e32.v.yaml new file mode 100644 index 000000000000..96d76fdee5fe --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg2e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 001000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e64.v.yaml new file mode 100644 index 000000000000..21d998dbe98c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg2e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 001000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e8.v.yaml new file mode 100644 index 000000000000..1c8a525e0f7a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg2e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg2e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 001000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e16.v.yaml new file mode 100644 index 000000000000..2f3efe6cd6f8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg3e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 010000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e32.v.yaml new file mode 100644 index 000000000000..6e935f0431fd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg3e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 010000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e64.v.yaml new file mode 100644 index 000000000000..22e75a68c3c5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg3e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 010000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e8.v.yaml new file mode 100644 index 000000000000..14082e37d467 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg3e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg3e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 010000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e16.v.yaml new file mode 100644 index 000000000000..ee18139a3e40 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg4e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 011000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e32.v.yaml new file mode 100644 index 000000000000..f3c4a8938f6e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg4e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 011000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e64.v.yaml new file mode 100644 index 000000000000..040bfb5eb74d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg4e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 011000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e8.v.yaml new file mode 100644 index 000000000000..48ac14a83629 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg4e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg4e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 011000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e16.v.yaml new file mode 100644 index 000000000000..4b350a606876 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg5e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 100000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e32.v.yaml new file mode 100644 index 000000000000..52631d1bd83a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg5e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 100000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e64.v.yaml new file mode 100644 index 000000000000..cce85bdff703 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg5e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 100000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e8.v.yaml new file mode 100644 index 000000000000..f40ee3aa7fb3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg5e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg5e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 100000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e16.v.yaml new file mode 100644 index 000000000000..46efc386c841 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg6e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 101000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e32.v.yaml new file mode 100644 index 000000000000..32e3c48d4b23 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg6e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 101000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e64.v.yaml new file mode 100644 index 000000000000..6c59fcc1913f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg6e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 101000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e8.v.yaml new file mode 100644 index 000000000000..4e76f80fc12c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg6e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg6e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 101000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e16.v.yaml new file mode 100644 index 000000000000..b149851e62f2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg7e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 110000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e32.v.yaml new file mode 100644 index 000000000000..ab26736c118d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg7e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 110000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e64.v.yaml new file mode 100644 index 000000000000..854089fabb0b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg7e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 110000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e8.v.yaml new file mode 100644 index 000000000000..ab69f4313e01 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg7e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg7e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 110000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e16.v.yaml new file mode 100644 index 000000000000..f219f824ff31 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e16.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg8e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 111000-00000-----101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e32.v.yaml new file mode 100644 index 000000000000..1f722f030202 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e32.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg8e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 111000-00000-----110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e64.v.yaml new file mode 100644 index 000000000000..925c40fa6b26 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e64.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg8e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 111000-00000-----111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e8.v.yaml new file mode 100644 index 000000000000..ae089964006a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsseg8e8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsseg8e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vm +encoding: + match: 111000-00000-----000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssra.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssra.vi.yaml new file mode 100644 index 000000000000..af84fc0c5f6b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssra.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vssra.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 101011-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssra.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssra.vv.yaml new file mode 100644 index 000000000000..3f8fe652765f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssra.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vssra.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 101011-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssra.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssra.vx.yaml new file mode 100644 index 000000000000..e390c1f2e4df --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssra.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vssra.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 101011-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssrl.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssrl.vi.yaml new file mode 100644 index 000000000000..5f2601378cdc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssrl.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vssrl.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 101010-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssrl.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssrl.vv.yaml new file mode 100644 index 000000000000..809c912c7211 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssrl.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vssrl.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 101010-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssrl.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssrl.vx.yaml new file mode 100644 index 000000000000..342d28dcf93d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssrl.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vssrl.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 101010-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e16.v.yaml new file mode 100644 index 000000000000..d22527f7c64c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg2e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 001010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e32.v.yaml new file mode 100644 index 000000000000..c78cd3923f0c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg2e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 001010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e64.v.yaml new file mode 100644 index 000000000000..cff65b133173 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg2e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 001010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e8.v.yaml new file mode 100644 index 000000000000..e659e69ddfc2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg2e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg2e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 001010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e16.v.yaml new file mode 100644 index 000000000000..78dfb1ef0e2c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg3e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 010010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e32.v.yaml new file mode 100644 index 000000000000..b545ffc78617 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg3e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 010010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e64.v.yaml new file mode 100644 index 000000000000..e44ff4bf9b2d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg3e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 010010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e8.v.yaml new file mode 100644 index 000000000000..0dce30bb6c48 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg3e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg3e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 010010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e16.v.yaml new file mode 100644 index 000000000000..f752a3b29cfa --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg4e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 011010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e32.v.yaml new file mode 100644 index 000000000000..8e01a30a6bbf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg4e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 011010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e64.v.yaml new file mode 100644 index 000000000000..4d6d40581b77 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg4e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 011010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e8.v.yaml new file mode 100644 index 000000000000..23c052e5e03d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg4e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg4e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 011010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e16.v.yaml new file mode 100644 index 000000000000..70105f389b37 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg5e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 100010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e32.v.yaml new file mode 100644 index 000000000000..961000d487c6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg5e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 100010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e64.v.yaml new file mode 100644 index 000000000000..5ec8907460cf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg5e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 100010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e8.v.yaml new file mode 100644 index 000000000000..ebe89d3fc5da --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg5e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg5e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 100010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e16.v.yaml new file mode 100644 index 000000000000..f3e3cccbfac3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg6e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 101010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e32.v.yaml new file mode 100644 index 000000000000..dd6cc3b50815 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg6e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 101010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e64.v.yaml new file mode 100644 index 000000000000..5f1de9af3afc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg6e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 101010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e8.v.yaml new file mode 100644 index 000000000000..69613547139d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg6e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg6e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 101010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e16.v.yaml new file mode 100644 index 000000000000..5e3cbfda8eef --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg7e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 110010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e32.v.yaml new file mode 100644 index 000000000000..d017160a85d5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg7e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 110010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e64.v.yaml new file mode 100644 index 000000000000..ad3ef11d0981 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg7e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 110010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e8.v.yaml new file mode 100644 index 000000000000..530d704cf0b0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg7e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg7e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 110010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e16.v.yaml new file mode 100644 index 000000000000..5b5a8d1e5609 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg8e16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 111010-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e32.v.yaml new file mode 100644 index 000000000000..20855bff3fa2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg8e32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 111010-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e64.v.yaml new file mode 100644 index 000000000000..44b35ebdf674 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg8e64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 111010-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e8.v.yaml new file mode 100644 index 000000000000..e6fa31184545 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssseg8e8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vssseg8e8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), xs2, vm +encoding: + match: 111010-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssub.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssub.vv.yaml new file mode 100644 index 000000000000..d92778fd8304 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssub.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vssub.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100011-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssub.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssub.vx.yaml new file mode 100644 index 000000000000..402090be9497 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssub.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vssub.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100011-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssubu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssubu.vv.yaml new file mode 100644 index 000000000000..51e3c3589a7c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssubu.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vssubu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 100010-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vssubu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vssubu.vx.yaml new file mode 100644 index 000000000000..3d10a7e1ed03 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vssubu.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vssubu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 100010-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsub.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsub.vv.yaml new file mode 100644 index 000000000000..5dc012ceb91d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsub.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsub.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 000010-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsub.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsub.vx.yaml new file mode 100644 index 000000000000..29f3c57220a8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsub.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsub.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 000010-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxei16.v.yaml new file mode 100644 index 000000000000..b30bf3efc80a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxei16.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsuxei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 000001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ + let nf_int = nfields_int(nf); + + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxei32.v.yaml new file mode 100644 index 000000000000..afa42f1605f1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxei32.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsuxei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 000001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ + let nf_int = nfields_int(nf); + + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxei64.v.yaml new file mode 100644 index 000000000000..8c9019daebd2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxei64.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsuxei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 000001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ + let nf_int = nfields_int(nf); + + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxei8.v.yaml new file mode 100644 index 000000000000..d613b5063ffd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxei8.v.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsuxei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 000001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let EEW_index_pow = vlewidth_pow(width); + let EEW_index_bytes = vlewidth_bytesnumber(width); + let EEW_data_pow = get_sew_pow(); + let EEW_data_bytes = get_sew_bytes(); + let EMUL_data_pow = get_lmul_pow(); + let EMUL_index_pow = EEW_index_pow - EEW_data_pow + EMUL_data_pow; + let num_elem = get_num_elem(EMUL_data_pow, EEW_data_bytes * 8); /* number of data and indices are the same */ + let nf_int = nfields_int(nf); + + if illegal_indexed_store(nf_int, EEW_index_bytes * 8, EMUL_index_pow, EMUL_data_pow) then { handle_illegal(); return RETIRE_FAIL }; + + process_vsxseg(nf_int, vm, vs3, EEW_index_bytes, EEW_data_bytes, EMUL_index_pow, EMUL_data_pow, rs1, vs2, num_elem, 1) + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei16.v.yaml new file mode 100644 index 000000000000..ad6a058fbd0a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg2ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 001001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei32.v.yaml new file mode 100644 index 000000000000..83f88e526a79 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg2ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 001001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei64.v.yaml new file mode 100644 index 000000000000..12e6a6bb5a3d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg2ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 001001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei8.v.yaml new file mode 100644 index 000000000000..e81f0c61639c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg2ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg2ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 001001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei16.v.yaml new file mode 100644 index 000000000000..e8a093952eee --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg3ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 010001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei32.v.yaml new file mode 100644 index 000000000000..0b784dc923e5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg3ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 010001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei64.v.yaml new file mode 100644 index 000000000000..0217d174ed75 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg3ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 010001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei8.v.yaml new file mode 100644 index 000000000000..c2b310f25325 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg3ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg3ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 010001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei16.v.yaml new file mode 100644 index 000000000000..bf8121e0faa4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg4ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 011001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei32.v.yaml new file mode 100644 index 000000000000..902af2edcb36 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg4ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 011001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei64.v.yaml new file mode 100644 index 000000000000..99d344baa40b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg4ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 011001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei8.v.yaml new file mode 100644 index 000000000000..1a2dcdde3533 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg4ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg4ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 011001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei16.v.yaml new file mode 100644 index 000000000000..ff2e25caa683 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg5ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 100001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei32.v.yaml new file mode 100644 index 000000000000..bc19a4accdc6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg5ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 100001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei64.v.yaml new file mode 100644 index 000000000000..e7acf7d48520 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg5ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 100001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei8.v.yaml new file mode 100644 index 000000000000..05906984869d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg5ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg5ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 100001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei16.v.yaml new file mode 100644 index 000000000000..0811ac8569bd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg6ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 101001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei32.v.yaml new file mode 100644 index 000000000000..78d8f1dfd72a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg6ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 101001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei64.v.yaml new file mode 100644 index 000000000000..b7df93544981 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg6ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 101001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei8.v.yaml new file mode 100644 index 000000000000..21607fc31d1c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg6ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg6ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 101001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei16.v.yaml new file mode 100644 index 000000000000..db4b1bd6d93f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg7ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 110001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei32.v.yaml new file mode 100644 index 000000000000..0c01d8c57396 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg7ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 110001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei64.v.yaml new file mode 100644 index 000000000000..f2e12cd0cc67 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg7ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 110001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei8.v.yaml new file mode 100644 index 000000000000..0bfa255b7468 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg7ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg7ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 110001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei16.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei16.v.yaml new file mode 100644 index 000000000000..de795cea921d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei16.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg8ei16.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 111001-----------101-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei32.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei32.v.yaml new file mode 100644 index 000000000000..8a76e72867e3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei32.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg8ei32.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 111001-----------110-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei64.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei64.v.yaml new file mode 100644 index 000000000000..b5b78a7c6212 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei64.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg8ei64.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 111001-----------111-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei8.v.yaml new file mode 100644 index 000000000000..2c9dbc176902 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vsuxseg8ei8.v.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: vsuxseg8ei8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vs3, (xs1), vs2, vm +encoding: + match: 111001-----------000-----0100111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vs3 + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwadd.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwadd.vv.yaml new file mode 100644 index 000000000000..0734155dfdb4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwadd.vv.yaml @@ -0,0 +1,83 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwadd.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110001-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WVV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WVV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WVV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])), + WVV_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(vs1_val[i])), + WVV_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(vs1_val[i])), + WVV_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwadd.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwadd.vx.yaml new file mode 100644 index 000000000000..fa236802a428 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwadd.vx.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwadd.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 110001-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WVX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WVX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WVX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)), + WVX_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(rs1_val)), + WVX_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(rs1_val)), + WVX_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwadd.wv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwadd.wv.yaml new file mode 100644 index 000000000000..d511a200ff6c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwadd.wv.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwadd.wv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110101-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwadd.wx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwadd.wx.yaml new file mode 100644 index 000000000000..cd14203927f4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwadd.wx.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwadd.wx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 110101-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.vv.yaml new file mode 100644 index 000000000000..2018d20be28c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.vv.yaml @@ -0,0 +1,83 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwaddu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110000-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WVV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WVV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WVV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])), + WVV_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(vs1_val[i])), + WVV_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(vs1_val[i])), + WVV_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.vx.yaml new file mode 100644 index 000000000000..380263a23805 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.vx.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwaddu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 110000-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WVX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WVX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WVX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)), + WVX_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(rs1_val)), + WVX_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(rs1_val)), + WVX_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.wv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.wv.yaml new file mode 100644 index 000000000000..3a5afc47c12d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.wv.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwaddu.wv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110100-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.wx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.wx.yaml new file mode 100644 index 000000000000..a0f81a9affc4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwaddu.wx.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwaddu.wx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 110100-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmacc.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmacc.vv.yaml new file mode 100644 index 000000000000..aa6d4da469f2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmacc.vv.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmacc.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 111101-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WMVV_VWMACC => to_bits(SEW_widen, signed(vs1_val[i]) * signed(vs2_val[i])) + vd_val[i], + WMVV_VWMACCU => to_bits(SEW_widen, unsigned(vs1_val[i]) * unsigned(vs2_val[i])) + vd_val[i], + WMVV_VWMACCSU => to_bits(SEW_widen, signed(vs1_val[i]) * unsigned(vs2_val[i]))+ vd_val[i] + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmacc.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmacc.vx.yaml new file mode 100644 index 000000000000..327e76838c03 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmacc.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmacc.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, xs1, vs2, vm +encoding: + match: 111101-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WMVX_VWMACCU => (to_bits(SEW_widen, unsigned(rs1_val) * unsigned(vs2_val[i]) )) + vd_val[i], + WMVX_VWMACC => (to_bits(SEW_widen, signed(rs1_val) * signed(vs2_val[i]) )) + vd_val[i], + WMVX_VWMACCUS => (to_bits(SEW_widen, unsigned(rs1_val) * signed(vs2_val[i]) ))+ vd_val[i], + WMVX_VWMACCSU => (to_bits(SEW_widen, signed(rs1_val) * unsigned(vs2_val[i]) ))+ vd_val[i] + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmaccsu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmaccsu.vv.yaml new file mode 100644 index 000000000000..e67a446592a4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmaccsu.vv.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmaccsu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 111111-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WMVV_VWMACC => to_bits(SEW_widen, signed(vs1_val[i]) * signed(vs2_val[i])) + vd_val[i], + WMVV_VWMACCU => to_bits(SEW_widen, unsigned(vs1_val[i]) * unsigned(vs2_val[i])) + vd_val[i], + WMVV_VWMACCSU => to_bits(SEW_widen, signed(vs1_val[i]) * unsigned(vs2_val[i]))+ vd_val[i] + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmaccsu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmaccsu.vx.yaml new file mode 100644 index 000000000000..8a7ad3e93531 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmaccsu.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmaccsu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, xs1, vs2, vm +encoding: + match: 111111-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WMVX_VWMACCU => (to_bits(SEW_widen, unsigned(rs1_val) * unsigned(vs2_val[i]) )) + vd_val[i], + WMVX_VWMACC => (to_bits(SEW_widen, signed(rs1_val) * signed(vs2_val[i]) )) + vd_val[i], + WMVX_VWMACCUS => (to_bits(SEW_widen, unsigned(rs1_val) * signed(vs2_val[i]) ))+ vd_val[i], + WMVX_VWMACCSU => (to_bits(SEW_widen, signed(rs1_val) * unsigned(vs2_val[i]) ))+ vd_val[i] + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmaccu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmaccu.vv.yaml new file mode 100644 index 000000000000..cd7c4eb646bf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmaccu.vv.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmaccu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs1, vs2, vm +encoding: + match: 111100-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WMVV_VWMACC => to_bits(SEW_widen, signed(vs1_val[i]) * signed(vs2_val[i])) + vd_val[i], + WMVV_VWMACCU => to_bits(SEW_widen, unsigned(vs1_val[i]) * unsigned(vs2_val[i])) + vd_val[i], + WMVV_VWMACCSU => to_bits(SEW_widen, signed(vs1_val[i]) * unsigned(vs2_val[i]))+ vd_val[i] + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmaccu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmaccu.vx.yaml new file mode 100644 index 000000000000..3a6b2f07a5c0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmaccu.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmaccu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, xs1, vs2, vm +encoding: + match: 111100-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WMVX_VWMACCU => (to_bits(SEW_widen, unsigned(rs1_val) * unsigned(vs2_val[i]) )) + vd_val[i], + WMVX_VWMACC => (to_bits(SEW_widen, signed(rs1_val) * signed(vs2_val[i]) )) + vd_val[i], + WMVX_VWMACCUS => (to_bits(SEW_widen, unsigned(rs1_val) * signed(vs2_val[i]) ))+ vd_val[i], + WMVX_VWMACCSU => (to_bits(SEW_widen, signed(rs1_val) * unsigned(vs2_val[i]) ))+ vd_val[i] + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmaccus.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmaccus.vx.yaml new file mode 100644 index 000000000000..58806f908f77 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmaccus.vx.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmaccus.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, xs1, vs2, vm +encoding: + match: 111110-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WMVX_VWMACCU => (to_bits(SEW_widen, unsigned(rs1_val) * unsigned(vs2_val[i]) )) + vd_val[i], + WMVX_VWMACC => (to_bits(SEW_widen, signed(rs1_val) * signed(vs2_val[i]) )) + vd_val[i], + WMVX_VWMACCUS => (to_bits(SEW_widen, unsigned(rs1_val) * signed(vs2_val[i]) ))+ vd_val[i], + WMVX_VWMACCSU => (to_bits(SEW_widen, signed(rs1_val) * unsigned(vs2_val[i]) ))+ vd_val[i] + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmul.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmul.vv.yaml new file mode 100644 index 000000000000..21029ede1a09 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmul.vv.yaml @@ -0,0 +1,83 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmul.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 111011-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WVV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WVV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WVV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])), + WVV_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(vs1_val[i])), + WVV_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(vs1_val[i])), + WVV_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmul.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmul.vx.yaml new file mode 100644 index 000000000000..a99dea009f88 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmul.vx.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmul.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 111011-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WVX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WVX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WVX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)), + WVX_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(rs1_val)), + WVX_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(rs1_val)), + WVX_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmulsu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmulsu.vv.yaml new file mode 100644 index 000000000000..7fab9e2903da --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmulsu.vv.yaml @@ -0,0 +1,83 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmulsu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 111010-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WVV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WVV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WVV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])), + WVV_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(vs1_val[i])), + WVV_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(vs1_val[i])), + WVV_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmulsu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmulsu.vx.yaml new file mode 100644 index 000000000000..f75ebc0dc133 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmulsu.vx.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmulsu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 111010-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WVX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WVX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WVX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)), + WVX_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(rs1_val)), + WVX_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(rs1_val)), + WVX_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmulu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmulu.vv.yaml new file mode 100644 index 000000000000..7d2b208d88bb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmulu.vv.yaml @@ -0,0 +1,83 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmulu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 111000-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WVV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WVV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WVV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])), + WVV_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(vs1_val[i])), + WVV_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(vs1_val[i])), + WVV_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwmulu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwmulu.vx.yaml new file mode 100644 index 000000000000..cc065f230b66 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwmulu.vx.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwmulu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 111000-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WVX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WVX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WVX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)), + WVX_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(rs1_val)), + WVX_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(rs1_val)), + WVX_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwredsum.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwredsum.vs.yaml new file mode 100644 index 000000000000..fb9d2b218391 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwredsum.vs.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwredsum.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110001-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */ + + if illegal_reduction_widen(SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; + + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ + + let 'n = num_elem_vs; + let 'd = num_elem_vd; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + + sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */ + foreach (i from 0 to (num_elem_vs - 1)) { + if mask[i] then { + let elem : bits('o) = match funct6 { + IVV_VWREDSUMU => to_bits(SEW_widen, unsigned(vs2_val[i])), + IVV_VWREDSUM => to_bits(SEW_widen, signed(vs2_val[i])) + }; + sum = sum + elem + } + }; + + write_single_element(SEW_widen, 0, vd, sum); + /* other elements in vd are treated as tail elements, currently remain unchanged */ + /* TODO: configuration support for agnostic behavior */ + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwredsumu.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwredsumu.vs.yaml new file mode 100644 index 000000000000..8f64dece7d74 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwredsumu.vs.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwredsumu.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110000-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + let num_elem_vs = get_num_elem(LMUL_pow, SEW); + let num_elem_vd = get_num_elem(0, SEW_widen); /* vd regardless of LMUL setting */ + + if illegal_reduction_widen(SEW_widen, LMUL_pow_widen) then { handle_illegal(); return RETIRE_FAIL }; + + if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */ + + let 'n = num_elem_vs; + let 'd = num_elem_vd; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000); + let vd_val : vector('d, dec, bits('o)) = read_vreg(num_elem_vd, SEW_widen, 0, vd); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2); + let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val); + + sum : bits('o) = read_single_element(SEW_widen, 0, vs1); /* vs1 regardless of LMUL setting */ + foreach (i from 0 to (num_elem_vs - 1)) { + if mask[i] then { + let elem : bits('o) = match funct6 { + IVV_VWREDSUMU => to_bits(SEW_widen, unsigned(vs2_val[i])), + IVV_VWREDSUM => to_bits(SEW_widen, signed(vs2_val[i])) + }; + sum = sum + elem + } + }; + + write_single_element(SEW_widen, 0, vd, sum); + /* other elements in vd are treated as tail elements, currently remain unchanged */ + /* TODO: configuration support for agnostic behavior */ + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwsub.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwsub.vv.yaml new file mode 100644 index 000000000000..46a7afefbc03 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwsub.vv.yaml @@ -0,0 +1,83 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsub.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110011-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WVV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WVV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WVV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])), + WVV_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(vs1_val[i])), + WVV_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(vs1_val[i])), + WVV_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwsub.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwsub.vx.yaml new file mode 100644 index 000000000000..3101e8146f75 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwsub.vx.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsub.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 110011-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WVX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WVX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WVX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)), + WVX_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(rs1_val)), + WVX_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(rs1_val)), + WVX_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwsub.wv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwsub.wv.yaml new file mode 100644 index 000000000000..6ad74896e649 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwsub.wv.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsub.wv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110111-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwsub.wx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwsub.wx.yaml new file mode 100644 index 000000000000..fa9e7a720134 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwsub.wx.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsub.wx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 110111-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.vv.yaml new file mode 100644 index 000000000000..ac396ab861b2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.vv.yaml @@ -0,0 +1,83 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsubu.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110010-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WVV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WVV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WVV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])), + WVV_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(vs1_val[i])), + WVV_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(vs1_val[i])), + WVV_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.vx.yaml new file mode 100644 index 000000000000..aa099fe62c7b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.vx.yaml @@ -0,0 +1,82 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsubu.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 110010-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WVX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WVX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WVX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WVX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)), + WVX_VWMUL => to_bits(SEW_widen, signed(vs2_val[i]) * signed(rs1_val)), + WVX_VWMULU => to_bits(SEW_widen, unsigned(vs2_val[i]) * unsigned(rs1_val)), + WVX_VWMULSU => to_bits(SEW_widen, signed(vs2_val[i]) * unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.wv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.wv.yaml new file mode 100644 index 000000000000..58988360be29 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.wv.yaml @@ -0,0 +1,79 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsubu.wv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 110110-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) | + not(valid_reg_overlap(vs1, vd, LMUL_pow, LMUL_pow_widen)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WV_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(vs1_val[i])), + WV_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(vs1_val[i])), + WV_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(vs1_val[i])), + WV_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(vs1_val[i])) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.wx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.wx.yaml new file mode 100644 index 000000000000..404c18c293e7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vwsubu.wx.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsubu.wx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 110110-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_widen = SEW * 2; + let LMUL_pow_widen = LMUL_pow + 1; + + if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_widen; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2); + result : vector('n, dec, bits('o)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + WX_VADD => to_bits(SEW_widen, signed(vs2_val[i]) + signed(rs1_val)), + WX_VSUB => to_bits(SEW_widen, signed(vs2_val[i]) - signed(rs1_val)), + WX_VADDU => to_bits(SEW_widen, unsigned(vs2_val[i]) + unsigned(rs1_val)), + WX_VSUBU => to_bits(SEW_widen, unsigned(vs2_val[i]) - unsigned(rs1_val)) + } + } + }; + + write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vxor.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vxor.vi.yaml new file mode 100644 index 000000000000..15fb0e21330b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vxor.vi.yaml @@ -0,0 +1,101 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vxor.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, imm, vm +encoding: + match: 001011-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let imm_val : bits('m) = sign_extend(simm); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VI_VADD => vs2_val[i] + imm_val, + VI_VRSUB => imm_val - vs2_val[i], + VI_VAND => vs2_val[i] & imm_val, + VI_VOR => vs2_val[i] | imm_val, + VI_VXOR => vs2_val[i] ^ imm_val, + VI_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, imm_val) ), + VI_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, imm_val) ), + VI_VSLL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] << shift_amount + }, + VI_VSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + vs2_val[i] >> shift_amount + }, + VI_VSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VI_VSSRL => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VI_VSSRA => { + let shift_amount = get_shift_amount(zero_extend('m, simm), SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vxor.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vxor.vv.yaml new file mode 100644 index 000000000000..983156f61518 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vxor.vv.yaml @@ -0,0 +1,134 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vxor.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vs1, vm +encoding: + match: 001011-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW_pow = get_sew_pow(); + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let VLEN_pow = get_vlen_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VV_VADD => vs2_val[i] + vs1_val[i], + VV_VSUB => vs2_val[i] - vs1_val[i], + VV_VAND => vs2_val[i] & vs1_val[i], + VV_VOR => vs2_val[i] | vs1_val[i], + VV_VXOR => vs2_val[i] ^ vs1_val[i], + VV_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i])), + VV_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i])), + VV_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(vs1_val[i]) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i])) + }, + VV_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i])), + VV_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(vs1_val[i])); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VV_VSLL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] << shift_amount + }, + VV_VSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + vs2_val[i] >> shift_amount + }, + VV_VSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VV_VSSRL => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VV_VSSRA => { + let shift_amount = get_shift_amount(vs1_val[i], SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VV_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(vs1_val[i]))), + VV_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(vs1_val[i]))), + VV_VRGATHER => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + let idx = unsigned(vs1_val[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + }, + VV_VRGATHEREI16 => { + if (vs1 == vd | vs2 == vd) then { handle_illegal(); return RETIRE_FAIL }; + /* vrgatherei16.vv uses SEW/LMUL for the data in vs2 but EEW=16 and EMUL = (16/SEW)*LMUL for the indices in vs1 */ + let vs1_new : vector('n, dec, bits(16)) = read_vreg(num_elem, 16, 4 + LMUL_pow - SEW_pow, vs1); + let idx = unsigned(vs1_new[i]); + let VLMAX = int_power(2, LMUL_pow + VLEN_pow - SEW_pow); + assert(VLMAX <= 'n); + if idx < VLMAX then vs2_val[idx] else zeros() + } + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vxor.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vxor.vx.yaml new file mode 100644 index 000000000000..0b687d97dba7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vxor.vx.yaml @@ -0,0 +1,117 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vxor.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, xs1, vm +encoding: + match: 001011-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + + if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let rs1_val : bits('m) = get_scalar(rs1, SEW); + let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VX_VADD => vs2_val[i] + rs1_val, + VX_VSUB => vs2_val[i] - rs1_val, + VX_VRSUB => rs1_val - vs2_val[i], + VX_VAND => vs2_val[i] & rs1_val, + VX_VOR => vs2_val[i] | rs1_val, + VX_VXOR => vs2_val[i] ^ rs1_val, + VX_VSADDU => unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, rs1_val) ), + VX_VSADD => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, rs1_val) ), + VX_VSSUBU => { + if unsigned(vs2_val[i]) < unsigned(rs1_val) then zeros() + else unsigned_saturation('m, zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, rs1_val) ) + }, + VX_VSSUB => signed_saturation('m, sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, rs1_val) ), + VX_VSMUL => { + let result_mul = to_bits('m * 2, signed(vs2_val[i]) * signed(rs1_val)); + let rounding_incr = get_fixed_rounding_incr(result_mul, 'm - 1); + let result_wide = (result_mul >> ('m - 1)) + zero_extend('m * 2, rounding_incr); + signed_saturation('m, result_wide['m..0]) + }, + VX_VSLL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] << shift_amount + }, + VX_VSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + vs2_val[i] >> shift_amount + }, + VX_VSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + }, + VX_VSSRL => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + (vs2_val[i] >> shift_amount) + zero_extend('m, rounding_incr) + }, + VX_VSSRA => { + let shift_amount = get_shift_amount(rs1_val, SEW); + let rounding_incr = get_fixed_rounding_incr(vs2_val[i], shift_amount); + let v_double : bits('m * 2) = sign_extend(vs2_val[i]); + slice(v_double >> shift_amount, 0, SEW) + zero_extend('m, rounding_incr) + }, + VX_VMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(rs1_val))), + VX_VMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(rs1_val))), + VX_VMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(rs1_val))) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vzext.vf2.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vzext.vf2.yaml new file mode 100644 index 000000000000..e7f931959084 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vzext.vf2.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vzext.vf2 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00110010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_half = SEW / 2; + let LMUL_pow_half = LMUL_pow - 1; + + if illegal_variable_width(vd, vm, SEW_half, LMUL_pow_half) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_half, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_half; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_half, LMUL_pow_half, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW > SEW_half); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VEXT2_ZVF2 => zero_extend(vs2_val[i]), + VEXT2_SVF2 => sign_extend(vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vzext.vf4.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vzext.vf4.yaml new file mode 100644 index 000000000000..6e991faa0e65 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vzext.vf4.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vzext.vf4 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00100010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_quart = SEW / 4; + let LMUL_pow_quart = LMUL_pow - 2; + + if illegal_variable_width(vd, vm, SEW_quart, LMUL_pow_quart) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_quart, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_quart; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_quart, LMUL_pow_quart, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW > SEW_quart); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VEXT4_ZVF4 => zero_extend(vs2_val[i]), + VEXT4_SVF4 => sign_extend(vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/V/vzext.vf8.yaml b/pkg/ifuzz/riscv64/gen/inst/V/vzext.vf8.yaml new file mode 100644 index 000000000000..6fa4d1676964 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/V/vzext.vf8.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vzext.vf8 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: V +assembly: vd, vs2, vm +encoding: + match: 010010------00010010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let SEW = get_sew(); + let LMUL_pow = get_lmul_pow(); + let num_elem = get_num_elem(LMUL_pow, SEW); + let SEW_eighth = SEW / 8; + let LMUL_pow_eighth = LMUL_pow - 3; + + if illegal_variable_width(vd, vm, SEW_eighth, LMUL_pow_eighth) | + not(valid_reg_overlap(vs2, vd, LMUL_pow_eighth, LMUL_pow)) + then { handle_illegal(); return RETIRE_FAIL }; + + let 'n = num_elem; + let 'm = SEW; + let 'o = SEW_eighth; + + let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000); + let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd); + let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_eighth, LMUL_pow_eighth, vs2); + result : vector('n, dec, bits('m)) = undefined; + mask : vector('n, dec, bool) = undefined; + + (result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val); + + assert(SEW > SEW_eighth); + foreach (i from 0 to (num_elem - 1)) { + if mask[i] then { + result[i] = match funct6 { + VEXT8_ZVF8 => zero_extend(vs2_val[i]), + VEXT8_SVF8 => sign_extend(vs2_val[i]) + } + } + }; + + write_vreg(num_elem, SEW, LMUL_pow, vd, result); + vstart = zeros(); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.SIZE.AQRL.layout b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.SIZE.AQRL.layout new file mode 100644 index 000000000000..8c3631cfded2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.SIZE.AQRL.layout @@ -0,0 +1,181 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +<%- + raise "'size' must be defined as 'b', 'h', 'w', or 'd'" unless %w[b h w d].include?(size) + raise "'aq' must be defined as true or false" unless [true, false].include?(aq) + raise "'rl' must be defined as true or false" unless [true, false].include?(rl) + + size_info = { + "b" => { name: "byte", bits: 8, funct3: "000", operation_bits: "8" }, + "h" => { name: "halfword", bits: 16, funct3: "001", operation_bits: "16" }, + "w" => { name: "word", bits: 32, funct3: "010", operation_bits: "32" }, + "d" => { name: "doubleword", bits: 64, funct3: "011", operation_bits: "64" } + } + + current_size = size_info[size] + + # Generate instruction name suffix based on aq/rl + aq_rl_suffix = "" + if aq && rl + aq_rl_suffix = ".aqrl" + elsif aq + aq_rl_suffix = ".aq" + elsif rl + aq_rl_suffix = ".rl" + end + + # Generate match string with fixed aq/rl bits + aq_bit = aq ? "1" : "0" + rl_bit = rl ? "1" : "0" +-%> + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.<%= size %><%= aq_rl_suffix %> +long_name: Atomic fetch-and-add <%= current_size[:name] %><%= aq && rl ? " (acquire-release)" : (aq ? " (acquire)" : (rl ? " (release)" : "")) %> +description: | + Atomically<%= aq && rl ? " with acquire and release ordering" : (aq ? " with acquire ordering" : (rl ? " with release ordering" : "")) %>: + + * Load the <%= current_size[:name] %> at address _xs1_ + * Write the <%= %w[b h w].include?(size) ? "sign-extended value" : "loaded value" %> into _xd_ + * Add the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: +<%- if size == "d" -%> + allOf: + - extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> + - xlen: 64 +<%- else -%> + extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> +<%- end -%> +assembly: xd, xs2, (xs1) +encoding: + match: 00000<%= aq_bit %><%= rl_bit %>----------<%= current_size[:funct3] %>-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + +<% if aq -%> + memory_model_acquire(); + +<% end -%> + XReg virtual_address = X[xs1]; + X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Add, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding); +<% if rl -%> + + memory_model_release(); +<% end -%> + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.aq.yaml new file mode 100644 index 000000000000..3747ffa57f29 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.aq.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.d.aq +long_name: Atomic fetch-and-add doubleword (acquire) +description: | + Atomically with acquire ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Add the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0000010----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Add, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.aqrl.yaml new file mode 100644 index 000000000000..eb277cdff41c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.aqrl.yaml @@ -0,0 +1,147 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.d.aqrl +long_name: Atomic fetch-and-add doubleword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Add the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0000011----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Add, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.rl.yaml new file mode 100644 index 000000000000..afc66dfb9975 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.rl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.d.rl +long_name: Atomic fetch-and-add doubleword (release) +description: | + Atomically with release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Add the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0000001----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Add, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.yaml new file mode 100644 index 000000000000..d91d9ffb2f61 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.d.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.d +long_name: Atomic fetch-and-add doubleword +description: | + Atomically: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Add the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0000000----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Add, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.aq.yaml new file mode 100644 index 000000000000..da5a655f7b15 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.w.aq +long_name: Atomic fetch-and-add word (acquire) +description: | + Atomically with acquire ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0000010----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.aqrl.yaml new file mode 100644 index 000000000000..b211f45c8b2f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.w.aqrl +long_name: Atomic fetch-and-add word (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0000011----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.rl.yaml new file mode 100644 index 000000000000..813e4e24c700 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.w.rl +long_name: Atomic fetch-and-add word (release) +description: | + Atomically with release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0000001----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.yaml new file mode 100644 index 000000000000..3ad9c4314b43 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoadd.w.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.w +long_name: Atomic fetch-and-add word +description: | + Atomically: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0000000----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Add, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.SIZE.AQRL.layout b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.SIZE.AQRL.layout new file mode 100644 index 000000000000..24136db8e78d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.SIZE.AQRL.layout @@ -0,0 +1,181 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +<%- + raise "'size' must be defined as 'b', 'h', 'w', or 'd'" unless %w[b h w d].include?(size) + raise "'aq' must be defined as true or false" unless [true, false].include?(aq) + raise "'rl' must be defined as true or false" unless [true, false].include?(rl) + + size_info = { + "b" => { name: "byte", bits: 8, funct3: "000", operation_bits: "8" }, + "h" => { name: "halfword", bits: 16, funct3: "001", operation_bits: "16" }, + "w" => { name: "word", bits: 32, funct3: "010", operation_bits: "32" }, + "d" => { name: "doubleword", bits: 64, funct3: "011", operation_bits: "64" } + } + + current_size = size_info[size] + + # Generate instruction name suffix based on aq/rl + aq_rl_suffix = "" + if aq && rl + aq_rl_suffix = ".aqrl" + elsif aq + aq_rl_suffix = ".aq" + elsif rl + aq_rl_suffix = ".rl" + end + + # Generate match string with fixed aq/rl bits + aq_bit = aq ? "1" : "0" + rl_bit = rl ? "1" : "0" +-%> + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.<%= size %><%= aq_rl_suffix %> +long_name: Atomic fetch-and-and <%= current_size[:name] %><%= aq && rl ? " (acquire-release)" : (aq ? " (acquire)" : (rl ? " (release)" : "")) %> +description: | + Atomically<%= aq && rl ? " with acquire and release ordering" : (aq ? " with acquire ordering" : (rl ? " with release ordering" : "")) %>: + + * Load the <%= current_size[:name] %> at address _xs1_ + * Write the <%= %w[b h w].include?(size) ? "sign-extended value" : "loaded value" %> into _xd_ + * AND the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: +<%- if size == "d" -%> + allOf: + - extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> + - xlen: 64 +<%- else -%> + extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> +<%- end -%> +assembly: xd, xs2, (xs1) +encoding: + match: 01100<%= aq_bit %><%= rl_bit %>----------<%= current_size[:funct3] %>-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + +<% if aq -%> + memory_model_acquire(); + +<% end -%> + XReg virtual_address = X[xs1]; + X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::And, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding); +<% if rl -%> + + memory_model_release(); +<% end -%> + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.aq.yaml new file mode 100644 index 000000000000..8e8fc8a4afe5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.aq.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.d.aq +long_name: Atomic fetch-and-and doubleword (acquire) +description: | + Atomically with acquire ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * AND the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0110010----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::And, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.aqrl.yaml new file mode 100644 index 000000000000..e3878a62dd4f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.aqrl.yaml @@ -0,0 +1,147 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.d.aqrl +long_name: Atomic fetch-and-and doubleword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * AND the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0110011----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::And, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.rl.yaml new file mode 100644 index 000000000000..950e5cdd6cc3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.rl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.d.rl +long_name: Atomic fetch-and-and doubleword (release) +description: | + Atomically with release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * AND the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0110001----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::And, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.yaml new file mode 100644 index 000000000000..cf5bee46772b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.d.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.d +long_name: Atomic fetch-and-and doubleword +description: | + Atomically: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * AND the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0110000----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::And, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.aq.yaml new file mode 100644 index 000000000000..bfd980d72c99 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.w.aq +long_name: Atomic fetch-and-and word (acquire) +description: | + Atomically with acquire ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0110010----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::And, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.aqrl.yaml new file mode 100644 index 000000000000..270ed7fb7cb4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.w.aqrl +long_name: Atomic fetch-and-and word (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0110011----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::And, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.rl.yaml new file mode 100644 index 000000000000..bffad0a517be --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.w.rl +long_name: Atomic fetch-and-and word (release) +description: | + Atomically with release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0110001----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::And, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.yaml new file mode 100644 index 000000000000..e49cbb24a808 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoand.w.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.w +long_name: Atomic fetch-and-and word +description: | + Atomically: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0110000----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::And, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.SIZE.AQRL.layout b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.SIZE.AQRL.layout new file mode 100644 index 000000000000..1039f3463561 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.SIZE.AQRL.layout @@ -0,0 +1,181 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +<%- + raise "'size' must be defined as 'b', 'h', 'w', or 'd'" unless %w[b h w d].include?(size) + raise "'aq' must be defined as true or false" unless [true, false].include?(aq) + raise "'rl' must be defined as true or false" unless [true, false].include?(rl) + + size_info = { + "b" => { name: "byte", bits: 8, funct3: "000", operation_bits: "8" }, + "h" => { name: "halfword", bits: 16, funct3: "001", operation_bits: "16" }, + "w" => { name: "word", bits: 32, funct3: "010", operation_bits: "32" }, + "d" => { name: "doubleword", bits: 64, funct3: "011", operation_bits: "64" } + } + + current_size = size_info[size] + + # Generate instruction name suffix based on aq/rl + aq_rl_suffix = "" + if aq && rl + aq_rl_suffix = ".aqrl" + elsif aq + aq_rl_suffix = ".aq" + elsif rl + aq_rl_suffix = ".rl" + end + + # Generate match string with fixed aq/rl bits + aq_bit = aq ? "1" : "0" + rl_bit = rl ? "1" : "0" +-%> + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.<%= size %><%= aq_rl_suffix %> +long_name: Atomic MAX <%= current_size[:name] %><%= aq && rl ? " (acquire-release)" : (aq ? " (acquire)" : (rl ? " (release)" : "")) %> +description: | + Atomically<%= aq && rl ? " with acquire and release ordering" : (aq ? " with acquire ordering" : (rl ? " with release ordering" : "")) %>: + + * Load the <%= current_size[:name] %> at address _xs1_ + * Write the <%= %w[b h w].include?(size) ? "sign-extended value" : "loaded value" %> into _xd_ + * Signed compare the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: +<%- if size == "d" -%> + allOf: + - extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> + - xlen: 64 +<%- else -%> + extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> +<%- end -%> +assembly: xd, xs2, (xs1) +encoding: + match: 10100<%= aq_bit %><%= rl_bit %>----------<%= current_size[:funct3] %>-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + +<% if aq -%> + memory_model_acquire(); + +<% end -%> + XReg virtual_address = X[xs1]; + X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Max, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding); +<% if rl -%> + + memory_model_release(); +<% end -%> + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.aq.yaml new file mode 100644 index 000000000000..481e50b04f00 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.aq.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.d.aq +long_name: Atomic MAX doubleword (acquire) +description: | + Atomically with acquire ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Signed compare the value of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1010010----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Max, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.aqrl.yaml new file mode 100644 index 000000000000..abf083ef0599 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.aqrl.yaml @@ -0,0 +1,147 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.d.aqrl +long_name: Atomic MAX doubleword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Signed compare the value of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1010011----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Max, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.rl.yaml new file mode 100644 index 000000000000..7d6b58aa24e0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.rl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.d.rl +long_name: Atomic MAX doubleword (release) +description: | + Atomically with release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Signed compare the value of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1010001----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Max, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.yaml new file mode 100644 index 000000000000..ee6732407a33 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.d.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.d +long_name: Atomic MAX doubleword +description: | + Atomically: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Signed compare the value of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1010000----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Max, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.aq.yaml new file mode 100644 index 000000000000..d86018994e32 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.w.aq +long_name: Atomic MAX word (acquire) +description: | + Atomically with acquire ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant word of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1010010----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.aqrl.yaml new file mode 100644 index 000000000000..7335ab32f4af --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.w.aqrl +long_name: Atomic MAX word (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant word of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1010011----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.rl.yaml new file mode 100644 index 000000000000..6cb92dc6559e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.w.rl +long_name: Atomic MAX word (release) +description: | + Atomically with release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant word of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1010001----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.yaml new file mode 100644 index 000000000000..eba8870661c7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomax.w.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.w +long_name: Atomic MAX word +description: | + Atomically: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant word of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1010000----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Max, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.SIZE.AQRL.layout b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.SIZE.AQRL.layout new file mode 100644 index 000000000000..ad740b257766 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.SIZE.AQRL.layout @@ -0,0 +1,181 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +<%- + raise "'size' must be defined as 'b', 'h', 'w', or 'd'" unless %w[b h w d].include?(size) + raise "'aq' must be defined as true or false" unless [true, false].include?(aq) + raise "'rl' must be defined as true or false" unless [true, false].include?(rl) + + size_info = { + "b" => { name: "byte", bits: 8, funct3: "000", operation_bits: "8" }, + "h" => { name: "halfword", bits: 16, funct3: "001", operation_bits: "16" }, + "w" => { name: "word", bits: 32, funct3: "010", operation_bits: "32" }, + "d" => { name: "doubleword", bits: 64, funct3: "011", operation_bits: "64" } + } + + current_size = size_info[size] + + # Generate instruction name suffix based on aq/rl + aq_rl_suffix = "" + if aq && rl + aq_rl_suffix = ".aqrl" + elsif aq + aq_rl_suffix = ".aq" + elsif rl + aq_rl_suffix = ".rl" + end + + # Generate match string with fixed aq/rl bits + aq_bit = aq ? "1" : "0" + rl_bit = rl ? "1" : "0" +-%> + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.<%= size %><%= aq_rl_suffix %> +long_name: Atomic MAX unsigned <%= current_size[:name] %><%= aq && rl ? " (acquire-release)" : (aq ? " (acquire)" : (rl ? " (release)" : "")) %> +description: | + Atomically<%= aq && rl ? " with acquire and release ordering" : (aq ? " with acquire ordering" : (rl ? " with release ordering" : "")) %>: + + * Load the <%= current_size[:name] %> at address _xs1_ + * Write the <%= %w[b h w].include?(size) ? "sign-extended value" : "loaded value" %> into _xd_ + * Unsigned compare the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: +<%- if size == "d" -%> + allOf: + - extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> + - xlen: 64 +<%- else -%> + extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> +<%- end -%> +assembly: xd, xs2, (xs1) +encoding: + match: 11100<%= aq_bit %><%= rl_bit %>----------<%= current_size[:funct3] %>-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + +<% if aq -%> + memory_model_acquire(); + +<% end -%> + XReg virtual_address = X[xs1]; + X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Maxu, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding); +<% if rl -%> + + memory_model_release(); +<% end -%> + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, <%= rl ? "true" : "false" %>, true), + (HALF, _) => mem_write_ea(addr, 2, <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, <%= rl ? "true" : "false" %>, true), + (WORD, _) => mem_write_ea(addr, 4, <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, <%= rl ? "true" : "false" %>, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, <%= rl ? "true" : "false" %>, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, <%= aq ? "true" : "false" %>, <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, <%= aq ? "true" : "false" %>, <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, <%= aq ? "true" : "false" %>, <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, <%= aq ? "true" : "false" %>, <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, <%= rl ? "true" : "false" %>, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, <%= rl ? "true" : "false" %>, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, <%= rl ? "true" : "false" %>, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, <%= aq ? "true" : "false" %> & <%= rl ? "true" : "false" %>, <%= rl ? "true" : "false" %>, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.aq.yaml new file mode 100644 index 000000000000..afb1b313df4d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.aq.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.d.aq +long_name: Atomic MAX unsigned doubleword (acquire) +description: | + Atomically with acquire ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Unsigned compare the value of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1110010----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Maxu, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, true & false, false, true), + (HALF, _) => mem_write_ea(addr, 2, true & false, false, true), + (WORD, _) => mem_write_ea(addr, 4, true & false, false, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, true & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, true, true & false, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, true, true & false, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, true, true & false, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, true, true & false, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], true & false, false, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], true & false, false, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], true & false, false, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, true & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.aqrl.yaml new file mode 100644 index 000000000000..a533b2d32cde --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.aqrl.yaml @@ -0,0 +1,147 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.d.aqrl +long_name: Atomic MAX unsigned doubleword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Unsigned compare the value of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1110011----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Maxu, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, true & true, true, true), + (HALF, _) => mem_write_ea(addr, 2, true & true, true, true), + (WORD, _) => mem_write_ea(addr, 4, true & true, true, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, true & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, true, true & true, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, true, true & true, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, true, true & true, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, true, true & true, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], true & true, true, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], true & true, true, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], true & true, true, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, true & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.rl.yaml new file mode 100644 index 000000000000..d36afeaa2984 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.rl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.d.rl +long_name: Atomic MAX unsigned doubleword (release) +description: | + Atomically with release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Unsigned compare the value of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1110001----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Maxu, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, false & true, true, true), + (HALF, _) => mem_write_ea(addr, 2, false & true, true, true), + (WORD, _) => mem_write_ea(addr, 4, false & true, true, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, false & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, false, false & true, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, false, false & true, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, false, false & true, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, false, false & true, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], false & true, true, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], false & true, true, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], false & true, true, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, false & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.yaml new file mode 100644 index 000000000000..80b1ae2151d6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.d.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.d +long_name: Atomic MAX unsigned doubleword +description: | + Atomically: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Unsigned compare the value of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1110000----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Maxu, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, false & false, false, true), + (HALF, _) => mem_write_ea(addr, 2, false & false, false, true), + (WORD, _) => mem_write_ea(addr, 4, false & false, false, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, false & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, false, false & false, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, false, false & false, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, false, false & false, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, false, false & false, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], false & false, false, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], false & false, false, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], false & false, false, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, false & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.aq.yaml new file mode 100644 index 000000000000..458911e8eb04 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.w.aq +long_name: Atomic MAX unsigned word (acquire) +description: | + Atomically with acquire ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant word of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1110010----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, true & false, false, true), + (HALF, _) => mem_write_ea(addr, 2, true & false, false, true), + (WORD, _) => mem_write_ea(addr, 4, true & false, false, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, true & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, true, true & false, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, true, true & false, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, true, true & false, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, true, true & false, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], true & false, false, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], true & false, false, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], true & false, false, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, true & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.aqrl.yaml new file mode 100644 index 000000000000..165fa0c1a82e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.w.aqrl +long_name: Atomic MAX unsigned word (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant word of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1110011----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, true & true, true, true), + (HALF, _) => mem_write_ea(addr, 2, true & true, true, true), + (WORD, _) => mem_write_ea(addr, 4, true & true, true, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, true & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, true, true & true, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, true, true & true, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, true, true & true, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, true, true & true, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], true & true, true, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], true & true, true, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], true & true, true, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, true & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.rl.yaml new file mode 100644 index 000000000000..95b5a37c6858 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.w.rl +long_name: Atomic MAX unsigned word (release) +description: | + Atomically with release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant word of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1110001----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, false & true, true, true), + (HALF, _) => mem_write_ea(addr, 2, false & true, true, true), + (WORD, _) => mem_write_ea(addr, 4, false & true, true, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, false & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, false, false & true, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, false, false & true, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, false, false & true, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, false, false & true, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], false & true, true, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], false & true, true, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], false & true, true, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, false & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.yaml new file mode 100644 index 000000000000..f45fbccf2361 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomaxu.w.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.w +long_name: Atomic MAX unsigned word +description: | + Atomically: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant word of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1110000----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Maxu, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, false & false, false, true), + (HALF, _) => mem_write_ea(addr, 2, false & false, false, true), + (WORD, _) => mem_write_ea(addr, 4, false & false, false, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, false & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, false, false & false, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, false, false & false, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, false, false & false, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, false, false & false, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], false & false, false, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], false & false, false, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], false & false, false, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, false & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.SIZE.AQRL.layout b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.SIZE.AQRL.layout new file mode 100644 index 000000000000..e88ea2b92d86 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.SIZE.AQRL.layout @@ -0,0 +1,181 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +<%- + raise "'size' must be defined as 'b', 'h', 'w', or 'd'" unless %w[b h w d].include?(size) + raise "'aq' must be defined as true or false" unless [true, false].include?(aq) + raise "'rl' must be defined as true or false" unless [true, false].include?(rl) + + size_info = { + "b" => { name: "byte", bits: 8, funct3: "000", operation_bits: "8" }, + "h" => { name: "halfword", bits: 16, funct3: "001", operation_bits: "16" }, + "w" => { name: "word", bits: 32, funct3: "010", operation_bits: "32" }, + "d" => { name: "doubleword", bits: 64, funct3: "011", operation_bits: "64" } + } + + current_size = size_info[size] + + # Generate instruction name suffix based on aq/rl + aq_rl_suffix = "" + if aq && rl + aq_rl_suffix = ".aqrl" + elsif aq + aq_rl_suffix = ".aq" + elsif rl + aq_rl_suffix = ".rl" + end + + # Generate match string with fixed aq/rl bits + aq_bit = aq ? "1" : "0" + rl_bit = rl ? "1" : "0" +-%> + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.<%= size %><%= aq_rl_suffix %> +long_name: Atomic MIN <%= current_size[:name] %><%= aq && rl ? " (acquire-release)" : (aq ? " (acquire)" : (rl ? " (release)" : "")) %> +description: | + Atomically<%= aq && rl ? " with acquire and release ordering" : (aq ? " with acquire ordering" : (rl ? " with release ordering" : "")) %>: + + * Load the <%= current_size[:name] %> at address _xs1_ + * Write the <%= %w[b h w].include?(size) ? "sign-extended value" : "loaded value" %> into _xd_ + * Signed compare the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: +<%- if size == "d" -%> + allOf: + - extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> + - xlen: 64 +<%- else -%> + extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> +<%- end -%> +assembly: xd, xs2, (xs1) +encoding: + match: 10000<%= aq_bit %><%= rl_bit %>----------<%= current_size[:funct3] %>-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + +<% if aq -%> + memory_model_acquire(); + +<% end -%> + XReg virtual_address = X[xs1]; + X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Min, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding); +<% if rl -%> + + memory_model_release(); +<% end -%> + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.aq.yaml new file mode 100644 index 000000000000..f697b36b9fdd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.aq.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.d.aq +long_name: Atomic MIN doubleword (acquire) +description: | + Atomically with acquire ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Signed compare the value of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1000010----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Min, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.aqrl.yaml new file mode 100644 index 000000000000..91543eb0f93a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.aqrl.yaml @@ -0,0 +1,147 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.d.aqrl +long_name: Atomic MIN doubleword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Signed compare the value of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1000011----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Min, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.rl.yaml new file mode 100644 index 000000000000..f96a19be7710 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.rl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.d.rl +long_name: Atomic MIN doubleword (release) +description: | + Atomically with release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Signed compare the value of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1000001----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Min, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.yaml new file mode 100644 index 000000000000..fd0f75a6fb17 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.d.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.d +long_name: Atomic MIN doubleword +description: | + Atomically: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Signed compare the value of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1000000----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Min, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.aq.yaml new file mode 100644 index 000000000000..257087671b57 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.w.aq +long_name: Atomic MIN word (acquire) +description: | + Atomically with acquire ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant word of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1000010----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.aqrl.yaml new file mode 100644 index 000000000000..d3fa8f27ca7a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.w.aqrl +long_name: Atomic MIN word (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant word of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1000011----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.rl.yaml new file mode 100644 index 000000000000..c32bdbbdd800 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.w.rl +long_name: Atomic MIN word (release) +description: | + Atomically with release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant word of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1000001----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.yaml new file mode 100644 index 000000000000..6055ef1ee1e8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amomin.w.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.w +long_name: Atomic MIN word +description: | + Atomically: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant word of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1000000----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Min, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.SIZE.AQRL.layout b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.SIZE.AQRL.layout new file mode 100644 index 000000000000..5ea331a09398 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.SIZE.AQRL.layout @@ -0,0 +1,181 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +<%- + raise "'size' must be defined as 'b', 'h', 'w', or 'd'" unless %w[b h w d].include?(size) + raise "'aq' must be defined as true or false" unless [true, false].include?(aq) + raise "'rl' must be defined as true or false" unless [true, false].include?(rl) + + size_info = { + "b" => { name: "byte", bits: 8, funct3: "000", operation_bits: "8" }, + "h" => { name: "halfword", bits: 16, funct3: "001", operation_bits: "16" }, + "w" => { name: "word", bits: 32, funct3: "010", operation_bits: "32" }, + "d" => { name: "doubleword", bits: 64, funct3: "011", operation_bits: "64" } + } + + current_size = size_info[size] + + # Generate instruction name suffix based on aq/rl + aq_rl_suffix = "" + if aq && rl + aq_rl_suffix = ".aqrl" + elsif aq + aq_rl_suffix = ".aq" + elsif rl + aq_rl_suffix = ".rl" + end + + # Generate match string with fixed aq/rl bits + aq_bit = aq ? "1" : "0" + rl_bit = rl ? "1" : "0" +-%> + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.<%= size %><%= aq_rl_suffix %> +long_name: Atomic MIN unsigned <%= current_size[:name] %><%= aq && rl ? " (acquire-release)" : (aq ? " (acquire)" : (rl ? " (release)" : "")) %> +description: | + Atomically<%= aq && rl ? " with acquire and release ordering" : (aq ? " with acquire ordering" : (rl ? " with release ordering" : "")) %>: + + * Load the <%= current_size[:name] %> at address _xs1_ + * Write the <%= %w[b h w].include?(size) ? "sign-extended value" : "loaded value" %> into _xd_ + * Unsigned compare the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: +<%- if size == "d" -%> + allOf: + - extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> + - xlen: 64 +<%- else -%> + extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> +<%- end -%> +assembly: xd, xs2, (xs1) +encoding: + match: 11000<%= aq_bit %><%= rl_bit %>----------<%= current_size[:funct3] %>-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + +<% if aq -%> + memory_model_acquire(); + +<% end -%> + XReg virtual_address = X[xs1]; + X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Minu, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding); +<% if rl -%> + + memory_model_release(); +<% end -%> + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.aq.yaml new file mode 100644 index 000000000000..3ee36efd347d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.aq.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.d.aq +long_name: Atomic MIN unsigned doubleword (acquire) +description: | + Atomically with acquire ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Unsigned compare the value of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1100010----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Minu, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.aqrl.yaml new file mode 100644 index 000000000000..2775df619410 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.aqrl.yaml @@ -0,0 +1,147 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.d.aqrl +long_name: Atomic MIN unsigned doubleword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Unsigned compare the value of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1100011----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Minu, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.rl.yaml new file mode 100644 index 000000000000..37cfd63880a6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.rl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.d.rl +long_name: Atomic MIN unsigned doubleword (release) +description: | + Atomically with release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Unsigned compare the value of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1100001----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Minu, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.yaml new file mode 100644 index 000000000000..a5272eae7ce0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.d.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.d +long_name: Atomic MIN unsigned doubleword +description: | + Atomically: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Unsigned compare the value of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 1100000----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Minu, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.aq.yaml new file mode 100644 index 000000000000..80ba63aa6577 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.w.aq +long_name: Atomic MIN unsigned word (acquire) +description: | + Atomically with acquire ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant word of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1100010----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Minu, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.aqrl.yaml new file mode 100644 index 000000000000..ab38159559a5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.w.aqrl +long_name: Atomic MIN unsigned word (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant word of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1100011----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Minu, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.rl.yaml new file mode 100644 index 000000000000..9a1cb8f4e6f9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.w.rl +long_name: Atomic MIN unsigned word (release) +description: | + Atomically with release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant word of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1100001----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Minu, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.yaml new file mode 100644 index 000000000000..74524618c927 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amominu.w.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.w +long_name: Atomic MIN unsigned word +description: | + Atomically: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant word of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 1100000----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Minu, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.SIZE.AQRL.layout b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.SIZE.AQRL.layout new file mode 100644 index 000000000000..2d2b186fb284 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.SIZE.AQRL.layout @@ -0,0 +1,181 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +<%- + raise "'size' must be defined as 'b', 'h', 'w', or 'd'" unless %w[b h w d].include?(size) + raise "'aq' must be defined as true or false" unless [true, false].include?(aq) + raise "'rl' must be defined as true or false" unless [true, false].include?(rl) + + size_info = { + "b" => { name: "byte", bits: 8, funct3: "000", operation_bits: "8" }, + "h" => { name: "halfword", bits: 16, funct3: "001", operation_bits: "16" }, + "w" => { name: "word", bits: 32, funct3: "010", operation_bits: "32" }, + "d" => { name: "doubleword", bits: 64, funct3: "011", operation_bits: "64" } + } + + current_size = size_info[size] + + # Generate instruction name suffix based on aq/rl + aq_rl_suffix = "" + if aq && rl + aq_rl_suffix = ".aqrl" + elsif aq + aq_rl_suffix = ".aq" + elsif rl + aq_rl_suffix = ".rl" + end + + # Generate match string with fixed aq/rl bits + aq_bit = aq ? "1" : "0" + rl_bit = rl ? "1" : "0" +-%> + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.<%= size %><%= aq_rl_suffix %> +long_name: Atomic fetch-and-or <%= current_size[:name] %><%= aq && rl ? " (acquire-release)" : (aq ? " (acquire)" : (rl ? " (release)" : "")) %> +description: | + Atomically<%= aq && rl ? " with acquire and release ordering" : (aq ? " with acquire ordering" : (rl ? " with release ordering" : "")) %>: + + * Load the <%= current_size[:name] %> at address _xs1_ + * Write the <%= %w[b h w].include?(size) ? "sign-extended value" : "loaded value" %> into _xd_ + * OR the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: +<%- if size == "d" -%> + allOf: + - extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> + - xlen: 64 +<%- else -%> + extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> +<%- end -%> +assembly: xd, xs2, (xs1) +encoding: + match: 01000<%= aq_bit %><%= rl_bit %>----------<%= current_size[:funct3] %>-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + +<% if aq -%> + memory_model_acquire(); + +<% end -%> + XReg virtual_address = X[xs1]; + X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Or, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding); +<% if rl -%> + + memory_model_release(); +<% end -%> + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.aq.yaml new file mode 100644 index 000000000000..83cedc7a0709 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.aq.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.d.aq +long_name: Atomic fetch-and-or doubleword (acquire) +description: | + Atomically with acquire ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * OR the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0100010----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Or, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.aqrl.yaml new file mode 100644 index 000000000000..52fce6a213bd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.aqrl.yaml @@ -0,0 +1,147 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.d.aqrl +long_name: Atomic fetch-and-or doubleword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * OR the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0100011----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Or, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.rl.yaml new file mode 100644 index 000000000000..31228b78fb29 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.rl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.d.rl +long_name: Atomic fetch-and-or doubleword (release) +description: | + Atomically with release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * OR the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0100001----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Or, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.yaml new file mode 100644 index 000000000000..9100832e9797 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.d.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.d +long_name: Atomic fetch-and-or doubleword +description: | + Atomically: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * OR the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0100000----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Or, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.aq.yaml new file mode 100644 index 000000000000..9af4d13c29e3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.w.aq +long_name: Atomic fetch-and-or word (acquire) +description: | + Atomically with acquire ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0100010----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Or, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.aqrl.yaml new file mode 100644 index 000000000000..4f019b694ee6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.w.aqrl +long_name: Atomic fetch-and-or word (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0100011----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Or, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.rl.yaml new file mode 100644 index 000000000000..9aec1401aa0f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.w.rl +long_name: Atomic fetch-and-or word (release) +description: | + Atomically with release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0100001----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Or, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.yaml new file mode 100644 index 000000000000..fc4e27bbc4e0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoor.w.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.w +long_name: Atomic fetch-and-or word +description: | + Atomically: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0100000----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Or, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.SIZE.AQRL.layout b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.SIZE.AQRL.layout new file mode 100644 index 000000000000..b54aba9cfe4f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.SIZE.AQRL.layout @@ -0,0 +1,180 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +<%- + raise "'size' must be defined as 'b', 'h', 'w', or 'd'" unless %w[b h w d].include?(size) + raise "'aq' must be defined as true or false" unless [true, false].include?(aq) + raise "'rl' must be defined as true or false" unless [true, false].include?(rl) + + size_info = { + "b" => { name: "byte", bits: 8, funct3: "000", operation_bits: "8" }, + "h" => { name: "halfword", bits: 16, funct3: "001", operation_bits: "16" }, + "w" => { name: "word", bits: 32, funct3: "010", operation_bits: "32" }, + "d" => { name: "doubleword", bits: 64, funct3: "011", operation_bits: "64" } + } + + current_size = size_info[size] + + # Generate instruction name suffix based on aq/rl + aq_rl_suffix = "" + if aq && rl + aq_rl_suffix = ".aqrl" + elsif aq + aq_rl_suffix = ".aq" + elsif rl + aq_rl_suffix = ".rl" + end + + # Generate match string with fixed aq/rl bits + aq_bit = aq ? "1" : "0" + rl_bit = rl ? "1" : "0" +-%> + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.<%= size %><%= aq_rl_suffix %> +long_name: Atomic SWAP <%= current_size[:name] %><%= aq && rl ? " (acquire-release)" : (aq ? " (acquire)" : (rl ? " (release)" : "")) %> +description: | + Atomically<%= aq && rl ? " with acquire and release ordering" : (aq ? " with acquire ordering" : (rl ? " with release ordering" : "")) %>: + + * Load the <%= current_size[:name] %> at address _xs1_ + * Write the <%= %w[b h].include?(size) ? "sign-extended value" : (size == "w" ? "sign-extended value" : "loaded value") %> into _xd_ + * Store the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2_ to the address in _xs1_ +definedBy: +<%- if size == "d" -%> + allOf: + - extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> + - xlen: 64 +<%- else -%> + extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> +<%- end -%> +assembly: xd, xs2, (xs1) +encoding: + match: 00001<%= aq_bit %><%= rl_bit %>----------<%= current_size[:funct3] %>-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + +<% if aq -%> + memory_model_acquire(); + +<% end -%> + XReg virtual_address = X[xs1]; + X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Swap, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding); +<% if rl -%> + + memory_model_release(); +<% end -%> + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.aq.yaml new file mode 100644 index 000000000000..9d6d47c05fad --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.aq.yaml @@ -0,0 +1,144 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.d.aq +long_name: Atomic SWAP doubleword (acquire) +description: | + Atomically with acquire ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Store the value of register _xs2_ to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0000110----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Swap, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.aqrl.yaml new file mode 100644 index 000000000000..28266e1f8e6c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.aqrl.yaml @@ -0,0 +1,146 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.d.aqrl +long_name: Atomic SWAP doubleword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Store the value of register _xs2_ to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0000111----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Swap, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.rl.yaml new file mode 100644 index 000000000000..b8929a655f5a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.rl.yaml @@ -0,0 +1,144 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.d.rl +long_name: Atomic SWAP doubleword (release) +description: | + Atomically with release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Store the value of register _xs2_ to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0000101----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Swap, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.yaml new file mode 100644 index 000000000000..d867458f405e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.d.yaml @@ -0,0 +1,142 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.d +long_name: Atomic SWAP doubleword +description: | + Atomically: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Store the value of register _xs2_ to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0000100----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Swap, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.aq.yaml new file mode 100644 index 000000000000..9b4fc704be72 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.aq.yaml @@ -0,0 +1,142 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.w.aq +long_name: Atomic SWAP word (acquire) +description: | + Atomically with acquire ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant word of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0000110----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.aqrl.yaml new file mode 100644 index 000000000000..6853ad8067c7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.aqrl.yaml @@ -0,0 +1,144 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.w.aqrl +long_name: Atomic SWAP word (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant word of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0000111----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.rl.yaml new file mode 100644 index 000000000000..3dbb33a56487 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.rl.yaml @@ -0,0 +1,142 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.w.rl +long_name: Atomic SWAP word (release) +description: | + Atomically with release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant word of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0000101----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.yaml new file mode 100644 index 000000000000..f9ff206efe3c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoswap.w.yaml @@ -0,0 +1,140 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.w +long_name: Atomic SWAP word +description: | + Atomically: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant word of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0000100----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.SIZE.AQRL.layout b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.SIZE.AQRL.layout new file mode 100644 index 000000000000..7858ced2533b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.SIZE.AQRL.layout @@ -0,0 +1,181 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +<%- + raise "'size' must be defined as 'b', 'h', 'w', or 'd'" unless %w[b h w d].include?(size) + raise "'aq' must be defined as true or false" unless [true, false].include?(aq) + raise "'rl' must be defined as true or false" unless [true, false].include?(rl) + + size_info = { + "b" => { name: "byte", bits: 8, funct3: "000", operation_bits: "8" }, + "h" => { name: "halfword", bits: 16, funct3: "001", operation_bits: "16" }, + "w" => { name: "word", bits: 32, funct3: "010", operation_bits: "32" }, + "d" => { name: "doubleword", bits: 64, funct3: "011", operation_bits: "64" } + } + + current_size = size_info[size] + + # Generate instruction name suffix based on aq/rl + aq_rl_suffix = "" + if aq && rl + aq_rl_suffix = ".aqrl" + elsif aq + aq_rl_suffix = ".aq" + elsif rl + aq_rl_suffix = ".rl" + end + + # Generate match string with fixed aq/rl bits + aq_bit = aq ? "1" : "0" + rl_bit = rl ? "1" : "0" +-%> + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.<%= size %><%= aq_rl_suffix %> +long_name: Atomic fetch-and-xor <%= current_size[:name] %><%= aq && rl ? " (acquire-release)" : (aq ? " (acquire)" : (rl ? " (release)" : "")) %> +description: | + Atomically<%= aq && rl ? " with acquire and release ordering" : (aq ? " with acquire ordering" : (rl ? " with release ordering" : "")) %>: + + * Load the <%= current_size[:name] %> at address _xs1_ + * Write the <%= %w[b h w].include?(size) ? "sign-extended value" : "loaded value" %> into _xd_ + * XOR the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: +<%- if size == "d" -%> + allOf: + - extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> + - xlen: 64 +<%- else -%> + extension: + name: <%= %w[b h].include?(size) ? "Zabha" : "Zaamo" %> +<%- end -%> +assembly: xd, xs2, (xs1) +encoding: + match: 00100<%= aq_bit %><%= rl_bit %>----------<%= current_size[:funct3] %>-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + +<% if aq -%> + memory_model_acquire(); + +<% end -%> + XReg virtual_address = X[xs1]; + X[xd] = amo<<%= current_size[:operation_bits] %>>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, AmoOperation::Xor, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding); +<% if rl -%> + + memory_model_release(); +<% end -%> + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.aq.yaml new file mode 100644 index 000000000000..61c3ddf65598 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.aq.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.d.aq +long_name: Atomic fetch-and-xor doubleword (acquire) +description: | + Atomically with acquire ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * XOR the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0010010----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Xor, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.aqrl.yaml new file mode 100644 index 000000000000..506bdac81fc2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.aqrl.yaml @@ -0,0 +1,147 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.d.aqrl +long_name: Atomic fetch-and-xor doubleword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * XOR the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0010011----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Xor, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.rl.yaml new file mode 100644 index 000000000000..452e4bf6c331 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.rl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.d.rl +long_name: Atomic fetch-and-xor doubleword (release) +description: | + Atomically with release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * XOR the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0010001----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Xor, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.yaml new file mode 100644 index 000000000000..c033f010bc26 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.d.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.d +long_name: Atomic fetch-and-xor doubleword +description: | + Atomically: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * XOR the value of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zaamo + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0010000----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<64>(virtual_address, X[xs2], AmoOperation::Xor, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.aq.yaml new file mode 100644 index 000000000000..1ce154abf21b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.w.aq +long_name: Atomic fetch-and-xor word (acquire) +description: | + Atomically with acquire ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0010010----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.aqrl.yaml new file mode 100644 index 000000000000..758403657ba5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.w.aqrl +long_name: Atomic fetch-and-xor word (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0010011----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.rl.yaml new file mode 100644 index 000000000000..6cba29af4fbd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.w.rl +long_name: Atomic fetch-and-xor word (release) +description: | + Atomically with release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0010001----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.yaml new file mode 100644 index 000000000000..6f602d26afda --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zaamo/amoxor.w.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.w +long_name: Atomic fetch-and-xor word +description: | + Atomically: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant word of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zaamo +assembly: xd, xs2, (xs1) +encoding: + match: 0010000----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<32>(virtual_address, X[xs2][31:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.aq.yaml new file mode 100644 index 000000000000..00e1d34e2cd6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.b.aq +long_name: Atomic fetch-and-add byte (acquire) +description: | + Atomically with acquire ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000010----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Add, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.aqrl.yaml new file mode 100644 index 000000000000..220a4975ea15 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.b.aqrl +long_name: Atomic fetch-and-add byte (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000011----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Add, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.rl.yaml new file mode 100644 index 000000000000..75554ef106c8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.b.rl +long_name: Atomic fetch-and-add byte (release) +description: | + Atomically with release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000001----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Add, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.yaml new file mode 100644 index 000000000000..0b80d6a21b82 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.b.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.b +long_name: Atomic fetch-and-add byte +description: | + Atomically: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000000----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Add, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.aq.yaml new file mode 100644 index 000000000000..c0bb9afcb962 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.h.aq +long_name: Atomic fetch-and-add halfword (acquire) +description: | + Atomically with acquire ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000010----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Add, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.aqrl.yaml new file mode 100644 index 000000000000..c49122ec74af --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.h.aqrl +long_name: Atomic fetch-and-add halfword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000011----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Add, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.rl.yaml new file mode 100644 index 000000000000..9fdd017cbe9c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.h.rl +long_name: Atomic fetch-and-add halfword (release) +description: | + Atomically with release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000001----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Add, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.yaml new file mode 100644 index 000000000000..0b639309bca4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoadd.h.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoadd.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoadd.h +long_name: Atomic fetch-and-add halfword +description: | + Atomically: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Add the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000000----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Add, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.aq.yaml new file mode 100644 index 000000000000..f07b423478c0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.b.aq +long_name: Atomic fetch-and-and byte (acquire) +description: | + Atomically with acquire ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0110010----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::And, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.aqrl.yaml new file mode 100644 index 000000000000..b1f9916fe9ec --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.b.aqrl +long_name: Atomic fetch-and-and byte (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0110011----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::And, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.rl.yaml new file mode 100644 index 000000000000..6ff87141dbb4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.b.rl +long_name: Atomic fetch-and-and byte (release) +description: | + Atomically with release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0110001----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::And, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.yaml new file mode 100644 index 000000000000..791498781cce --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.b.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.b +long_name: Atomic fetch-and-and byte +description: | + Atomically: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0110000----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::And, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.aq.yaml new file mode 100644 index 000000000000..357fbe67a7c0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.h.aq +long_name: Atomic fetch-and-and halfword (acquire) +description: | + Atomically with acquire ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0110010----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::And, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.aqrl.yaml new file mode 100644 index 000000000000..c426023640c2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.h.aqrl +long_name: Atomic fetch-and-and halfword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0110011----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::And, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.rl.yaml new file mode 100644 index 000000000000..712466ae4d4e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.h.rl +long_name: Atomic fetch-and-and halfword (release) +description: | + Atomically with release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0110001----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::And, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.yaml new file mode 100644 index 000000000000..04a59f187bc2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoand.h.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoand.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoand.h +long_name: Atomic fetch-and-and halfword +description: | + Atomically: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * AND the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0110000----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::And, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.aq.yaml new file mode 100644 index 000000000000..4740d38443eb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.aq.yaml @@ -0,0 +1,135 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.b.aq +long_name: Atomic compare-and-swap byte (acquire) +description: | + Atomically with acquire ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant byte of register _xs2_ + * If equal, write the least-significant byte of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010110----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zabha)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas8(virtual_address, X[xs2][7:0], X[xd][7:0], 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zabha") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.aqrl.yaml new file mode 100644 index 000000000000..d522da83c92c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.aqrl.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.b.aqrl +long_name: Atomic compare-and-swap byte (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant byte of register _xs2_ + * If equal, write the least-significant byte of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010111----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zabha)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas8(virtual_address, X[xs2][7:0], X[xd][7:0], 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zabha") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.rl.yaml new file mode 100644 index 000000000000..51f5c93fa6d8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.rl.yaml @@ -0,0 +1,135 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.b.rl +long_name: Atomic compare-and-swap byte (release) +description: | + Atomically with release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant byte of register _xs2_ + * If equal, write the least-significant byte of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010101----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zabha)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas8(virtual_address, X[xs2][7:0], X[xd][7:0], 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zabha") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.yaml new file mode 100644 index 000000000000..fec3ce20a0b7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.b.yaml @@ -0,0 +1,133 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.b +long_name: Atomic compare-and-swap byte +description: | + Atomically: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant byte of register _xs2_ + * If equal, write the least-significant byte of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010100----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zabha)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas8(virtual_address, X[xs2][7:0], X[xd][7:0], 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zabha") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.aq.yaml new file mode 100644 index 000000000000..d0fee2c9088a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.aq.yaml @@ -0,0 +1,135 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.h.aq +long_name: Atomic compare-and-swap halfword (acquire) +description: | + Atomically with acquire ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant halfword of register _xs2_ + * If equal, write the least-significant halfword of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010110----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zabha)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas16(virtual_address, X[xs2][15:0], X[xd][15:0], 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zabha") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.aqrl.yaml new file mode 100644 index 000000000000..530bc0bf0417 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.aqrl.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.h.aqrl +long_name: Atomic compare-and-swap halfword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant halfword of register _xs2_ + * If equal, write the least-significant halfword of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010111----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zabha)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas16(virtual_address, X[xs2][15:0], X[xd][15:0], 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zabha") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.rl.yaml new file mode 100644 index 000000000000..9413f625573d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.rl.yaml @@ -0,0 +1,135 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.h.rl +long_name: Atomic compare-and-swap halfword (release) +description: | + Atomically with release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant halfword of register _xs2_ + * If equal, write the least-significant halfword of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010101----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zabha)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas16(virtual_address, X[xs2][15:0], X[xd][15:0], 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zabha") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.yaml new file mode 100644 index 000000000000..14d987afe2a9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amocas.h.yaml @@ -0,0 +1,133 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.h +long_name: Atomic compare-and-swap halfword +description: | + Atomically: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant halfword of register _xs2_ + * If equal, write the least-significant halfword of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010100----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zabha)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas16(virtual_address, X[xs2][15:0], X[xd][15:0], 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zabha") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.aq.yaml new file mode 100644 index 000000000000..645af1a4e30b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.b.aq +long_name: Atomic MAX byte (acquire) +description: | + Atomically with acquire ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant byte of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1010010----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Max, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.aqrl.yaml new file mode 100644 index 000000000000..a182980670ea --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.b.aqrl +long_name: Atomic MAX byte (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant byte of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1010011----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Max, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.rl.yaml new file mode 100644 index 000000000000..76fb25bcfa9d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.b.rl +long_name: Atomic MAX byte (release) +description: | + Atomically with release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant byte of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1010001----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Max, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.yaml new file mode 100644 index 000000000000..ac54ad238e12 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.b.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.b +long_name: Atomic MAX byte +description: | + Atomically: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant byte of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1010000----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Max, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.aq.yaml new file mode 100644 index 000000000000..47b3aa723787 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.h.aq +long_name: Atomic MAX halfword (acquire) +description: | + Atomically with acquire ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant halfword of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1010010----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Max, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.aqrl.yaml new file mode 100644 index 000000000000..387ce13e2f28 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.h.aqrl +long_name: Atomic MAX halfword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant halfword of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1010011----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Max, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.rl.yaml new file mode 100644 index 000000000000..78b61ce13337 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.h.rl +long_name: Atomic MAX halfword (release) +description: | + Atomically with release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant halfword of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1010001----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Max, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.yaml new file mode 100644 index 000000000000..87438c33a703 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomax.h.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomax.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomax.h +long_name: Atomic MAX halfword +description: | + Atomically: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant halfword of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1010000----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Max, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.aq.yaml new file mode 100644 index 000000000000..d86d9292ef6d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.b.aq +long_name: Atomic MAX unsigned byte (acquire) +description: | + Atomically with acquire ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant byte of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1110010----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Maxu, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, true & false, false, true), + (HALF, _) => mem_write_ea(addr, 2, true & false, false, true), + (WORD, _) => mem_write_ea(addr, 4, true & false, false, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, true & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, true, true & false, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, true, true & false, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, true, true & false, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, true, true & false, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], true & false, false, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], true & false, false, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], true & false, false, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, true & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.aqrl.yaml new file mode 100644 index 000000000000..2d49d82dda50 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.b.aqrl +long_name: Atomic MAX unsigned byte (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant byte of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1110011----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Maxu, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, true & true, true, true), + (HALF, _) => mem_write_ea(addr, 2, true & true, true, true), + (WORD, _) => mem_write_ea(addr, 4, true & true, true, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, true & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, true, true & true, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, true, true & true, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, true, true & true, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, true, true & true, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], true & true, true, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], true & true, true, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], true & true, true, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, true & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.rl.yaml new file mode 100644 index 000000000000..9c925ec42917 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.b.rl +long_name: Atomic MAX unsigned byte (release) +description: | + Atomically with release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant byte of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1110001----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Maxu, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, false & true, true, true), + (HALF, _) => mem_write_ea(addr, 2, false & true, true, true), + (WORD, _) => mem_write_ea(addr, 4, false & true, true, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, false & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, false, false & true, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, false, false & true, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, false, false & true, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, false, false & true, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], false & true, true, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], false & true, true, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], false & true, true, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, false & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.yaml new file mode 100644 index 000000000000..6fce0bf12516 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.b.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.b +long_name: Atomic MAX unsigned byte +description: | + Atomically: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant byte of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1110000----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Maxu, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, false & false, false, true), + (HALF, _) => mem_write_ea(addr, 2, false & false, false, true), + (WORD, _) => mem_write_ea(addr, 4, false & false, false, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, false & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, false, false & false, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, false, false & false, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, false, false & false, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, false, false & false, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], false & false, false, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], false & false, false, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], false & false, false, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, false & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.aq.yaml new file mode 100644 index 000000000000..eeca9537fb46 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.h.aq +long_name: Atomic MAX unsigned halfword (acquire) +description: | + Atomically with acquire ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant halfword of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1110010----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Maxu, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, true & false, false, true), + (HALF, _) => mem_write_ea(addr, 2, true & false, false, true), + (WORD, _) => mem_write_ea(addr, 4, true & false, false, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, true & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, true, true & false, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, true, true & false, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, true, true & false, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, true, true & false, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], true & false, false, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], true & false, false, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], true & false, false, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, true & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.aqrl.yaml new file mode 100644 index 000000000000..6981e1214804 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.h.aqrl +long_name: Atomic MAX unsigned halfword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant halfword of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1110011----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Maxu, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, true & true, true, true), + (HALF, _) => mem_write_ea(addr, 2, true & true, true, true), + (WORD, _) => mem_write_ea(addr, 4, true & true, true, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, true & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, true, true & true, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, true, true & true, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, true, true & true, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, true, true & true, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], true & true, true, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], true & true, true, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], true & true, true, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, true & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.rl.yaml new file mode 100644 index 000000000000..518c28b638c0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.h.rl +long_name: Atomic MAX unsigned halfword (release) +description: | + Atomically with release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant halfword of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1110001----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Maxu, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, false & true, true, true), + (HALF, _) => mem_write_ea(addr, 2, false & true, true, true), + (WORD, _) => mem_write_ea(addr, 4, false & true, true, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, false & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, false, false & true, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, false, false & true, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, false, false & true, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, false, false & true, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], false & true, true, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], false & true, true, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], false & true, true, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, false & true, true, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.yaml new file mode 100644 index 000000000000..1d209c3ba0ad --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomaxu.h.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomaxu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomaxu.h +long_name: Atomic MAX unsigned halfword +description: | + Atomically: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant halfword of register _xs2_ to the loaded value, and select the maximum value + * Write the maximum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1110000----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Maxu, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, false & false, false, true), + (HALF, _) => mem_write_ea(addr, 2, false & false, false, true), + (WORD, _) => mem_write_ea(addr, 4, false & false, false, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, false & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let xs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, false, false & false, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, false, false & false, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, false, false & false, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, false, false & false, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => xs2_val, + AMOADD => xs2_val + loaded, + AMOXOR => xs2_val ^ loaded, + AMOAND => xs2_val & loaded, + AMOOR => xs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(xs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(xs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(xs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(xs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], false & false, false, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], false & false, false, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], false & false, false, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, false & false, false, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.aq.yaml new file mode 100644 index 000000000000..5dace1d44d69 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.b.aq +long_name: Atomic MIN byte (acquire) +description: | + Atomically with acquire ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant byte of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1000010----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Min, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.aqrl.yaml new file mode 100644 index 000000000000..d71be2fb1239 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.b.aqrl +long_name: Atomic MIN byte (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant byte of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1000011----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Min, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.rl.yaml new file mode 100644 index 000000000000..22890cb269b0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.b.rl +long_name: Atomic MIN byte (release) +description: | + Atomically with release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant byte of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1000001----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Min, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.yaml new file mode 100644 index 000000000000..2755e51fc88a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.b.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.b +long_name: Atomic MIN byte +description: | + Atomically: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant byte of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1000000----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Min, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.aq.yaml new file mode 100644 index 000000000000..0d396ce73593 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.h.aq +long_name: Atomic MIN halfword (acquire) +description: | + Atomically with acquire ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant halfword of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1000010----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Min, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.aqrl.yaml new file mode 100644 index 000000000000..f73d4ee6d97b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.h.aqrl +long_name: Atomic MIN halfword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant halfword of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1000011----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Min, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.rl.yaml new file mode 100644 index 000000000000..8ab26e8e5eee --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.h.rl +long_name: Atomic MIN halfword (release) +description: | + Atomically with release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant halfword of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1000001----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Min, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.yaml new file mode 100644 index 000000000000..9ba8c4e95561 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amomin.h.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amomin.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amomin.h +long_name: Atomic MIN halfword +description: | + Atomically: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Signed compare the least-significant halfword of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1000000----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Min, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.aq.yaml new file mode 100644 index 000000000000..5295bb731896 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.b.aq +long_name: Atomic MIN unsigned byte (acquire) +description: | + Atomically with acquire ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant byte of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1100010----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.aqrl.yaml new file mode 100644 index 000000000000..6e72a92ffdd8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.b.aqrl +long_name: Atomic MIN unsigned byte (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant byte of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1100011----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.rl.yaml new file mode 100644 index 000000000000..535d6f60b71a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.b.rl +long_name: Atomic MIN unsigned byte (release) +description: | + Atomically with release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant byte of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1100001----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.yaml new file mode 100644 index 000000000000..b6e537de6ba7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.b.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.b +long_name: Atomic MIN unsigned byte +description: | + Atomically: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant byte of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1100000----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Minu, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.aq.yaml new file mode 100644 index 000000000000..72b44079d32c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.h.aq +long_name: Atomic MIN unsigned halfword (acquire) +description: | + Atomically with acquire ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant halfword of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1100010----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.aqrl.yaml new file mode 100644 index 000000000000..f27323637d6a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.h.aqrl +long_name: Atomic MIN unsigned halfword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant halfword of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1100011----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.rl.yaml new file mode 100644 index 000000000000..f5c09bda296d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.h.rl +long_name: Atomic MIN unsigned halfword (release) +description: | + Atomically with release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant halfword of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1100001----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.yaml new file mode 100644 index 000000000000..a6bd04bda43c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amominu.h.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amominu.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amominu.h +long_name: Atomic MIN unsigned halfword +description: | + Atomically: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Unsigned compare the least-significant halfword of register _xs2_ to the loaded value, and select the minimum value + * Write the minimum to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 1100000----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Minu, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.aq.yaml new file mode 100644 index 000000000000..7f2deb6a0bea --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.b.aq +long_name: Atomic fetch-and-or byte (acquire) +description: | + Atomically with acquire ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0100010----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.aqrl.yaml new file mode 100644 index 000000000000..6fe76c5d31e6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.b.aqrl +long_name: Atomic fetch-and-or byte (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0100011----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.rl.yaml new file mode 100644 index 000000000000..ddb310f1d5a2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.b.rl +long_name: Atomic fetch-and-or byte (release) +description: | + Atomically with release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0100001----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.yaml new file mode 100644 index 000000000000..263ca9d43707 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.b.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.b +long_name: Atomic fetch-and-or byte +description: | + Atomically: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0100000----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Or, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.aq.yaml new file mode 100644 index 000000000000..0bdd5790155b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.h.aq +long_name: Atomic fetch-and-or halfword (acquire) +description: | + Atomically with acquire ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0100010----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.aqrl.yaml new file mode 100644 index 000000000000..c8540aaf523a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.h.aqrl +long_name: Atomic fetch-and-or halfword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0100011----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.rl.yaml new file mode 100644 index 000000000000..d7b4e540cc0a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.h.rl +long_name: Atomic fetch-and-or halfword (release) +description: | + Atomically with release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0100001----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.yaml new file mode 100644 index 000000000000..c34a43690919 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoor.h.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoor.h +long_name: Atomic fetch-and-or halfword +description: | + Atomically: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * OR the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0100000----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Or, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.aq.yaml new file mode 100644 index 000000000000..e02ae7a3a0ae --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.aq.yaml @@ -0,0 +1,142 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.b.aq +long_name: Atomic SWAP byte (acquire) +description: | + Atomically with acquire ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant byte of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000110----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.aqrl.yaml new file mode 100644 index 000000000000..0bdf6e04eabc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.aqrl.yaml @@ -0,0 +1,144 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.b.aqrl +long_name: Atomic SWAP byte (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant byte of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000111----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.rl.yaml new file mode 100644 index 000000000000..dc57394dd7a7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.rl.yaml @@ -0,0 +1,142 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.b.rl +long_name: Atomic SWAP byte (release) +description: | + Atomically with release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant byte of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000101----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.yaml new file mode 100644 index 000000000000..191c12cc1770 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.b.yaml @@ -0,0 +1,140 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.b +long_name: Atomic SWAP byte +description: | + Atomically: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant byte of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000100----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.aq.yaml new file mode 100644 index 000000000000..20ab7ec96d84 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.aq.yaml @@ -0,0 +1,142 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.h.aq +long_name: Atomic SWAP halfword (acquire) +description: | + Atomically with acquire ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant halfword of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000110----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.aqrl.yaml new file mode 100644 index 000000000000..2d1cc07a3585 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.aqrl.yaml @@ -0,0 +1,144 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.h.aqrl +long_name: Atomic SWAP halfword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant halfword of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000111----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.rl.yaml new file mode 100644 index 000000000000..7c434a0ea6f4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.rl.yaml @@ -0,0 +1,142 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.h.rl +long_name: Atomic SWAP halfword (release) +description: | + Atomically with release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant halfword of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000101----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.yaml new file mode 100644 index 000000000000..b69454a95343 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoswap.h.yaml @@ -0,0 +1,140 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoswap.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoswap.h +long_name: Atomic SWAP halfword +description: | + Atomically: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * Store the least-significant halfword of register _xs2_ to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0000100----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Swap, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.aq.yaml new file mode 100644 index 000000000000..2466407b2c34 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.b.aq +long_name: Atomic fetch-and-xor byte (acquire) +description: | + Atomically with acquire ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010010----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.aqrl.yaml new file mode 100644 index 000000000000..3da5aafa8831 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.b.aqrl +long_name: Atomic fetch-and-xor byte (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010011----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.rl.yaml new file mode 100644 index 000000000000..30bffe9e7361 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.b.rl +long_name: Atomic fetch-and-xor byte (release) +description: | + Atomically with release ordering: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010001----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.yaml new file mode 100644 index 000000000000..401e6e152b22 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.b.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.b +long_name: Atomic fetch-and-xor byte +description: | + Atomically: + + * Load the byte at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant byte of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010000----------000-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<8>(virtual_address, X[xs2][7:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.aq.yaml new file mode 100644 index 000000000000..14b1271d70f6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.aq.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.h.aq +long_name: Atomic fetch-and-xor halfword (acquire) +description: | + Atomically with acquire ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010010----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.aqrl.yaml new file mode 100644 index 000000000000..80d3177fbdaa --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.aqrl.yaml @@ -0,0 +1,145 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.h.aqrl +long_name: Atomic fetch-and-xor halfword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010011----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.rl.yaml new file mode 100644 index 000000000000..2598a3208340 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.rl.yaml @@ -0,0 +1,143 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.h.rl +long_name: Atomic fetch-and-xor halfword (release) +description: | + Atomically with release ordering: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010001----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.yaml new file mode 100644 index 000000000000..30b3d96d53f2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zabha/amoxor.h.yaml @@ -0,0 +1,141 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zaamo/amoxor.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amoxor.h +long_name: Atomic fetch-and-xor halfword +description: | + Atomically: + + * Load the halfword at address _xs1_ + * Write the sign-extended value into _xd_ + * XOR the least-significant halfword of register _xs2_ to the loaded value + * Write the result to the address in _xs1_ +definedBy: + extension: + name: Zabha +assembly: xd, xs2, (xs1) +encoding: + match: 0010000----------001-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::A) || (MISA_CSR_IMPLEMENTED && (CSR[misa].A == 1'b0))) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + X[xd] = amo<16>(virtual_address, X[xs2][15:0], AmoOperation::Xor, 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + let is_unsigned : bool = match op { + AMOMINU => true, + AMOMAXU => true, + _ => false + }; + let rs2_val : xlenbits = match width { + BYTE => if is_unsigned then zero_extend(X(rs2)[7..0]) else sign_extend(X(rs2)[7..0]), + HALF => if is_unsigned then zero_extend(X(rs2)[15..0]) else sign_extend(X(rs2)[15..0]), + WORD => if is_unsigned then zero_extend(X(rs2)[31..0]) else sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(is_unsigned, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let result : xlenbits = + match op { + AMOSWAP => rs2_val, + AMOADD => rs2_val + loaded, + AMOXOR => rs2_val ^ loaded, + AMOAND => rs2_val & loaded, + AMOOR => rs2_val | loaded, + + /* These operations convert bitvectors to integer values using [un]signed, + * and back using to_bits(). + */ + AMOMIN => to_bits(sizeof(xlen), min(signed(rs2_val), signed(loaded))), + AMOMAX => to_bits(sizeof(xlen), max(signed(rs2_val), signed(loaded))), + AMOMINU => to_bits(sizeof(xlen), min(unsigned(rs2_val), unsigned(loaded))), + AMOMAXU => to_bits(sizeof(xlen), max(unsigned(rs2_val), unsigned(loaded))) + }; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.SIZE.AQRL.layout b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.SIZE.AQRL.layout new file mode 100644 index 000000000000..3c8cce20c97e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.SIZE.AQRL.layout @@ -0,0 +1,174 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json +<%- + raise "'size' must be defined as 'b', 'h', 'w', 'd', or 'q'" unless %w[b h w d q].include?(size) + raise "'aq' must be defined as true or false" unless [true, false].include?(aq) + raise "'rl' must be defined as true or false" unless [true, false].include?(rl) + + size_info = { + "b" => { name: "byte", bits: 8, funct3: "000", operation_bits: "8", extension: "Zabha" }, + "h" => { name: "halfword", bits: 16, funct3: "001", operation_bits: "16", extension: "Zabha" }, + "w" => { name: "word", bits: 32, funct3: "010", operation_bits: "32", extension: "Zacas" }, + "d" => { name: "doubleword", bits: 64, funct3: "011", operation_bits: "64", extension: "Zacas" }, + "q" => { name: "quadword", bits: 128, funct3: "100", operation_bits: "128", extension: "Zacas" } + } + + current_size = size_info[size] + + # Generate instruction name suffix based on aq/rl + aq_rl_suffix = "" + if aq && rl + aq_rl_suffix = ".aqrl" + elsif aq + aq_rl_suffix = ".aq" + elsif rl + aq_rl_suffix = ".rl" + end + + # Generate match string with fixed aq/rl bits (funct5 = 00101 for amocas) + aq_bit = aq ? "1" : "0" + rl_bit = rl ? "1" : "0" +-%> + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.<%= size %><%= aq_rl_suffix %> +long_name: Atomic compare-and-swap <%= current_size[:name] %><%= aq && rl ? " (acquire-release)" : (aq ? " (acquire)" : (rl ? " (release)" : "")) %> +description: | + Atomically<%= aq && rl ? " with acquire and release ordering" : (aq ? " with acquire ordering" : (rl ? " with release ordering" : "")) %>: + + * Load the <%= current_size[:name] %> at address _xs1_ + * Write the <%= %w[b h w].include?(size) ? "sign-extended value" : "loaded value" %> into _xd_ + * Compare the loaded value with the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2_ + * If equal, write the <%= %w[b h w].include?(size) ? "least-significant #{current_size[:name]} of register" : "value of register" %> _xs2+1_ to the address in _xs1_ +definedBy: +<%- if size == "q" -%> + allOf: + - extension: + name: <%= current_size[:extension] %> + - xlen: 64 +<%- else -%> + extension: + name: <%= current_size[:extension] %> +<%- end -%> +assembly: xd, xs2, (xs1) +encoding: + match: 00101<%= aq_bit %><%= rl_bit %>----------<%= current_size[:funct3] %>-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::<%= current_size[:extension] %>)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + +<% if aq -%> + memory_model_acquire(); + +<% end -%> + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas<%= current_size[:operation_bits] %>(virtual_address, X[xs2]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, X[xd]<%= %w[b h w].include?(size) ? "[#{current_size[:bits]-1}:0]" : "" %>, <%= aq ? "1'b1" : "1'b0" %>, <%= rl ? "1'b1" : "1'b0" %>, $encoding); +<% if rl -%> + + memory_model_release(); +<% end -%> + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("<%= current_size[:extension] %>") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.aq.yaml new file mode 100644 index 000000000000..34692c7655b7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.aq.yaml @@ -0,0 +1,135 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.d.aq +long_name: Atomic compare-and-swap doubleword (acquire) +description: | + Atomically with acquire ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Compare the loaded value with the value of register _xs2_ + * If equal, write the value of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zacas +assembly: xd, xs2, (xs1) +encoding: + match: 0010110----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas64(virtual_address, X[xs2], X[xd], 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.aqrl.yaml new file mode 100644 index 000000000000..bea941928cbb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.aqrl.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.d.aqrl +long_name: Atomic compare-and-swap doubleword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Compare the loaded value with the value of register _xs2_ + * If equal, write the value of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zacas +assembly: xd, xs2, (xs1) +encoding: + match: 0010111----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas64(virtual_address, X[xs2], X[xd], 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.rl.yaml new file mode 100644 index 000000000000..f8cfa85dab37 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.rl.yaml @@ -0,0 +1,135 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.d.rl +long_name: Atomic compare-and-swap doubleword (release) +description: | + Atomically with release ordering: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Compare the loaded value with the value of register _xs2_ + * If equal, write the value of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zacas +assembly: xd, xs2, (xs1) +encoding: + match: 0010101----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas64(virtual_address, X[xs2], X[xd], 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.yaml new file mode 100644 index 000000000000..d06934fd4135 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.d.yaml @@ -0,0 +1,133 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.d +long_name: Atomic compare-and-swap doubleword +description: | + Atomically: + + * Load the doubleword at address _xs1_ + * Write the loaded value into _xd_ + * Compare the loaded value with the value of register _xs2_ + * If equal, write the value of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zacas +assembly: xd, xs2, (xs1) +encoding: + match: 0010100----------011-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas64(virtual_address, X[xs2], X[xd], 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.aq.yaml new file mode 100644 index 000000000000..243a2c86e65f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.aq.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.q.aq +long_name: Atomic compare-and-swap quadword (acquire) +description: | + Atomically with acquire ordering: + + * Load the quadword at address _xs1_ + * Write the loaded value into _xd_ + * Compare the loaded value with the value of register _xs2_ + * If equal, write the value of register _xs2+1_ to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zacas + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0010110----------100-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas128(virtual_address, X[xs2], X[xd], 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.aqrl.yaml new file mode 100644 index 000000000000..b2c5c9e8c0cf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.aqrl.yaml @@ -0,0 +1,139 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.q.aqrl +long_name: Atomic compare-and-swap quadword (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the quadword at address _xs1_ + * Write the loaded value into _xd_ + * Compare the loaded value with the value of register _xs2_ + * If equal, write the value of register _xs2+1_ to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zacas + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0010111----------100-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas128(virtual_address, X[xs2], X[xd], 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.rl.yaml new file mode 100644 index 000000000000..7b2821a8658e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.rl.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.q.rl +long_name: Atomic compare-and-swap quadword (release) +description: | + Atomically with release ordering: + + * Load the quadword at address _xs1_ + * Write the loaded value into _xd_ + * Compare the loaded value with the value of register _xs2_ + * If equal, write the value of register _xs2+1_ to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zacas + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0010101----------100-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas128(virtual_address, X[xs2], X[xd], 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.yaml new file mode 100644 index 000000000000..085fc5266a60 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.q.yaml @@ -0,0 +1,135 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.q +long_name: Atomic compare-and-swap quadword +description: | + Atomically: + + * Load the quadword at address _xs1_ + * Write the loaded value into _xd_ + * Compare the loaded value with the value of register _xs2_ + * If equal, write the value of register _xs2+1_ to the address in _xs1_ +definedBy: + allOf: + - extension: + name: Zacas + - xlen: 64 +assembly: xd, xs2, (xs1) +encoding: + match: 0010100----------100-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas128(virtual_address, X[xs2], X[xd], 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.aq.yaml new file mode 100644 index 000000000000..c8d339ccca25 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.aq.yaml @@ -0,0 +1,135 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.w.aq +long_name: Atomic compare-and-swap word (acquire) +description: | + Atomically with acquire ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant word of register _xs2_ + * If equal, write the least-significant word of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zacas +assembly: xd, xs2, (xs1) +encoding: + match: 0010110----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas32(virtual_address, X[xs2][31:0], X[xd][31:0], 1'b1, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.aqrl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.aqrl.yaml new file mode 100644 index 000000000000..bcbf05b1ff21 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.aqrl.yaml @@ -0,0 +1,137 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.w.aqrl +long_name: Atomic compare-and-swap word (acquire-release) +description: | + Atomically with acquire and release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant word of register _xs2_ + * If equal, write the least-significant word of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zacas +assembly: xd, xs2, (xs1) +encoding: + match: 0010111----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + memory_model_acquire(); + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas32(virtual_address, X[xs2][31:0], X[xd][31:0], 1'b1, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.rl.yaml new file mode 100644 index 000000000000..3f355fa45fcd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.rl.yaml @@ -0,0 +1,135 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.w.rl +long_name: Atomic compare-and-swap word (release) +description: | + Atomically with release ordering: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant word of register _xs2_ + * If equal, write the least-significant word of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zacas +assembly: xd, xs2, (xs1) +encoding: + match: 0010101----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas32(virtual_address, X[xs2][31:0], X[xd][31:0], 1'b0, 1'b1, $encoding); + + memory_model_release(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.yaml new file mode 100644 index 000000000000..c9dd1832ab33 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zacas/amocas.w.yaml @@ -0,0 +1,133 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +# WARNING: This file is auto-generated from spec/std/isa/inst/Zacas/amocas.SIZE.AQRL.layout + +# Copyright (c) Abhijit Das(Sukuna0007Abhi) +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: amocas.w +long_name: Atomic compare-and-swap word +description: | + Atomically: + + * Load the word at address _xs1_ + * Write the sign-extended value into _xd_ + * Compare the loaded value with the least-significant word of register _xs2_ + * If equal, write the least-significant word of register _xs2+1_ to the address in _xs1_ +definedBy: + extension: + name: Zacas +assembly: xd, xs2, (xs1) +encoding: + match: 0010100----------010-----0101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (!implemented?(ExtensionName::Zacas)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + # TODO + # X[xd] = amocas32(virtual_address, X[xs2][31:0], X[xd][31:0], 1'b0, 1'b0, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("Zacas") then { + /* Get the address, X(rs1) (no offset). + * Some extensions perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + match translateAddr(vaddr, ReadWrite(Data, Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + let rs2_val : xlenbits = match width { + BYTE => sign_extend(X(rs2)[7..0]), + HALF => sign_extend(X(rs2)[15..0]), + WORD => sign_extend(X(rs2)[31..0]), + DOUBLE => X(rs2) + }; + let rd_val : xlenbits = match width { + BYTE => sign_extend(X(rd)[7..0]), + HALF => sign_extend(X(rd)[15..0]), + WORD => sign_extend(X(rd)[31..0]), + DOUBLE => X(rd) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let mval : MemoryOpResult(xlenbits) = match (width, sizeof(xlen)) { + (BYTE, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 1, aq, aq & rl, true)), + (HALF, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 2, aq, aq & rl, true)), + (WORD, _) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 4, aq, aq & rl, true)), + (DOUBLE, 64) => extend_value(false, mem_read(ReadWrite(Data, Data), addr, 8, aq, aq & rl, true)), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + }; + match (mval) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(loaded) => { + let success : bool = (loaded == rs2_val); + let result : xlenbits = if success then rd_val else loaded; + let rval : xlenbits = match width { + BYTE => sign_extend(loaded[7..0]), + HALF => sign_extend(loaded[15..0]), + WORD => sign_extend(loaded[31..0]), + DOUBLE => loaded + }; + let wval : MemoryOpResult(bool) = if success then { + match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, result[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, result[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, result[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, result, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMOCAS width") + } + } else { + MemValue(true) /* No write on compare failure */ + }; + match (wval) { + MemValue(true) => { X(rd) = rval; RETIRE_SUCCESS }, + MemValue(false) => { internal_error(__FILE__, __LINE__, "AMOCAS got false from mem_write_value") }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalasr/lb.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalasr/lb.aq.yaml new file mode 100644 index 000000000000..95d4b2ef3a08 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalasr/lb.aq.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lb.aq +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zalasr +assembly: xd, (xs1) +encoding: + match: 001101000000-----000-----0101111 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalasr/ld.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalasr/ld.aq.yaml new file mode 100644 index 000000000000..003d9dbeb2e6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalasr/ld.aq.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: ld.aq +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zalasr +assembly: xd, (xs1) +encoding: + match: 001101000000-----011-----0101111 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalasr/lh.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalasr/lh.aq.yaml new file mode 100644 index 000000000000..ce713ce59b1e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalasr/lh.aq.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lh.aq +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zalasr +assembly: xd, (xs1) +encoding: + match: 001101000000-----001-----0101111 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalasr/lw.aq.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalasr/lw.aq.yaml new file mode 100644 index 000000000000..71970a818ecb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalasr/lw.aq.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lw.aq +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zalasr +assembly: xd, (xs1) +encoding: + match: 001101000000-----010-----0101111 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rd, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalasr/sb.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalasr/sb.rl.yaml new file mode 100644 index 000000000000..a7ffda41319a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalasr/sb.rl.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sb.rl +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zalasr +assembly: xs2, (xs1) +encoding: + match: 0011101----------000000000101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Write(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => { + let eares : MemoryOpResult(unit) = match width { + BYTE => mem_write_ea(paddr, 1, aq, rl, false), + HALF => mem_write_ea(paddr, 2, aq, rl, false), + WORD => mem_write_ea(paddr, 4, aq, rl, false), + DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let rs2_val = X(rs2); + let res : MemoryOpResult(bool) = match (width) { + BYTE => mem_write_value(paddr, 1, rs2_val[7..0], aq, rl, false), + HALF => mem_write_value(paddr, 2, rs2_val[15..0], aq, rl, false), + WORD => mem_write_value(paddr, 4, rs2_val[31..0], aq, rl, false), + DOUBLE if sizeof(xlen) >= 64 + => mem_write_value(paddr, 8, rs2_val, aq, rl, false), + _ => report_invalid_width(__FILE__, __LINE__, width, "store"), + }; + match (res) { + MemValue(true) => RETIRE_SUCCESS, + MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalasr/sd.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalasr/sd.rl.yaml new file mode 100644 index 000000000000..5d200c2b3142 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalasr/sd.rl.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sd.rl +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zalasr +assembly: xs2, (xs1) +encoding: + match: 0011101----------011000000101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Write(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => { + let eares : MemoryOpResult(unit) = match width { + BYTE => mem_write_ea(paddr, 1, aq, rl, false), + HALF => mem_write_ea(paddr, 2, aq, rl, false), + WORD => mem_write_ea(paddr, 4, aq, rl, false), + DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let rs2_val = X(rs2); + let res : MemoryOpResult(bool) = match (width) { + BYTE => mem_write_value(paddr, 1, rs2_val[7..0], aq, rl, false), + HALF => mem_write_value(paddr, 2, rs2_val[15..0], aq, rl, false), + WORD => mem_write_value(paddr, 4, rs2_val[31..0], aq, rl, false), + DOUBLE if sizeof(xlen) >= 64 + => mem_write_value(paddr, 8, rs2_val, aq, rl, false), + _ => report_invalid_width(__FILE__, __LINE__, width, "store"), + }; + match (res) { + MemValue(true) => RETIRE_SUCCESS, + MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalasr/sh.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalasr/sh.rl.yaml new file mode 100644 index 000000000000..952be9fea49d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalasr/sh.rl.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sh.rl +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zalasr +assembly: xs2, (xs1) +encoding: + match: 0011101----------001000000101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Write(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => { + let eares : MemoryOpResult(unit) = match width { + BYTE => mem_write_ea(paddr, 1, aq, rl, false), + HALF => mem_write_ea(paddr, 2, aq, rl, false), + WORD => mem_write_ea(paddr, 4, aq, rl, false), + DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let rs2_val = X(rs2); + let res : MemoryOpResult(bool) = match (width) { + BYTE => mem_write_value(paddr, 1, rs2_val[7..0], aq, rl, false), + HALF => mem_write_value(paddr, 2, rs2_val[15..0], aq, rl, false), + WORD => mem_write_value(paddr, 4, rs2_val[31..0], aq, rl, false), + DOUBLE if sizeof(xlen) >= 64 + => mem_write_value(paddr, 8, rs2_val, aq, rl, false), + _ => report_invalid_width(__FILE__, __LINE__, width, "store"), + }; + match (res) { + MemValue(true) => RETIRE_SUCCESS, + MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalasr/sw.rl.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalasr/sw.rl.yaml new file mode 100644 index 000000000000..3e05b643662d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalasr/sw.rl.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sw.rl +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zalasr +assembly: xs2, (xs1) +encoding: + match: 0011101----------010000000101111 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Write(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => { + let eares : MemoryOpResult(unit) = match width { + BYTE => mem_write_ea(paddr, 1, aq, rl, false), + HALF => mem_write_ea(paddr, 2, aq, rl, false), + WORD => mem_write_ea(paddr, 4, aq, rl, false), + DOUBLE => mem_write_ea(paddr, 8, aq, rl, false) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let rs2_val = X(rs2); + let res : MemoryOpResult(bool) = match (width) { + BYTE => mem_write_value(paddr, 1, rs2_val[7..0], aq, rl, false), + HALF => mem_write_value(paddr, 2, rs2_val[15..0], aq, rl, false), + WORD => mem_write_value(paddr, 4, rs2_val[31..0], aq, rl, false), + DOUBLE if sizeof(xlen) >= 64 + => mem_write_value(paddr, 8, rs2_val, aq, rl, false), + _ => report_invalid_width(__FILE__, __LINE__, width, "store"), + }; + match (res) { + MemValue(true) => RETIRE_SUCCESS, + MemValue(false) => internal_error(__FILE__, __LINE__, "store got false from mem_write_value"), + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalrsc/lr.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalrsc/lr.d.yaml new file mode 100644 index 000000000000..6fccd1d49257 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalrsc/lr.d.yaml @@ -0,0 +1,147 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lr.d +long_name: Load reserved doubleword +description: | + Loads a word from the address in xs1, places the value in xd, + and registers a _reservation set_ -- a set of bytes that subsumes the bytes in the + addressed word. + + The address in xs1 must be 8-byte aligned. + + If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an + `LoadAccessFault` exception will be generated. The access-fault exception can be generated + for a memory access that would otherwise be able to complete except for the misalignment, + if the misaligned access should not be emulated. + + An implementation can register an arbitrarily large reservation set on each LR, provided the + reservation set includes all bytes of the addressed data word or doubleword. + An SC can only pair with the most recent LR in program order. + An SC may succeed only if no store from another hart to the reservation set can be + observed to have occurred between the LR and the SC, and if there is no other SC between the + LR and itself in program order. + An SC may succeed only if no write from a device other than a hart to the bytes accessed by + the LR instruction can be observed to have occurred between the LR and SC. Note this LR + might have had a different effective address and data size, but reserved the SC's + address as part of the reservation set. + + [NOTE] + ---- + Following this model, in systems with memory translation, an SC is allowed to succeed if the + earlier LR reserved the same location using an alias with a different virtual address, but is + also allowed to fail if the virtual address is different. + + To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only + required to invalidate reservations when they overlap the bytes accessed by the LR. + These writes are not required to invalidate the reservation when they access other bytes in + the reservation set. + ---- + + Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. + LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those + with both bits clear, but may result in lower performance. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zalrsc +assembly: xd, (xs1) +encoding: + match: 00010--00000-----011-----0101111 + variables: + - name: aq + location: 26 + not: 1 + - name: rl + location: 25 + not: 1 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) { + # even though this is a memory operation, the exception occurs before that would be known, + # so mode() is the correct reporting mode rathat than effective_ldst_mode() + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + + if (!is_naturally_aligned<64>(virtual_address)) { + # can raise either LoadAddressMisaligned *or* LoadAccessFault + # + # from the spec: + # If the address is not naturally aligned, an address-misaligned exception or + # an access-fault exception will be generated. The access-fault exception can + # be generated for a memory access that would otherwise be able to complete except + # for the misalignment, if the misaligned access should not be emulated. + + if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") { + raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address); + } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") { + raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address); + } else { + unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned"); + } + } + + X[xd] = load_reserved<32>(virtual_address, aq, rl, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Extensions might perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + let aligned : bool = + /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt + * to treat them as valid here; otherwise we'd need to throw an internal_error. + */ + match width { + BYTE => true, + HALF => vaddr[0..0] == 0b0, + WORD => vaddr[1..0] == 0b00, + DOUBLE => vaddr[2..0] == 0b000 + }; + /* "LR faults like a normal load, even though it's in the AMO major opcode space." + * - Andrew Waterman, isa-dev, 10 Jul 2018. + */ + if not(aligned) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => + match (width, sizeof(xlen)) { + (BYTE, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 1, aq, aq & rl, true), false), + (HALF, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 2, aq, aq & rl, true), false), + (WORD, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 4, aq, aq & rl, true), false), + (DOUBLE, 64) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 8, aq, aq & rl, true), false), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalrsc/lr.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalrsc/lr.w.yaml new file mode 100644 index 000000000000..06029674bcdb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalrsc/lr.w.yaml @@ -0,0 +1,155 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: lr.w +long_name: Load reserved word +description: | + Loads a word from the address in xs1, places the sign-extended value in xd, + and registers a _reservation set_ -- a set of bytes that subsumes the bytes in the + addressed word. + + <%- if MXLEN == 64 -%> + The 32-bit load result is sign-extended to 64-bits. + <%- end -%> + + The address in xs1 must be naturally aligned to the size of the operand + (_i.e._, eight-byte aligned for doublewords and four-byte aligned for words). + + If the address is not naturally aligned, a `LoadAddressMisaligned` exception or an + `LoadAccessFault` exception will be generated. The access-fault exception can be generated + for a memory access that would otherwise be able to complete except for the misalignment, + if the misaligned access should not be emulated. + + An implementation can register an arbitrarily large reservation set on each LR, provided the + reservation set includes all bytes of the addressed data word or doubleword. + An SC can only pair with the most recent LR in program order. + An SC may succeed only if no store from another hart to the reservation set can be + observed to have occurred between the LR and the SC, and if there is no other SC between the + LR and itself in program order. + An SC may succeed only if no write from a device other than a hart to the bytes accessed by + the LR instruction can be observed to have occurred between the LR and SC. Note this LR + might have had a different effective address and data size, but reserved the SC's + address as part of the reservation set. + + [NOTE] + ---- + Following this model, in systems with memory translation, an SC is allowed to succeed if the + earlier LR reserved the same location using an alias with a different virtual address, but is + also allowed to fail if the virtual address is different. + + To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only + required to invalidate reservations when they overlap the bytes accessed by the LR. + These writes are not required to invalidate the reservation when they access other bytes in + the reservation set. + ---- + + Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. + LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those + with both bits clear, but may result in lower performance. +definedBy: + extension: + name: Zalrsc +assembly: xd, (xs1) +encoding: + match: 00010--00000-----010-----0101111 + variables: + - name: aq + location: 26 + not: 1 + - name: rl + location: 25 + not: 1 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) { + # even though this is a memory operation, the exception occurs before that would be known, + # so mode() is the correct reporting mode rathat than effective_ldst_mode() + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + + if (!is_naturally_aligned<32>(virtual_address)) { + # can raise either LoadAddressMisaligned *or* LoadAccessFault + # + # from the spec: + # If the address is not naturally aligned, an address-misaligned exception or + # an access-fault exception will be generated. The access-fault exception can + # be generated for a memory access that would otherwise be able to complete except + # for the misalignment, if the misaligned access should not be emulated. + + if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") { + raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address); + } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") { + raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address); + } else { + unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned"); + } + } + + XReg load_value = load_reserved<32>(virtual_address, aq, rl, $encoding); + if (xlen() == 64) { + X[xd] = load_value; + } else { + X[xd] = sext(load_value[31:0], 32); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if extension("A") then { + /* Get the address, X(rs1) (no offset). + * Extensions might perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + let aligned : bool = + /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt + * to treat them as valid here; otherwise we'd need to throw an internal_error. + */ + match width { + BYTE => true, + HALF => vaddr[0..0] == 0b0, + WORD => vaddr[1..0] == 0b00, + DOUBLE => vaddr[2..0] == 0b000 + }; + /* "LR faults like a normal load, even though it's in the AMO major opcode space." + * - Andrew Waterman, isa-dev, 10 Jul 2018. + */ + if not(aligned) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => + match (width, sizeof(xlen)) { + (BYTE, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 1, aq, aq & rl, true), false), + (HALF, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 2, aq, aq & rl, true), false), + (WORD, _) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 4, aq, aq & rl, true), false), + (DOUBLE, 64) => process_loadres(rd, vaddr, mem_read(Read(Data), addr, 8, aq, aq & rl, true), false), + _ => internal_error(__FILE__, __LINE__, "Unexpected AMO width") + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalrsc/sc.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalrsc/sc.d.yaml new file mode 100644 index 000000000000..884123d93090 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalrsc/sc.d.yaml @@ -0,0 +1,239 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sc.d +long_name: Store conditional doubleword +description: | + `sc.d` conditionally writes a doubleword in _xs2_ to the address in _xs1_: + the `sc.d` succeeds only if the reservation is still valid and the + reservation set contains the bytes being written. If the `sc.d` succeeds, + the instruction writes the doubleword in _xs2_ to memory, and it writes zero to _xd_. + If the `sc.d` fails, the instruction does not write to memory, and it writes a + nonzero value to _xd_. For the purposes of memory protection, a failed `sc.d` + may be treated like a store. Regardless of success or failure, executing an + `sc.d` instruction invalidates any reservation held by this hart. + + The failure code with value 1 encodes an unspecified failure. + Other failure codes are reserved at this time. + Portable software should only assume the failure code will be non-zero. + + The address held in _xs1_ must be naturally aligned to the size of the operand + (_i.e._, eight-byte aligned). + If the address is not naturally aligned, an address-misaligned exception or an + access-fault exception will be generated. + The access-fault exception can be generated for a memory access that would otherwise + be able to complete except for the misalignment, + if the misaligned access should not be emulated. + + [NOTE] + -- + Emulating misaligned LR/SC sequences is impractical in most systems. + + Misaligned LR/SC sequences also raise the possibility of accessing multiple + reservation sets at once, which present definitions do not provide for. + -- + + An implementation can register an arbitrarily large reservation set on each LR, + provided the reservation set includes all bytes of the addressed data word or + doubleword. + An SC can only pair with the most recent LR in program order. + An SC may succeed only if no store from another hart to the reservation set + can be observed to have occurred between the LR and the SC, + and if there is no other SC between the LR and itself in program order. + An SC may succeed only if no write from a device other than a hart to the bytes + accessed by the LR instruction can be observed to have occurred between the LR + and SC. + Note this LR might have had a different effective address and data size, + but reserved the SC's address as part of the reservation set. + + [NOTE] + ---- + Following this model, in systems with memory translation, an SC is allowed to succeed if the + earlier LR reserved the same location using an alias with a different virtual address, but is + also allowed to fail if the virtual address is different. + + To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only + required to invalidate reservations when they overlap the bytes accessed by the LR. + These writes are not required to invalidate the reservation when they access other bytes in + the reservation set. + ---- + + The SC must fail if the address is not within the reservation set of the most + recent LR in program order. + The SC must fail if a store to the reservation set from another hart can be + observed to occur between the LR and SC. + The SC must fail if a write from some other device to the bytes accessed by the + LR can be observed to occur between the LR and SC. + (If such a device writes the reservation set but does not write the bytes accessed + by the LR, the SC may or may not fail.) + An SC must fail if there is another SC (to any address) between the LR and the SC + in program order. + The precise statement of the atomicity requirements for successful LR/SC sequences + is defined by the Atomicity Axiom of the memory model. + + [NOTE] + -- + The platform should provide a means to determine the size and shape of the reservation set. + + A platform specification may constrain the size and shape of the reservation set. + + A store-conditional instruction to a scratch word of memory should be used to forcibly invalidate any existing load reservation: + + * during a preemptive context switch, and + * if necessary when changing virtual to physical address mappings, such as when migrating pages that might contain an active reservation. + + The invalidation of a hart's reservation when it executes an LR or SC imply that a hart can only hold one reservation at a time, and that an SC can only pair with the most recent LR, and LR with the next following SC, in program order. This is a restriction to the Atomicity Axiom in Section 18.1 that ensures software runs correctly on expected common implementations that operate in this manner. + -- + + An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation. + + [NOTE] + -- + The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. The LR/SC sequence can be given release semantics by by setting the rl bit on the SC instruction. Assuming suitable mappings for other atomic operations, setting the aq bit on the LR instruction, and setting the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent in the C++ memory_order_seq_cst sense. Such a sequence does not act as a fence for ordering ordinary load and store instructions before and after the sequence. Specific instruction mappings for other C++ atomic operations, or stronger notions of "sequential consistency", may require both bits to be set on either or both of the LR or SC instruction. + + If neither bit is set on either LR or SC, the LR/SC sequence can be observed to occur before or after surrounding memory operations from the same RISC-V hart. This can be appropriate when the LR/SC sequence is used to implement a parallel reduction operation. + -- + + Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. + LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those + with both bits clear, but may result in lower performance. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zalrsc +assembly: xd, xs2, (xs1) +encoding: + match: 00011------------011-----0101111 + variables: + - name: aq + location: 26 + - name: rl + location: 25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) { + # even though this is a memory operation, the exception occurs before that would be known, + # so mode() is the correct reporting mode rathat than effective_ldst_mode() + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + XReg value = X[xs2]; + + if (!is_naturally_aligned<64>(virtual_address)) { + # can raise either LoadAddressMisaligned *or* LoadAccessFault + # + # from the spec: + # If the address is not naturally aligned, an address-misaligned exception or + # an access-fault exception will be generated. The access-fault exception can + # be generated for a memory access that would otherwise be able to complete except + # for the misalignment, if the misaligned access should not be emulated. + + if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") { + raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address); + } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") { + raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address); + } else { + unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned"); + } + } + + Boolean success = store_conditional<64>(virtual_address, value, aq, rl, $encoding); + X[xd] = success ? 0 : 1; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if speculate_conditional () == false then { + /* should only happen in rmem + * rmem: allow SC to fail very early + */ + X(rd) = zero_extend(0b1); RETIRE_SUCCESS + } else { + if extension("A") then { + /* normal non-rmem case + * rmem: SC is allowed to succeed (but might fail later) + */ + /* Get the address, X(rs1) (no offset). + * Extensions might perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + let aligned : bool = + /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt + * to treat them as valid here; otherwise we'd need to throw an internal_error. + */ + match width { + BYTE => true, + HALF => vaddr[0..0] == 0b0, + WORD => vaddr[1..0] == 0b00, + DOUBLE => vaddr[2..0] == 0b000 + }; + if not(aligned) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else { + if match_reservation(vaddr) == false then { + /* cannot happen in rmem */ + X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS + } else { + match translateAddr(vaddr, Write(Data)) { /* Write and ReadWrite are equivalent here: + * both result in a SAMO exception */ + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "STORECON expected word or double") + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + rs2_val = X(rs2); + let res : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, rs2_val[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, rs2_val[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, rs2_val[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, rs2_val, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "STORECON expected word or double") + }; + match (res) { + MemValue(true) => { X(rd) = zero_extend(0b0); cancel_reservation(); RETIRE_SUCCESS }, + MemValue(false) => { X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zalrsc/sc.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zalrsc/sc.w.yaml new file mode 100644 index 000000000000..8c0907f49272 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zalrsc/sc.w.yaml @@ -0,0 +1,245 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sc.w +long_name: Store conditional word +description: | + `sc.w` conditionally writes a word in _xs2_ to the address in _xs1_: + the `sc.w` succeeds only if the reservation is still valid and the + reservation set contains the bytes being written. If the `sc.w` succeeds, + the instruction writes the word in _xs2_ to memory, and it writes zero to _xd_. + If the `sc.w` fails, the instruction does not write to memory, and it writes a + nonzero value to _xd_. For the purposes of memory protection, a failed `sc.w` + may be treated like a store. Regardless of success or failure, executing an + `sc.w` instruction invalidates any reservation held by this hart. + + <%- if MXLEN == 64 -%> + [NOTE] + If a value other than 0 or 1 is defined as a result for `sc.w`, the value will before + sign-extended into _xd_. + <%- end -%> + + The failure code with value 1 encodes an unspecified failure. + Other failure codes are reserved at this time. + Portable software should only assume the failure code will be non-zero. + + The address held in _xs1_ must be naturally aligned to the size of the operand + (_i.e._, eight-byte aligned for doublewords and four-byte aligned for words). + If the address is not naturally aligned, an address-misaligned exception or an + access-fault exception will be generated. + The access-fault exception can be generated for a memory access that would otherwise + be able to complete except for the misalignment, + if the misaligned access should not be emulated. + + [NOTE] + -- + Emulating misaligned LR/SC sequences is impractical in most systems. + + Misaligned LR/SC sequences also raise the possibility of accessing multiple + reservation sets at once, which present definitions do not provide for. + -- + + An implementation can register an arbitrarily large reservation set on each LR, + provided the reservation set includes all bytes of the addressed data word or + doubleword. + An SC can only pair with the most recent LR in program order. + An SC may succeed only if no store from another hart to the reservation set + can be observed to have occurred between the LR and the SC, + and if there is no other SC between the LR and itself in program order. + An SC may succeed only if no write from a device other than a hart to the bytes + accessed by the LR instruction can be observed to have occurred between the LR + and SC. + Note this LR might have had a different effective address and data size, + but reserved the SC's address as part of the reservation set. + + [NOTE] + ---- + Following this model, in systems with memory translation, an SC is allowed to succeed if the + earlier LR reserved the same location using an alias with a different virtual address, but is + also allowed to fail if the virtual address is different. + + To accommodate legacy devices and buses, writes from devices other than RISC-V harts are only + required to invalidate reservations when they overlap the bytes accessed by the LR. + These writes are not required to invalidate the reservation when they access other bytes in + the reservation set. + ---- + + The SC must fail if the address is not within the reservation set of the most + recent LR in program order. + The SC must fail if a store to the reservation set from another hart can be + observed to occur between the LR and SC. + The SC must fail if a write from some other device to the bytes accessed by the + LR can be observed to occur between the LR and SC. + (If such a device writes the reservation set but does not write the bytes accessed + by the LR, the SC may or may not fail.) + An SC must fail if there is another SC (to any address) between the LR and the SC + in program order. + The precise statement of the atomicity requirements for successful LR/SC sequences + is defined by the Atomicity Axiom of the memory model. + + [NOTE] + -- + The platform should provide a means to determine the size and shape of the reservation set. + + A platform specification may constrain the size and shape of the reservation set. + + A store-conditional instruction to a scratch word of memory should be used to forcibly invalidate any existing load reservation: + + * during a preemptive context switch, and + * if necessary when changing virtual to physical address mappings, such as when migrating pages that might contain an active reservation. + + The invalidation of a hart's reservation when it executes an LR or SC imply that a hart can only hold one reservation at a time, and that an SC can only pair with the most recent LR, and LR with the next following SC, in program order. This is a restriction to the Atomicity Axiom in Section 18.1 that ensures software runs correctly on expected common implementations that operate in this manner. + -- + + An SC instruction can never be observed by another RISC-V hart before the LR instruction that established the reservation. + + [NOTE] + -- + The LR/SC sequence can be given acquire semantics by setting the aq bit on the LR instruction. The LR/SC sequence can be given release semantics by by setting the rl bit on the SC instruction. Assuming suitable mappings for other atomic operations, setting the aq bit on the LR instruction, and setting the rl bit on the SC instruction makes the LR/SC sequence sequentially consistent in the C++ memory_order_seq_cst sense. Such a sequence does not act as a fence for ordering ordinary load and store instructions before and after the sequence. Specific instruction mappings for other C++ atomic operations, or stronger notions of "sequential consistency", may require both bits to be set on either or both of the LR or SC instruction. + + If neither bit is set on either LR or SC, the LR/SC sequence can be observed to occur before or after surrounding memory operations from the same RISC-V hart. This can be appropriate when the LR/SC sequence is used to implement a parallel reduction operation. + -- + + Software should not set the _rl_ bit on an LR instruction unless the _aq_ bit is also set. + LR.rl and SC.aq instructions are not guaranteed to provide any stronger ordering than those + with both bits clear, but may result in lower performance. +definedBy: + extension: + name: Zalrsc +assembly: xd, xs2, (xs1) +encoding: + match: 00011------------010-----0101111 + variables: + - name: aq + location: 26 + not: 1 + - name: rl + location: 25 + not: 1 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::A) && (CSR[misa].A == 1'b0)) { + # even though this is a memory operation, the exception occurs before that would be known, + # so mode() is the correct reporting mode rathat than effective_ldst_mode() + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[xs1]; + XReg value = X[xs2]; + + if (!is_naturally_aligned<32>(virtual_address)) { + # can raise either LoadAddressMisaligned *or* LoadAccessFault + # + # from the spec: + # If the address is not naturally aligned, an address-misaligned exception or + # an access-fault exception will be generated. The access-fault exception can + # be generated for a memory access that would otherwise be able to complete except + # for the misalignment, if the misaligned access should not be emulated. + + if (LRSC_MISALIGNED_BEHAVIOR == "always raise misaligned exception") { + raise(ExceptionCode::LoadAddressMisaligned, effective_ldst_mode(), virtual_address); + } else if (LRSC_MISALIGNED_BEHAVIOR == "always raise access fault") { + raise(ExceptionCode::LoadAccessFault, effective_ldst_mode(), virtual_address); + } else { + unpredictable("Implementations may raise either a LoadAddressMisaligned or a LoadAccessFault when an LR/SC address is misaligned"); + } + } + + Boolean success = store_conditional<32>(virtual_address, value, aq, rl, $encoding); + X[xd] = success ? 0 : 1; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + if speculate_conditional () == false then { + /* should only happen in rmem + * rmem: allow SC to fail very early + */ + X(rd) = zero_extend(0b1); RETIRE_SUCCESS + } else { + if extension("A") then { + /* normal non-rmem case + * rmem: SC is allowed to succeed (but might fail later) + */ + /* Get the address, X(rs1) (no offset). + * Extensions might perform additional checks on address validity. + */ + match ext_data_get_addr(rs1, zeros(), Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => { + let aligned : bool = + /* BYTE and HALF would only occur due to invalid decodes, but it doesn't hurt + * to treat them as valid here; otherwise we'd need to throw an internal_error. + */ + match width { + BYTE => true, + HALF => vaddr[0..0] == 0b0, + WORD => vaddr[1..0] == 0b00, + DOUBLE => vaddr[2..0] == 0b000 + }; + if not(aligned) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else { + if match_reservation(vaddr) == false then { + /* cannot happen in rmem */ + X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS + } else { + match translateAddr(vaddr, Write(Data)) { /* Write and ReadWrite are equivalent here: + * both result in a SAMO exception */ + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_ea(addr, 1, aq & rl, rl, true), + (HALF, _) => mem_write_ea(addr, 2, aq & rl, rl, true), + (WORD, _) => mem_write_ea(addr, 4, aq & rl, rl, true), + (DOUBLE, 64) => mem_write_ea(addr, 8, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "STORECON expected word or double") + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + rs2_val = X(rs2); + let res : MemoryOpResult(bool) = match (width, sizeof(xlen)) { + (BYTE, _) => mem_write_value(addr, 1, rs2_val[7..0], aq & rl, rl, true), + (HALF, _) => mem_write_value(addr, 2, rs2_val[15..0], aq & rl, rl, true), + (WORD, _) => mem_write_value(addr, 4, rs2_val[31..0], aq & rl, rl, true), + (DOUBLE, 64) => mem_write_value(addr, 8, rs2_val, aq & rl, rl, true), + _ => internal_error(__FILE__, __LINE__, "STORECON expected word or double") + }; + match (res) { + MemValue(true) => { X(rd) = zero_extend(0b0); cancel_reservation(); RETIRE_SUCCESS }, + MemValue(false) => { X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS }, + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL } + } + } + } + } + } + } + } + } + } + } else { + handle_illegal(); + RETIRE_FAIL + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zawrs/wrs.nto.yaml b/pkg/ifuzz/riscv64/gen/inst/Zawrs/wrs.nto.yaml new file mode 100644 index 000000000000..18bf11a66950 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zawrs/wrs.nto.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: wrs.nto +long_name: Wait-on-Reservation-Set-with-No-Timeout +description: | + To mitigate the wasteful looping in such usages, a `wrs.nto` (WRS-with-no-timeout) instruction is provided. + Instead of polling for a store to a specific memory location, software registers a reservation set that + includes all the bytes of the memory location using the LR instruction. Then a subsequent `wrs.nto` + instruction would cause the hart to temporarily stall execution in a low-power state until a store + occurs to the reservation set or an interrupt is observed. + + This instruction is not supported in a constrained LR/SC loop. + While stalled, an implementation is permitted to occasionally terminate the stall and complete + execution for any reason. + + `wrs.nto` follows the rules of the WFI instruction for resuming execution + on a pending interrupt. + + When the TW (Timeout Wait) bit in `mstatus` is set and `wrs.nto` is executed + in any privilege mode otherthan M mode, and it does not complete within an implementation-specific + bounded time limit, the `wrs.nto` instruction will cause an illegal instruction exception. + + When executing in VS or VU mode, if the VTW bit is set in `hstatus`, the TW bit in `mstatus` is clear, + and the `wrs.nto` does not complete within an implementation-specific bounded time limit, + the `wrs.nto` instruction will cause a virtual instruction exception. + + [Note] + Since `wrs.nto` can complete execution for reasons other than stores to the reservation set, + software will likely need a means of looping until the required stores have occurred. + + [Note] + `wrs.nto`, unlike WFI, is not specified to cause an illegal instruction exception if executed in U-mode + when the governing TW bit is 0. WFI is typically not expected to be used in U-mode and on many systems + may promptly cause an illegal instruction exception if used at U-mode. + Unlike WFI, `wrs.nto` is expected to be used by software in U-mode when waiting on memory but without + a deadline for that wait. +definedBy: + extension: + name: Zawrs +assembly: "" +encoding: + match: "00000000110100000000000001110011" + variables: [] +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zawrs/wrs.sto.yaml b/pkg/ifuzz/riscv64/gen/inst/Zawrs/wrs.sto.yaml new file mode 100644 index 000000000000..0961babebba8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zawrs/wrs.sto.yaml @@ -0,0 +1,51 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: wrs.sto +long_name: Wait-on-Reservation-Set-with-Short-Timeout +description: | + Instead of polling for a store to a specific memory location, software registers a + reservation set that includes all the bytes of the memory location using the LR instruction. + A subsequent `wrs.sto` instruction would cause the hart to temporarily stall execution in a + low-power state until a store occurs to the reservation set or an interrupt is observed. + Sometimes the program waiting on a memory update may also need to carry out a task at a future time + or otherwise place an upper bound on the wait. To support such use cases, `wrs.sto` bounds the + stall duration to an implementation-define short timeout such that the stall is terminated on the + timeout if no other conditions have occurred to terminate the stall. The program using this instruction + may then determine if its deadline has been reached. + `wrs.sto` causes the hart to temporarily stall execution in a low-power state as long as the reservation + set is valid and no pending interrupts, even if disabled, are observed. For `wrs.sto` the stall duration + is bounded by an implementation defined short timeout. These instructions are not supported in a + constrained LR/SC loop. + Hart execution may be stalled while the following conditions are all satisfied: + a. The reservation set is valid + b. If `wrs.sto`, a "short" duration since start of stall has not elapsed + c. No pending interrupt is observed (see the rules below) + + While stalled, an implementation is permitted to occasionally terminate the stall and complete + execution for any reason. `wrs.sto` follows the rules of the WFI instruction for resuming execution + on a pending interrupt. Since `wrs.sto` can complete execution for reasons other than stores to + the reservation set, software will likely need a means of looping until the required stores have occurred. + + [Note] + The duration of a `wrs.sto` instruction's timeout may vary significantly within and among implementations. + In typical implementations this duration should be roughly in the range of 10 to 100 times an on-chip + cache miss latency or a cacheless access to main memory. +definedBy: + extension: + name: Zawrs +assembly: "" +encoding: + match: "00000001110100000000000001110011" + variables: [] +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zba/add.uw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zba/add.uw.yaml new file mode 100644 index 000000000000..80527e648e82 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zba/add.uw.yaml @@ -0,0 +1,63 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: add.uw +long_name: Add unsigned word +description: | + Performs an XLEN-wide addition between xs2 and the + zero-extended least-significant word of xs1. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zba +assembly: xd, xs1, xs2 +format: + $inherits: + - inst_subtype/R/R-x.yaml#/data + opcodes: + funct7: + display_name: ADD.UW + value: 0b0000100 + funct3: + display_name: ADD.UW + value: 0b000 + opcode: { $inherits: inst_opcode/OP-32.yaml#/data } +access: + s: always + u: always + vs: always + vu: always +pseudoinstructions: + - when: xs2 == 0 + to: zext.w xd, xs1 +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs2] + X[xs1][31:0]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let shamt : bits(2) = match op { + RISCV_ADDUW => 0b00, + RISCV_SH1ADDUW => 0b01, + RISCV_SH2ADDUW => 0b10, + RISCV_SH3ADDUW => 0b11 + }; + let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zba/sh1add.uw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zba/sh1add.uw.yaml new file mode 100644 index 000000000000..dddc73d429b3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zba/sh1add.uw.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sh1add.uw +long_name: Shift unsigned word left by 1 and add +description: | + Performs an XLEN-wide addition of two addends. The first addend is xs2. + The second addend is the unsigned value formed by extracting the least-significant word of xs1 + and shifting it left by 1 place. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zba +encoding: + match: 0010000----------010-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +assembly: xd, xs1, xs2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs2] + (X[xs1][31:0] << 1); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let shamt : bits(2) = match op { + RISCV_ADDUW => 0b00, + RISCV_SH1ADDUW => 0b01, + RISCV_SH2ADDUW => 0b10, + RISCV_SH3ADDUW => 0b11 + }; + let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zba/sh1add.yaml b/pkg/ifuzz/riscv64/gen/inst/Zba/sh1add.yaml new file mode 100644 index 000000000000..eceeb0fff673 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zba/sh1add.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sh1add +long_name: Shift left by 1 and add +description: | + Shifts `xs1` to the left by 1 bit and adds it to `xs2`. +definedBy: + extension: + name: Zba +assembly: xd, xs1, xs2 +encoding: + match: 0010000----------010-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs2] + (X[xs1] << 1); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let shamt : bits(2) = match op { + RISCV_SH1ADD => 0b01, + RISCV_SH2ADD => 0b10, + RISCV_SH3ADD => 0b11 + }; + let result : xlenbits = (rs1_val << shamt) + rs2_val; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zba/sh2add.uw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zba/sh2add.uw.yaml new file mode 100644 index 000000000000..477488c3e80c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zba/sh2add.uw.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sh2add.uw +long_name: Shift unsigned word left by 2 and add +description: | + Performs an XLEN-wide addition of two addends. The first addend is xs2. + The second addend is the unsigned value formed by extracting the least-significant word of xs1 + and shifting it left by 2 places. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zba +assembly: xd, xs1, xs2 +encoding: + match: 0010000----------100-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs2] + (X[xs1][31:0] << 2); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let shamt : bits(2) = match op { + RISCV_ADDUW => 0b00, + RISCV_SH1ADDUW => 0b01, + RISCV_SH2ADDUW => 0b10, + RISCV_SH3ADDUW => 0b11 + }; + let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zba/sh2add.yaml b/pkg/ifuzz/riscv64/gen/inst/Zba/sh2add.yaml new file mode 100644 index 000000000000..fe719b8ab636 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zba/sh2add.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sh2add +long_name: Shift left by 2 and add +description: | + Shifts `xs1` to the left by 2 places and adds it to `xs2`. +definedBy: + extension: + name: Zba +assembly: xd, xs1, xs2 +encoding: + match: 0010000----------100-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs2] + (X[xs1] << 2); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let shamt : bits(2) = match op { + RISCV_SH1ADD => 0b01, + RISCV_SH2ADD => 0b10, + RISCV_SH3ADD => 0b11 + }; + let result : xlenbits = (rs1_val << shamt) + rs2_val; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zba/sh3add.uw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zba/sh3add.uw.yaml new file mode 100644 index 000000000000..253eb64c9c36 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zba/sh3add.uw.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sh3add.uw +long_name: Shift unsigned word left by 3 and add +description: | + Performs an XLEN-wide addition of two addends. The first addend is xs2. + The second addend is the unsigned value formed by extracting the least-significant word of xs1 + and shifting it left by 3 places. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zba +assembly: xd, xs1, xs2 +encoding: + match: 0010000----------110-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs2] + (X[xs1][31:0] << 3); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let shamt : bits(2) = match op { + RISCV_ADDUW => 0b00, + RISCV_SH1ADDUW => 0b01, + RISCV_SH2ADDUW => 0b10, + RISCV_SH3ADDUW => 0b11 + }; + let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zba/sh3add.yaml b/pkg/ifuzz/riscv64/gen/inst/Zba/sh3add.yaml new file mode 100644 index 000000000000..a0aed38ec15e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zba/sh3add.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sh3add +long_name: Shift left by 3 and add +description: | + Shifts `xs1` to the left by 3 places and adds it to `xs2`. +definedBy: + extension: + name: Zba +assembly: xd, xs1, xs2 +encoding: + match: 0010000----------110-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs2] + (X[xs1] << 3); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let shamt : bits(2) = match op { + RISCV_SH1ADD => 0b01, + RISCV_SH2ADD => 0b10, + RISCV_SH3ADD => 0b11 + }; + let result : xlenbits = (rs1_val << shamt) + rs2_val; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zba/slli.uw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zba/slli.uw.yaml new file mode 100644 index 000000000000..2e376408f5df --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zba/slli.uw.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: slli.uw +long_name: Shift left unsigned word (Immediate) +description: | + Takes the least-significant word of xs1, zero-extends it, and shifts it + left by the immediate. + + [NOTE] + This instruction is the same as `slli` with `zext.w` performed on xs1 before shifting. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zba +encoding: + match: 000010-----------001-----0011011 + variables: + - name: shamt + location: 25-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +assembly: xd, xs1, shamt +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs1][31:0] << shamt; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let result : xlenbits = zero_extend(rs1_val[31..0]) << shamt; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/clz.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/clz.yaml new file mode 100644 index 000000000000..348dedceab40 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/clz.yaml @@ -0,0 +1,54 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: clz +long_name: Count leading zero bits +description: | + Counts the number of 0's before the first 1, + starting at the most-significant bit (i.e., XLEN-1) and progressing to bit 0. + Accordingly, if the input is 0, the output is XLEN, and if the most-significant + bit of the input is a 1, the output is 0. +definedBy: + extension: + name: Zbb +assembly: xd, xs1 +encoding: + match: 011000000000-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = (xlen() - 1) - $signed(highest_set_bit(X[xs1])); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + result : nat = 0; + done : bool = false; + foreach (i from (sizeof(xlen) - 1) downto 0) + if not(done) then if rs1_val[i] == bitzero + then result = result + 1 + else done = true; + X(rd) = to_bits(sizeof(xlen), result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/clzw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/clzw.yaml new file mode 100644 index 000000000000..9cd583e33ac1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/clzw.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: clzw +long_name: Count leading zero bits in word +description: | + Counts the number of 0's before the first 1 starting at bit 31 and progressing to bit 0. + Accordingly, if the least-significant word is 0, the output is 32, and if the most-significant + bit of the word (_i.e._, bit 31) is a 1, the output is 0. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zbb +assembly: xd, xs1 +encoding: + match: 011000000000-----001-----0011011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = 31 - $signed(highest_set_bit(X[xs1][31:0])); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + result : nat = 0; + done : bool = false; + foreach (i from 31 downto 0) + if not(done) then if rs1_val[i] == bitzero + then result = result + 1 + else done = true; + X(rd) = to_bits(sizeof(xlen), result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/cpop.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/cpop.yaml new file mode 100644 index 000000000000..a9461fe0840d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/cpop.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cpop +long_name: Count set bits +description: | + Counts the number of 1's (i.e., set bits) in the source register. + + .Software Hint + [NOTE] + ---- + This operations is known as population count, popcount, sideways sum, + bit summation, or Hamming weight. + + The GCC builtin function `__builtin_popcount (unsigned int x)` is + implemented by cpop on RV32 and by cpopw on RV64. The GCC builtin + function `__builtin_popcountl (unsigned long x)` for LP64 is + implemented by cpop on RV64. + ---- +definedBy: + extension: + name: Zbb +assembly: xd, xs1 +encoding: + match: 011000000010-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg bitcount = 0; + XReg xs1_val = X[xs1]; + + for (U32 i=0; i < xlen(); i++) { + if (xs1_val[i] == 1'b1) { + bitcount = bitcount + 1; + } + } + + X[xd] = bitcount; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + result : nat = 0; + foreach (i from 0 to (xlen_val - 1)) + if rs1_val[i] == bitone then result = result + 1; + X(rd) = to_bits(sizeof(xlen), result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/cpopw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/cpopw.yaml new file mode 100644 index 000000000000..5a7c2211df19 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/cpopw.yaml @@ -0,0 +1,71 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cpopw +long_name: Count set bits in word +description: | + Counts the number of 1's (i.e., set bits) in the least-significant word of the source register. + + .Software Hint + [NOTE] + ---- + This operations is known as population count, popcount, sideways sum, + bit summation, or Hamming weight. + + The GCC builtin function `__builtin_popcount (unsigned int x)` is + implemented by cpop on RV32 and by cpopw on RV64. The GCC builtin + function `__builtin_popcountl (unsigned long x)` for LP64 is + implemented by cpop on RV64. + ---- +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zbb +assembly: xd, xs1 +encoding: + match: 011000000010-----001-----0011011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg bitcount = 0; + XReg xs1_val = X[xs1]; + + for (U32 i=0; i < 32; i++) { + if (xs1_val[i] == 1'b1) { + bitcount = bitcount + 1; + } + } + + X[xd] = bitcount; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + result : nat = 0; + foreach (i from 0 to 31) + if rs1_val[i] == bitone then result = result + 1; + X(rd) = to_bits(sizeof(xlen), result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/ctz.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/ctz.yaml new file mode 100644 index 000000000000..175e8136a0e3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/ctz.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: ctz +long_name: Count trailing zero bits +description: | + Counts the number of 0's before the first 1, + starting at the least-significant bit (i.e., 0) and progressing + to the most-significant bit (i.e., XLEN-1). Accordingly, if the + input is 0, the output is XLEN, and if the least-significant bit + of the input is a 1, the output is 0. +definedBy: + extension: + name: Zbb +assembly: xd, xs1 +encoding: + match: 011000000001-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (xlen() == 32) { + X[xd] = lowest_set_bit(X[xs1][31:0]); + } else { + X[xd] = lowest_set_bit(X[xs1]); + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + result : nat = 0; + done : bool = false; + foreach (i from 0 to (sizeof(xlen) - 1)) + if not(done) then if rs1_val[i] == bitzero + then result = result + 1 + else done = true; + X(rd) = to_bits(sizeof(xlen), result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/ctzw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/ctzw.yaml new file mode 100644 index 000000000000..7972ee93f6b4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/ctzw.yaml @@ -0,0 +1,57 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: ctzw +long_name: Count trailing zero bits in word +description: | + Counts the number of 0's before the first 1, + starting at the least-significant bit (i.e., 0) and progressing + to the most-significant bit of the least-significant word (i.e., 31). Accordingly, if the + least-significant word is 0, the output is 32, and if the least-significant bit + of the input is a 1, the output is 0. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zbb +assembly: xd, xs1 +encoding: + match: 011000000001-----001-----0011011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = lowest_set_bit(X[xs1][31:0]); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + result : nat = 0; + done : bool = false; + foreach (i from 0 to 31) + if not(done) then if rs1_val[i] == bitzero + then result = result + 1 + else done = true; + X(rd) = to_bits(sizeof(xlen), result); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/max.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/max.yaml new file mode 100644 index 000000000000..0224d11daf87 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/max.yaml @@ -0,0 +1,71 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: max +long_name: Maximum +description: | + Returns the larger of two signed integers. + + .Software Hint + [NOTE] + Calculating the absolute value of a signed integer can be performed using the + following sequence: `neg rD,rS` followed by `max rD,rS,rD. When using this + common sequence, it is suggested that they are scheduled with no intervening + instructions so that implementations that are so optimized can fuse them + together. +definedBy: + extension: + name: Zbb +assembly: xd, xs1, xs2 +encoding: + match: 0000101----------110-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = ($signed(X[xs1]) > $signed(X[xs2])) ? X[xs1] : X[xs2]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let result : xlenbits = match op { + RISCV_ANDN => rs1_val & ~(rs2_val), + RISCV_ORN => rs1_val | ~(rs2_val), + RISCV_XNOR => ~(rs1_val ^ rs2_val), + RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), + RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), + RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_ROL => if sizeof(xlen) == 32 + then rs1_val <<< rs2_val[4..0] + else rs1_val <<< rs2_val[5..0], + RISCV_ROR => if sizeof(xlen) == 32 + then rs1_val >>> rs2_val[4..0] + else rs1_val >>> rs2_val[5..0] + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/maxu.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/maxu.yaml new file mode 100644 index 000000000000..af074c08b45d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/maxu.yaml @@ -0,0 +1,63 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: maxu +long_name: Unsigned maximum +description: | + Returns the larger of two unsigned integers. +definedBy: + extension: + name: Zbb +assembly: xd, xs1, xs2 +encoding: + match: 0000101----------111-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = (X[xs1] > X[xs2]) ? X[xs1] : X[xs2]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let result : xlenbits = match op { + RISCV_ANDN => rs1_val & ~(rs2_val), + RISCV_ORN => rs1_val | ~(rs2_val), + RISCV_XNOR => ~(rs1_val ^ rs2_val), + RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), + RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), + RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_ROL => if sizeof(xlen) == 32 + then rs1_val <<< rs2_val[4..0] + else rs1_val <<< rs2_val[5..0], + RISCV_ROR => if sizeof(xlen) == 32 + then rs1_val >>> rs2_val[4..0] + else rs1_val >>> rs2_val[5..0] + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/min.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/min.yaml new file mode 100644 index 000000000000..dc7552f78dec --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/min.yaml @@ -0,0 +1,63 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: min +long_name: Minimum +description: | + Returns the smaller of two signed integers. +definedBy: + extension: + name: Zbb +assembly: xd, xs1, xs2 +encoding: + match: 0000101----------100-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = ($signed(X[xs1]) < $signed(X[xs2])) ? X[xs1] : X[xs2]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let result : xlenbits = match op { + RISCV_ANDN => rs1_val & ~(rs2_val), + RISCV_ORN => rs1_val | ~(rs2_val), + RISCV_XNOR => ~(rs1_val ^ rs2_val), + RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), + RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), + RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_ROL => if sizeof(xlen) == 32 + then rs1_val <<< rs2_val[4..0] + else rs1_val <<< rs2_val[5..0], + RISCV_ROR => if sizeof(xlen) == 32 + then rs1_val >>> rs2_val[4..0] + else rs1_val >>> rs2_val[5..0] + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/minu.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/minu.yaml new file mode 100644 index 000000000000..8d848d63b927 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/minu.yaml @@ -0,0 +1,63 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: minu +long_name: Unsigned minimum +description: | + Returns the smaller of two unsigned integers. +definedBy: + extension: + name: Zbb +assembly: xd, xs1, xs2 +encoding: + match: 0000101----------101-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = (X[xs1] < X[xs2]) ? X[xs1] : X[xs2]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let result : xlenbits = match op { + RISCV_ANDN => rs1_val & ~(rs2_val), + RISCV_ORN => rs1_val | ~(rs2_val), + RISCV_XNOR => ~(rs1_val ^ rs2_val), + RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))), + RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))), + RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))), + RISCV_ROL => if sizeof(xlen) == 32 + then rs1_val <<< rs2_val[4..0] + else rs1_val <<< rs2_val[5..0], + RISCV_ROR => if sizeof(xlen) == 32 + then rs1_val >>> rs2_val[4..0] + else rs1_val >>> rs2_val[5..0] + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/orc.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/orc.b.yaml new file mode 100644 index 000000000000..234afd7041cc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/orc.b.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: orc.b +long_name: Bitware OR-combine, byte granule +description: | + Combines the bits within each byte using bitwise logical OR. This sets the bits + of each byte in the result xd to all zeros if no bit within the respective byte + of xs1 is set, or to all ones if any bit within the respective byte of xs1 is set. +definedBy: + extension: + name: Zbb +assembly: xd, xs1 +encoding: + match: 001010000111-----101-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg input = X[xs1]; + XReg output = 0; + + for (U32 i=0; i<(xlen() - 8); i = i+8) { + output[(i+7):i] = (input[(i+7):i] == 0) ? 8'd0 : ~8'd0; + } + + X[xd] = output; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + result : xlenbits = zeros(); + foreach (i from 0 to (sizeof(xlen) - 8) by 8) + result[(i + 7) .. i] = if rs1_val[(i + 7) .. i] == zeros() + then 0x00 + else 0xFF; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/sext.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/sext.b.yaml new file mode 100644 index 000000000000..c6a5ac6d72a2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/sext.b.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sext.b +long_name: Sign-extend byte +description: | + Sign-extends the least-significant byte in the source to XLEN by copying the + most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. +definedBy: + extension: + name: Zbb +assembly: xd, xs1 +encoding: + match: 011000000100-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (xlen() == 32) { + X[xd] = {{24{X[xs1][7]}}, X[xs1][7:0]}; + } else if (xlen() == 64) { + X[xd] = {{56{X[xs1][7]}}, X[xs1][7:0]}; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]) + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/sext.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/sext.h.yaml new file mode 100644 index 000000000000..b1e019744862 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/sext.h.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sext.h +long_name: Sign-extend halfword +description: | + Sign-extends the least-significant halfword in the source to XLEN by copying the + most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. +definedBy: + extension: + name: Zbb +assembly: xd, xs1 +encoding: + match: 011000000101-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (xlen() == 32) { + X[xd] = {{16{X[xs1][15]}}, X[xs1][15:0]}; + } else if (xlen() == 64) { + X[xd] = {{48{X[xs1][15]}}, X[xs1][15:0]}; + } + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]) + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbb/zext.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbb/zext.h.yaml new file mode 100644 index 000000000000..8d6d194feb8e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbb/zext.h.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: zext.h +long_name: Zero-extend halfword +description: | + Zero-extends the least-significant halfword of the source to XLEN by inserting + 0's into all of the bits more significant than 15. + + [NOTE] + The *zext.h* instruction is a pseudo-op for `pack` when `Zbkb` is implemented and XLEN == 32. + + [NOTE] + The *zext.h* instruction is a pseudo-op for `packw` when `Zbkb` is implemented and XLEN == 64. +definedBy: + # When The Bit-manipulation for Cryptography extension (Zbkb) is implemented, then zext.h is an alias of pack. + extension: + allOf: + - name: Zbb + - not: + name: Zbkb +encoding: + RV32: + match: 000010000000-----100-----0110011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + RV64: + match: 000010000000-----100-----0111011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +assembly: xd, xs1 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[xd] = X[xs1][15:0]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]) + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbc/clmulr.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbc/clmulr.yaml new file mode 100644 index 000000000000..4812293431a6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbc/clmulr.yaml @@ -0,0 +1,61 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: clmulr +long_name: Carry-less multiply (reversed) +description: | + `clmulr` produces bits 2*XLEN-2:XLEN-1 of the 2*XLEN carry-less product +definedBy: + extension: + name: Zbc +assembly: xd, xs1, xs2 +access: + s: always + u: always + vs: always + vu: always +encoding: + match: 0000101----------010-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg xs1_val = X[xs1]; + XReg xs2_val = X[xs2]; + XReg output = 0; + + for (U32 i=0; i < xlen(); i++) { + output = (((xs2_val >> i) & 1) == 1) + ? output ^ (xs1_val >> (xlen() - i - 1)) + : output; + } + + X[xd] = output; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + result : xlenbits = zeros(); + foreach (i from 0 to (xlen_val - 1)) + if rs2_val[i] == bitone then result = result ^ (rs1_val >> (xlen_val - i - 1)); + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbkb/brev8.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbkb/brev8.yaml new file mode 100644 index 000000000000..2334adae41b1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbkb/brev8.yaml @@ -0,0 +1,51 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: brev8 +long_name: Reverse bits in bytes +description: | + Reverses the order of the bits in every byte of a register. +definedBy: + extension: + name: Zbkb +assembly: xd, xs1 +encoding: + match: 011010000111-----101-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg input = X[xs1]; + XReg output = 0; + + for(U32 i=0; i<(xlen()-8); i = i+8) { + for(U32 j=0; j<8; j = j+1) { + output[(i*8)+(7-j)] = input[(i*8)+j]; + } + } + + X[xd] = output; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + result : xlenbits = EXTZ(0b0); + foreach (i from 0 to sizeof(xlen) by 8) { + result[i+7..i] = reverse_bits_in_byte(X(rs1)[i+7..i]); + }; + X(rd) = result; + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbkb/pack.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbkb/pack.yaml new file mode 100644 index 000000000000..483738945af6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbkb/pack.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: pack +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zbkb +assembly: xd, xs1, xs2 +encoding: + match: 0000100----------100-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: (rs2 == 0) && (xlen() == 32) + to: zext.h xd, xs1 +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbkb/packh.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbkb/packh.yaml new file mode 100644 index 000000000000..ef4e783fbfac --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbkb/packh.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: packh +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zbkb +assembly: xd, xs1, xs2 +encoding: + match: 0000100----------111-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbkb/packw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbkb/packw.yaml new file mode 100644 index 000000000000..77ab49e68c8b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbkb/packw.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: packw +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zbkb +assembly: xd, xs1, xs2 +encoding: + match: 0000100----------100-----0111011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +pseudoinstructions: + - when: (rs2 == 0x0) + to: zext.h +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbkb/unzip.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbkb/unzip.yaml new file mode 100644 index 000000000000..458d4d6ffff5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbkb/unzip.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: unzip +long_name: Bit deinterleave +description: | + Gathers bits from the high and low halves of the source word into odd/even bit + positions in the destination word. It is the inverse of the zip instruction. This instruction is + available only on RV32. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zbkb +assembly: xd, xs1 +encoding: + match: 000010001111-----101-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg input = X[xs1]; + XReg output = 0; + + for(U32 i=0; i<(xlen()/2-1); i = i+1) { + output[i] = input[2*i]; + output[i+xlen()/2] = input[2*i+1]; + } + + X[xd] = output; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + foreach (i from 0 to xlen/2-1) { + X(rd)[i] = X(rs1)[2*i]; + X(rd)[i+xlen/2] = X(rs1)[2*i+1]; + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbkb/zip.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbkb/zip.yaml new file mode 100644 index 000000000000..a3bb853efd75 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbkb/zip.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: zip +long_name: Bit interleave +description: | + Scatters all of the odd and even bits of a source word into the high and low halves + of a destination word. It is the inverse of the unzip instruction. This instruction is available only on + RV32. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zbkb +assembly: xd, xs1 +encoding: + match: 000010001111-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg input = X[xs1]; + XReg output = 0; + + for(U32 i=0; i<(xlen()/2-1); i = i+1){ + output[2*i] = input[i]; + output[2*i+1] = input[i+xlen()/2]; + } + + X[xd] = output; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + foreach (i from 0 to xlen/2-1) { + X(rd)[2*i] = X(rs1)[i]; + X(rd)[2*i+1] = X(rs1)[i+xlen/2]; + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbkx/xperm4.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbkx/xperm4.yaml new file mode 100644 index 000000000000..5012c0c098d8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbkx/xperm4.yaml @@ -0,0 +1,64 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: xperm4 +long_name: Crossbar permutation (nibbles) +description: | + The xperm4 instruction operates on nibbles. The xs1 register contains a vector of XLEN/4 4-bit + elements. The xs2 register contains a vector of XLEN/4 4-bit indexes. The result is each element in + xs2 replaced by the indexed element in xs1, or zero if the index into xs2 is out of bounds. +definedBy: + extension: + name: Zbkx +assembly: xd, xs1, xs2 +encoding: + match: 0010100----------010-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg input1 = X[xs1]; + XReg input2 = X[xs2]; + XReg output = 0; + + for(U32 i=0; i<(xlen()-4); i = i+4) { + XReg index = input2[i+3:i]; + if(4*index < xlen()) { + output[i+3:i] = input1[4*index+3:4*index]; + } + } + + X[xd] = output; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + val xperm4_lookup : (bits(4), xlenbits) -> bits(4) + function xperm4_lookup (idx, lut) = { + (lut >> (idx @ 0b00))[3..0] + } + function clause execute ( XPERM_4 (rs2,rs1,rd)) = { + result : xlenbits = EXTZ(0b0); + foreach(i from 0 to xlen by 4) { + result[i+3..i] = xperm4_lookup(X(rs2)[i+3..i], X(rs1)); + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbkx/xperm8.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbkx/xperm8.yaml new file mode 100644 index 000000000000..9387e53ea117 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbkx/xperm8.yaml @@ -0,0 +1,64 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: xperm8 +long_name: Crossbar permutation (bytes) +description: | + The xperm8 instruction operates on bytes. The xs1 register contains a vector of XLEN/8 8-bit + elements. The xs2 register contains a vector of XLEN/8 8-bit indexes. The result is each element in + xs2 replaced by the indexed element in xs1, or zero if the index into xs2 is out of bounds. +definedBy: + extension: + name: Zbkx +assembly: xd, xs1, xs2 +encoding: + match: 0010100----------100-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg input1 = X[xs1]; + XReg input2 = X[xs2]; + XReg output = 0; + + for(U32 i=0; i<(xlen()-8); i = i+8) { + XReg index = input2[i+7:i]; + if(8*index < xlen()) { + output[i+7:i] = input1[8*index+7:8*index]; + } + } + + X[xd] = output; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + val xperm8_lookup : (bits(8), xlenbits) -> bits(8) + function xperm8_lookup (idx, lut) = { + (lut >> (idx @ 0b00))[7..0] + } + function clause execute ( XPERM_8 (rs2,rs1,rd)) = { + result : xlenbits = EXTZ(0b0); + foreach(i from 0 to xlen by 8) { + result[i+7..i] = xperm8_lookup(X(rs2)[i+7..i], X(rs1)); + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbs/bclr.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbs/bclr.yaml new file mode 100644 index 000000000000..2be8cb3edc1b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbs/bclr.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: bclr +long_name: Single-Bit clear (Register) +description: | + Returns xs1 with a single bit cleared at the index specified in xs2. + The index is read from the lower log2(XLEN) bits of xs2. +definedBy: + extension: + name: Zbs +assembly: xd, xs1, xs2 +encoding: + match: 0100100----------001-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg index = X[xs2] & (xlen() - 1); + X[xd] = X[xs1] & ~(1 << index); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let mask : xlenbits = if sizeof(xlen) == 32 + then zero_extend(0b1) << rs2_val[4..0] + else zero_extend(0b1) << rs2_val[5..0]; + let result : xlenbits = match op { + RISCV_BCLR => rs1_val & ~(mask), + RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), + RISCV_BINV => rs1_val ^ mask, + RISCV_BSET => rs1_val | mask + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbs/bclri.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbs/bclri.yaml new file mode 100644 index 000000000000..577a89c89a7f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbs/bclri.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: bclri +long_name: Single-Bit clear (Immediate) +description: | + Returns xs1 with a single bit cleared at the index specified in shamt. The + index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings corresponding + to shamt[5]=1 are reserved. +definedBy: + extension: + name: Zbs +assembly: xd, xs1, shamt +encoding: + RV32: + match: 0100100----------001-----0010011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + RV64: + match: 010010-----------001-----0010011 + variables: + - name: shamt + location: 25-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg index = shamt & (xlen() - 1); + X[xd] = X[xs1] & ~(1 << index); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let mask : xlenbits = if sizeof(xlen) == 32 + then zero_extend(0b1) << shamt[4..0] + else zero_extend(0b1) << shamt; + let result : xlenbits = match op { + RISCV_BCLRI => rs1_val & ~(mask), + RISCV_BEXTI => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), + RISCV_BINVI => rs1_val ^ mask, + RISCV_BSETI => rs1_val | mask + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbs/bext.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbs/bext.yaml new file mode 100644 index 000000000000..afc6681e5a69 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbs/bext.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: bext +long_name: Single-Bit extract (Register) +description: | + Returns a single bit extracted from xs1 at the index specified in xs2. + The index is read from the lower log2(XLEN) bits of xs2. +definedBy: + extension: + name: Zbs +assembly: xd, xs1, xs2 +encoding: + match: 0100100----------101-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg index = X[xs2] & (xlen() - 1); + X[xd] = (X[xs1] >> index) & 1; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let mask : xlenbits = if sizeof(xlen) == 32 + then zero_extend(0b1) << rs2_val[4..0] + else zero_extend(0b1) << rs2_val[5..0]; + let result : xlenbits = match op { + RISCV_BCLR => rs1_val & ~(mask), + RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), + RISCV_BINV => rs1_val ^ mask, + RISCV_BSET => rs1_val | mask + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbs/bexti.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbs/bexti.yaml new file mode 100644 index 000000000000..af1c1e31d798 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbs/bexti.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: bexti +long_name: Single-Bit extract (Immediate) +description: | + Returns a single bit extracted from xs1 at the index specified in xs2. + The index is read from the lower log2(XLEN) bits of shamt. For RV32, the encodings + corresponding to shamt[5]=1 are reserved. +definedBy: + extension: + name: Zbs +assembly: xd, xs1, shamt +encoding: + RV32: + match: 0100100----------101-----0010011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + RV64: + match: 010010-----------101-----0010011 + variables: + - name: shamt + location: 25-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg index = shamt & (xlen() - 1); + X[xd] = (X[xs1] >> index) & 1; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let mask : xlenbits = if sizeof(xlen) == 32 + then zero_extend(0b1) << shamt[4..0] + else zero_extend(0b1) << shamt; + let result : xlenbits = match op { + RISCV_BCLRI => rs1_val & ~(mask), + RISCV_BEXTI => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), + RISCV_BINVI => rs1_val ^ mask, + RISCV_BSETI => rs1_val | mask + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbs/binv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbs/binv.yaml new file mode 100644 index 000000000000..6128059c207b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbs/binv.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: binv +long_name: Single-Bit invert (Register) +description: | + Returns xs1 with a single bit inverted at the index specified in xs2. + The index is read from the lower log2(XLEN) bits of xs2. +definedBy: + extension: + name: Zbs +assembly: xd, xs1, xs2 +encoding: + match: 0110100----------001-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg index = X[xs2] & (xlen() - 1); + X[xd] = X[xs1] ^ (1 << index); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let mask : xlenbits = if sizeof(xlen) == 32 + then zero_extend(0b1) << rs2_val[4..0] + else zero_extend(0b1) << rs2_val[5..0]; + let result : xlenbits = match op { + RISCV_BCLR => rs1_val & ~(mask), + RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), + RISCV_BINV => rs1_val ^ mask, + RISCV_BSET => rs1_val | mask + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbs/binvi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbs/binvi.yaml new file mode 100644 index 000000000000..54c359e31dfa --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbs/binvi.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: binvi +long_name: Single-Bit invert (Immediate) +description: | + Returns xs1 with a single bit inverted at the index specified in shamt. + The index is read from the lower log2(XLEN) bits of shamt. + For RV32, the encodings corresponding to shamt[5]=1 are reserved. +definedBy: + extension: + name: Zbs +assembly: xd, xs1, shamt +encoding: + RV32: + match: 0110100----------001-----0010011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + RV64: + match: 011010-----------001-----0010011 + variables: + - name: shamt + location: 25-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg index = shamt & (xlen() - 1); + X[xd] = X[xs1] ^ (1 << index); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let mask : xlenbits = if sizeof(xlen) == 32 + then zero_extend(0b1) << shamt[4..0] + else zero_extend(0b1) << shamt; + let result : xlenbits = match op { + RISCV_BCLRI => rs1_val & ~(mask), + RISCV_BEXTI => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), + RISCV_BINVI => rs1_val ^ mask, + RISCV_BSETI => rs1_val | mask + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbs/bset.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbs/bset.yaml new file mode 100644 index 000000000000..975051860193 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbs/bset.yaml @@ -0,0 +1,59 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: bset +long_name: Single-Bit set (Register) +description: | + Returns xs1 with a single bit set at the index specified in xs2. + The index is read from the lower log2(XLEN) bits of xs2. +definedBy: + extension: + name: Zbs +assembly: xd, xs1, xs2 +encoding: + match: 0010100----------001-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg index = X[xs2] & (xlen() - 1); + X[xd] = X[xs1] | (1 << index); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let rs2_val = X(rs2); + let mask : xlenbits = if sizeof(xlen) == 32 + then zero_extend(0b1) << rs2_val[4..0] + else zero_extend(0b1) << rs2_val[5..0]; + let result : xlenbits = match op { + RISCV_BCLR => rs1_val & ~(mask), + RISCV_BEXT => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), + RISCV_BINV => rs1_val ^ mask, + RISCV_BSET => rs1_val | mask + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zbs/bseti.yaml b/pkg/ifuzz/riscv64/gen/inst/Zbs/bseti.yaml new file mode 100644 index 000000000000..2938773e3ad5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zbs/bseti.yaml @@ -0,0 +1,69 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: bseti +long_name: Single-Bit set (Immediate) +description: | + Returns xs1 with a single bit set at the index specified in shamt. + The index is read from the lower log2(XLEN) bits of shamt. + For RV32, the encodings corresponding to shamt[5]=1 are reserved. +definedBy: + extension: + name: Zbs +assembly: xd, xs1, shamt +encoding: + RV32: + match: 0010100----------001-----0010011 + variables: + - name: shamt + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 + RV64: + match: 001010-----------001-----0010011 + variables: + - name: shamt + location: 25-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg index = shamt & (xlen() - 1); + X[xd] = X[xs1] | (1 << index); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rs1); + let mask : xlenbits = if sizeof(xlen) == 32 + then zero_extend(0b1) << shamt[4..0] + else zero_extend(0b1) << shamt; + let result : xlenbits = match op { + RISCV_BCLRI => rs1_val & ~(mask), + RISCV_BEXTI => zero_extend(bool_to_bits((rs1_val & mask) != zeros())), + RISCV_BINVI => rs1_val ^ mask, + RISCV_BSETI => rs1_val | mask + }; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.lbu.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.lbu.yaml new file mode 100644 index 000000000000..41cda696427d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.lbu.yaml @@ -0,0 +1,72 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.lbu +long_name: Load unsigned byte, 16-bit encoding +description: | + Loads a 8-bit value from memory into register xd. + It computes an effective address by adding the zero-extended offset, to the base address in register xs1. + It expands to `lbu` `xd, offset(xs1)`. +definedBy: + extension: + name: Zcb +assembly: xd, imm(xs1) +encoding: + match: 100000--------00 + variables: + - name: imm + location: 5|6 + - name: xd + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + X[creg2reg(xd)] = read_memory<8>(virtual_address, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = zero_extend(imm); + /* Get the address, X(rs1c) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1c, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.lh.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.lh.yaml new file mode 100644 index 000000000000..4ce7c74b68c4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.lh.yaml @@ -0,0 +1,73 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.lh +long_name: Load signed halfword, 16-bit encoding +description: | + Loads a 16-bit value from memory into register xd. + It computes an effective address by adding the zero-extended offset, to the base address in register xs1. + It expands to `lh` `xd, offset(xs1)`. +definedBy: + extension: + name: Zcb +assembly: xd, imm(xs1) +encoding: + match: 100001---1----00 + variables: + - name: imm + location: 5 + left_shift: 1 + - name: xd + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + X[creg2reg(xd)] = sext(read_memory<16>(virtual_address, $encoding), 16); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = zero_extend(imm); + /* Get the address, X(rs1c) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1c, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.lhu.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.lhu.yaml new file mode 100644 index 000000000000..ca67b9910ca1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.lhu.yaml @@ -0,0 +1,73 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.lhu +long_name: Load unsigned halfword, 16-bit encoding +description: | + Loads a 16-bit value from memory into register xd. + It computes an effective address by adding the zero-extended offset, to the base address in register xs1. + It expands to `lhu` `xd, offset(xs1)`. +definedBy: + extension: + name: Zcb +assembly: xd, imm(xs1) +encoding: + match: 100001---0----00 + variables: + - name: imm + location: 5 + left_shift: 1 + - name: xd + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + X[creg2reg(xd)] = read_memory<16>(virtual_address, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = zero_extend(imm); + /* Get the address, X(rs1c) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1c, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(paddr, _) => + match (width) { + BYTE => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 1, aq, rl, false), is_unsigned), + HALF => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 2, aq, rl, false), is_unsigned), + WORD => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 4, aq, rl, false), is_unsigned), + DOUBLE if sizeof(xlen) >= 64 => + process_load(rdc, vaddr, mem_read(Read(Data), paddr, 8, aq, rl, false), is_unsigned), + _ => report_invalid_width(__FILE__, __LINE__, width, "load") + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.mul.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.mul.yaml new file mode 100644 index 000000000000..ad021bf07f4e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.mul.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.mul +long_name: Multiply, 16-bit encoding +description: | + Multiplies XLEN bits of the source operands from rsd' and xs2' and writes the lowest XLEN bits of the result to rsd'. + +definedBy: + extension: + allOf: + - name: Zcb + - name: Zmmul +assembly: xd, xs2 +encoding: + match: 100111---10---01 + variables: + - name: xd + location: 9-7 + - name: xs2 + location: 4-2 +access: + s: always + u: always + vs: always + vu: always +operation(): |2 + + if (implemented?(ExtensionName::M) && (CSR[misa].M == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[creg2reg(xd)] = X[creg2reg(xd)] * X[creg2reg(xs2)]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let result_wide = to_bits(2 * sizeof(xlen), signed(X(rsdc)) * signed(X(rs2c))); + X(rsdc) = result_wide[(sizeof(xlen) - 1) .. 0]; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.not.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.not.yaml new file mode 100644 index 000000000000..3ff577484dc8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.not.yaml @@ -0,0 +1,45 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.not +long_name: Bitwise not, 16-bit encoding +description: | + Takes a single source/destination operand. + This instruction takes the one's complement of xd'/xs1' and writes the result to the same register. + +definedBy: + extension: + name: Zcb +assembly: xd +encoding: + match: 100111---1110101 + variables: + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[creg2reg(xd)] = ~X[creg2reg(xd)]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + X(rsdc) = X(rsdc) XOR -1; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sb.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sb.yaml new file mode 100644 index 000000000000..87b5027ef682 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sb.yaml @@ -0,0 +1,39 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sb +long_name: Store unsigned byte, 16-bit encoding +description: | + Stores a 8-bit value from register xs2 into memory. + It computes an effective address by adding the zero-extended offset, to the base address in register xs1. + It expands to `sb` `xs2, offset(xs1)`. +definedBy: + extension: + name: Zcb +assembly: xs2, imm(xs1) +encoding: + match: 100010--------00 + variables: + - name: imm + location: 5|6 + - name: xs2 + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + write_memory<8>(virtual_address, X[creg2reg(xs2)][7:0], $encoding); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sext.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sext.b.yaml new file mode 100644 index 000000000000..61a6ceda4578 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sext.b.yaml @@ -0,0 +1,60 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sext.b +long_name: Sign-extend byte, 16-bit encoding +description: | + Takes a single source/destination operand. + This instruction sign-extends the least-significant byte of the source to XLEN by copying + the most-significant bit in the byte (i.e., bit 7) to all of the more-significant bits. + +definedBy: + extension: + allOf: + - name: Zcb + - name: Zbb +assembly: xd +encoding: + match: 100111---1100101 + variables: + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): |2 + + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[creg2reg(xd)] = $signed(X[creg2reg(xd)][7:0]); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rsdc); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTB => zero_extend(rs1_val[7..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]), + RISCV_ZEXTW => zero_extend(rs1_val[31..0]) + }; + X(rsdc) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sext.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sext.h.yaml new file mode 100644 index 000000000000..e7ce6414df7f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sext.h.yaml @@ -0,0 +1,60 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sext.h +long_name: Sign-extend halfword, 16-bit encoding +description: | + Takes a single source/destination operand. + This instruction sign-extends the least-significant halfword of the source to XLEN by copying + the most-significant bit in the halfword (i.e., bit 15) to all of the more-significant bits. + +definedBy: + extension: + allOf: + - name: Zcb + - name: Zbb +assembly: xd +encoding: + match: 100111---1101101 + variables: + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): |2 + + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[creg2reg(xd)] = $signed(X[creg2reg(xd)][15:0]); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rsdc); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTB => zero_extend(rs1_val[7..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]), + RISCV_ZEXTW => zero_extend(rs1_val[31..0]) + }; + X(rsdc) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sh.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sh.yaml new file mode 100644 index 000000000000..13d0d5704a9a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.sh.yaml @@ -0,0 +1,40 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.sh +long_name: Store unsigned halfword, 16-bit encoding +description: | + Stores a 16-bit value from register xs2 into memory. + It computes an effective address by adding the zero-extended offset, to the base address in register xs1. + It expands to `sh` `xs2, offset(xs1)`. +definedBy: + extension: + name: Zcb +assembly: xs2, imm(xs1) +encoding: + match: 100011---0----00 + variables: + - name: imm + location: 5 + left_shift: 1 + - name: xs2 + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + write_memory<16>(virtual_address, X[creg2reg(xs2)][15:0], $encoding); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.zext.b.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.zext.b.yaml new file mode 100644 index 000000000000..9291aead5146 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.zext.b.yaml @@ -0,0 +1,60 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.zext.b +long_name: Zero-extend byte, 16-bit encoding +description: | + Takes a single source/destination operand. + This instruction zero-extends the least-significant byte of the source to XLEN by inserting + 0's into all of the bits more significant than 7. + +definedBy: + extension: + allOf: + - name: Zcb + - name: Zbb +assembly: xd +encoding: + match: 100111---1100001 + variables: + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): |2 + + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[creg2reg(xd)] = X[creg2reg(xd)][7:0]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rsdc); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTB => zero_extend(rs1_val[7..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]), + RISCV_ZEXTW => zero_extend(rs1_val[31..0]) + }; + X(rsdc) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.zext.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.zext.h.yaml new file mode 100644 index 000000000000..7af7d7500b28 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.zext.h.yaml @@ -0,0 +1,60 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.zext.h +long_name: Zero-extend halfword, 16-bit encoding +description: | + Takes a single source/destination operand. + This instruction zero-extends the least-significant halfword of the source to XLEN by inserting + 0's into all of the bits more significant than 15. + +definedBy: + extension: + allOf: + - name: Zcb + - name: Zbb +assembly: xd +encoding: + match: 100111---1101001 + variables: + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): |2 + + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[creg2reg(xd)] = X[creg2reg(xd)][15:0]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rsdc); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTB => zero_extend(rs1_val[7..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]), + RISCV_ZEXTW => zero_extend(rs1_val[31..0]) + }; + X(rsdc) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcb/c.zext.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.zext.w.yaml new file mode 100644 index 000000000000..95d4f6f10626 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcb/c.zext.w.yaml @@ -0,0 +1,61 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.zext.w +long_name: Zero-extend word, 16-bit encoding +description: | + Takes a single source/destination operand. + It zero-extends the least-significant word of the operand to XLEN bits by inserting zeros into all of the bits more significant than 31. + +definedBy: + allOf: + - xlen: 64 + - extension: + allOf: + - name: Zcb + - name: Zbb +assembly: xd +encoding: + match: 100111---1110001 + variables: + - name: xd + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): |2 + + if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + X[creg2reg(xd)] = X[creg2reg(xd)][31:0]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val = X(rsdc); + let result : xlenbits = match op { + RISCV_SEXTB => sign_extend(rs1_val[7..0]), + RISCV_SEXTH => sign_extend(rs1_val[15..0]), + RISCV_ZEXTB => zero_extend(rs1_val[7..0]), + RISCV_ZEXTH => zero_extend(rs1_val[15..0]), + RISCV_ZEXTW => zero_extend(rs1_val[31..0]) + }; + X(rsdc) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fld.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fld.yaml new file mode 100644 index 000000000000..fbbb4f437cb9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fld.yaml @@ -0,0 +1,41 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.fld +long_name: Load double-precision +description: | + Loads a double precision floating-point value from memory into register fd. + It computes an effective address by adding the zero-extended offset, scaled by 8, + to the base address in register xs1. + It expands to `fld` `fd, offset(xs1)`. +definedBy: + extension: + name: Zcd +assembly: fd, imm(xs1) +encoding: + match: 001-----------00 + variables: + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: fd + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + f[fd] = sext(read_memory<64>(virtual_address, $encoding), 64); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fldsp.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fldsp.yaml new file mode 100644 index 000000000000..9f140bc9bee3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fldsp.yaml @@ -0,0 +1,42 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.fldsp +long_name: Load doubleword into floating-point register from stack +description: | + Loads a double-precision floating-point value from memory into floating-point register fd. + It computes its effective address by adding the zero-extended offset, scaled by 8, + to the stack pointer, x2. + It expands to `fld` `fd, offset(x2)`. +definedBy: + extension: + name: Zcd +assembly: fd, imm(sp) +encoding: + match: 001-----------10 + variables: + - name: imm + location: 4-2|12|6-5 + left_shift: 3 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + if (implemented?(ExtensionName::D) && (CSR[misa].D == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[2] + imm; + + f[fd] = read_memory<64>(virtual_address, $encoding); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fsd.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fsd.yaml new file mode 100644 index 000000000000..39ea3177ea25 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fsd.yaml @@ -0,0 +1,41 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.fsd +long_name: Store double-precision +description: | + Stores a double precision floating-point value in register fs2 to memory. + It computes an effective address by adding the zero-extended offset, scaled by 8, + to the base address in register xs1. + It expands to `fsd` `fs2, offset(xs1)`. +definedBy: + extension: + name: Zcd +assembly: fs2, imm(xs1) +encoding: + match: 101-----------00 + variables: + - name: imm + location: 6-5|12-10 + left_shift: 3 + - name: fs2 + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + write_memory<64>(virtual_address, X[creg2reg(fs2)], $encoding); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fsdsp.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fsdsp.yaml new file mode 100644 index 000000000000..66607975bc51 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcd/c.fsdsp.yaml @@ -0,0 +1,42 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.fsdsp +long_name: Store double-precision value to stack +description: | + Stores a double-precision floating-point value in floating-point register fs2 to memory. + It computes an effective address by adding the zero-extended offset, scaled by 8, + to the stack pointer, x2. + It expands to `fsd` `fs2, offset(x2)`. +definedBy: + extension: + name: Zcd +assembly: fs2, imm(sp) +encoding: + match: 101-----------10 + variables: + - name: imm + location: 9-7|12-10 + left_shift: 3 + - name: fs2 + location: 6-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + if (implemented?(ExtensionName::D) && (CSR[misa].D == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[2] + imm; + + write_memory<64>(virtual_address, f[fs2][63:0], $encoding); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcf/c.flw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcf/c.flw.yaml new file mode 100644 index 000000000000..59aeea765333 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcf/c.flw.yaml @@ -0,0 +1,41 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.flw +long_name: Load single-precision +description: | + Loads a single precision floating-point value from memory into register fd. + It computes an effective address by adding the zero-extended offset, scaled by 4, + to the base address in register xs1. + It expands to `flw` `fd, offset(xs1)`. +definedBy: + extension: + name: Zcf +assembly: fd, imm(xs1) +encoding: + match: 011-----------00 + variables: + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: fd + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + X[creg2reg(fd)] = sext(read_memory<32>(virtual_address, $encoding), 32); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcf/c.flwsp.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcf/c.flwsp.yaml new file mode 100644 index 000000000000..087b65f57229 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcf/c.flwsp.yaml @@ -0,0 +1,42 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.flwsp +long_name: Load word into floating-point register from stack +description: | + Loads a single-precision floating-point value from memory into floating-point register fd. + It computes its effective address by adding the zero-extended offset, scaled by 4, + to the stack pointer, x2. + It expands to `flw` `fd, offset(x2)`. +definedBy: + extension: + name: Zcf +assembly: fd, imm(sp) +encoding: + match: 011-----------10 + variables: + - name: imm + location: 3-2|12|6-4 + left_shift: 2 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + if (implemented?(ExtensionName::F) && (CSR[misa].F == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[2] + imm; + + f[fd] = read_memory<32>(virtual_address, $encoding); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcf/c.fsw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcf/c.fsw.yaml new file mode 100644 index 000000000000..2c761295c2f6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcf/c.fsw.yaml @@ -0,0 +1,41 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.fsw +long_name: Store single-precision +description: | + Stores a single precision floating-point value in register fs2 to memory. + It computes an effective address by adding the zero-extended offset, scaled by 4, + to the base address in register xs1. + It expands to `fsw` `fs2, offset(xs1)`. +definedBy: + extension: + name: Zcf +assembly: fs2, imm(xs1) +encoding: + match: 111-----------00 + variables: + - name: imm + location: 5|12-10|6 + left_shift: 2 + - name: fs2 + location: 4-2 + - name: xs1 + location: 9-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[creg2reg(xs1)] + imm; + + write_memory<32>(virtual_address, X[creg2reg(fs2)][31:0], $encoding); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcf/c.fswsp.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcf/c.fswsp.yaml new file mode 100644 index 000000000000..fb25d4623145 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcf/c.fswsp.yaml @@ -0,0 +1,42 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: c.fswsp +long_name: Store single-precision value to stack +description: | + Stores a single-precision floating-point value in floating-point register fs2 to memory. + It computes an effective address by adding the zero-extended offset, scaled by 4, + to the stack pointer, x2. + It expands to `fsw` `fs2, offset(x2)`. +definedBy: + extension: + name: Zcf +assembly: fs2, imm(sp) +encoding: + match: 111-----------10 + variables: + - name: imm + location: 8-7|12-9 + left_shift: 2 + - name: fs2 + location: 6-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::C) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + if (implemented?(ExtensionName::F) && (CSR[misa].F == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg virtual_address = X[2] + imm; + + write_memory<32>(virtual_address, f[fs2][31:0], $encoding); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcmop/c.mop.n.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcmop/c.mop.n.yaml new file mode 100644 index 000000000000..e677e130b8ed --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcmop/c.mop.n.yaml @@ -0,0 +1,47 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: c.mop.n +long_name: Compressed May-Be-Operation +description: + C.MOP.n is encoded in the reserved encoding space corresponding to C.LUI + xn, 0. Unlike the MOPs defined in the Zimop extension, the C.MOP.n instructions + are defined to not write any register. Their encoding allows future extensions to + define them to read register x[n]. +definedBy: + extension: + name: Zcmop +assembly: "" +encoding: + match: 01100---10000001 + variables: + - name: n + location: 10-8 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +pseudoinstructions: + - when: (n == 0) + to: c.mop.1 + - when: (n == 1) + to: c.mop.3 + - when: (n == 2) + to: c.mop.5 + - when: (n == 3) + to: c.mop.7 + - when: (n == 4) + to: c.mop.9 + - when: (n == 5) + to: c.mop.11 + - when: (n == 6) + to: c.mop.13 + - when: (n == 7) + to: c.mop.15 +operation(): "" #do nothing diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.mva01s.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.mva01s.yaml new file mode 100644 index 000000000000..afccef45f521 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.mva01s.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cm.mva01s +long_name: Move two s0-s7 registers into a0-a1 +description: | + Moves r1s' into a0 and r2s' into a1. The execution is atomic, so it is not possible to observe state where only one of a0 or a1 have been updated. + The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space. The mapping between them is specified in the pseudo-code below. +definedBy: + extension: + name: Zcmp +assembly: r1s, r2s +encoding: + match: 101011---11---10 + variables: + - name: r1s + location: 9-7 + - name: r2s + location: 4-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + XReg xreg1 = (r1s[2:1]>0) ? {1,0,r1s[2:0]} : {0,1,r1s[2:0]}; + XReg xreg2 = (r2s[2:1]>0) ? {1,0,r2s[2:0]} : {0,1,r2s[2:0]}; + X[10] = X[xreg1]; + X[11] = X[xreg2]; diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.mvsa01.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.mvsa01.yaml new file mode 100644 index 000000000000..14af57b1f3b5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.mvsa01.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cm.mvsa01 +long_name: Move a0-a1 into two registers of s0-s7 +description: | + Moves a0 into r1s' and a1 into r2s'. r1s' and r2s' must be different. + The execution is atomic, so it is not possible to observe state where only one of r1s' or r2s' has been updated. + The encoding uses sreg number specifiers instead of xreg number specifiers to save encoding space. + The mapping between them is specified in the pseudo-code below. +definedBy: + extension: + name: Zcmp +assembly: r1s, r2s +encoding: + match: 101011---01---10 + variables: + - name: r1s + location: 9-7 + - name: r2s + location: 4-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + XReg xreg1 = (r1s[2:1]>0) ? {1,0,r1s[2:0]} : {0,1,r1s[2:0]}; + XReg xreg2 = (r2s[2:1]>0) ? {1,0,r2s[2:0]} : {0,1,r2s[2:0]}; + X[xreg1] = X[10]; + X[xreg2] = X[11]; diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.pop.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.pop.yaml new file mode 100644 index 000000000000..99deb9dbb3df --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.pop.yaml @@ -0,0 +1,86 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cm.pop +long_name: Destroy function call stack frame +description: | + Destroys a stack frame: load `ra` and 0 to 12 saved registers from the stack frame, deallocate the stack frame. + This instruction pops (loads) the registers in `reg_list` from stack memory, and then adjusts the stack pointer by `stack_adj`. + + Restrictions on stack_adj: + + * it must be enough to store all of the listed registers + * it must be a multiple of 16 (bytes): + ** for RV32 the allowed values are: 16, 32, 48, 64, 80, 96, 112 + ** for RV64 the allowed values are: 16, 32, 48, 64, 80, 96, 112, 128, 144, 160 +definedBy: + extension: + name: Zcmp +assembly: reg_list, stack_adj +encoding: + match: 10111010------10 + variables: + - name: rlist + location: 7-4 + not: [0, 1, 2, 3] + - name: spimm + location: 3-2 + left_shift: 4 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg size = xlen() / 8; + XReg nreg = (rlist == 15) ? 13 : (rlist - 3); + XReg stack_aligned_adj = (nreg * 4 + 15) & ~0xF; + XReg virtual_address_sp = X[2]; + XReg virtual_address_new_sp = virtual_address_sp + stack_aligned_adj + spimm; + XReg virtual_address_base = virtual_address_new_sp - (nreg * size); + + X[ 1] = read_memory_xlen_aligned(virtual_address_base + 0*size, $encoding); + if (nreg > 1) { + X[ 8] = read_memory_xlen_aligned(virtual_address_base + 1*size, $encoding); + } + if (nreg > 2) { + X[ 9] = read_memory_xlen_aligned(virtual_address_base + 2*size, $encoding); + } + if (nreg > 3) { + X[18] = read_memory_xlen_aligned(virtual_address_base + 3*size, $encoding); + } + if (nreg > 4) { + X[19] = read_memory_xlen_aligned(virtual_address_base + 4*size, $encoding); + } + if (nreg > 5) { + X[20] = read_memory_xlen_aligned(virtual_address_base + 5*size, $encoding); + } + if (nreg > 6) { + X[21] = read_memory_xlen_aligned(virtual_address_base + 6*size, $encoding); + } + if (nreg > 7) { + X[22] = read_memory_xlen_aligned(virtual_address_base + 7*size, $encoding); + } + if (nreg > 8) { + X[23] = read_memory_xlen_aligned(virtual_address_base + 8*size, $encoding); + } + if (nreg > 9) { + X[24] = read_memory_xlen_aligned(virtual_address_base + 9*size, $encoding); + } + if (nreg > 10) { + X[25] = read_memory_xlen_aligned(virtual_address_base + 10*size, $encoding); + } + if (nreg > 11) { + X[26] = read_memory_xlen_aligned(virtual_address_base + 11*size, $encoding); + X[27] = read_memory_xlen_aligned(virtual_address_base + 12*size, $encoding); + } + + X[2] = virtual_address_new_sp; diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.popret.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.popret.yaml new file mode 100644 index 000000000000..a589661a0949 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.popret.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cm.popret +long_name: Destroy function call stack frame and return to `ra` +description: | + Destroys a stack frame: load `ra` and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to `ra`. + This instruction pops (loads) the registers in `reg_list` from stack memory, and then adjusts the stack pointer by `stack_adj` and then return to `ra`. + + Restrictions on stack_adj: + + * it must be enough to store all of the listed registers + * it must be a multiple of 16 (bytes): + ** for RV32 the allowed values are: 16, 32, 48, 64, 80, 96, 112 + ** for RV64 the allowed values are: 16, 32, 48, 64, 80, 96, 112, 128, 144, 160 +definedBy: + extension: + name: Zcmp +assembly: reg_list, stack_adj +encoding: + match: 10111110------10 + variables: + - name: rlist + location: 7-4 + not: [0, 1, 2, 3] + - name: spimm + location: 3-2 + left_shift: 4 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg size = xlen() / 8; + XReg nreg = (rlist == 15) ? 13 : (rlist - 3); + XReg stack_aligned_adj = (nreg * 4 + 15) & ~0xF; + XReg virtual_address_sp = X[2]; + XReg virtual_address_new_sp = virtual_address_sp + stack_aligned_adj + spimm; + XReg virtual_address_base = virtual_address_new_sp - (nreg * size); + + X[ 1] = read_memory_xlen_aligned(virtual_address_base + 0*size, $encoding); + if (nreg > 1) { + X[ 8] = read_memory_xlen_aligned(virtual_address_base + 1*size, $encoding); + } + if (nreg > 2) { + X[ 9] = read_memory_xlen_aligned(virtual_address_base + 2*size, $encoding); + } + if (nreg > 3) { + X[18] = read_memory_xlen_aligned(virtual_address_base + 3*size, $encoding); + } + if (nreg > 4) { + X[19] = read_memory_xlen_aligned(virtual_address_base + 4*size, $encoding); + } + if (nreg > 5) { + X[20] = read_memory_xlen_aligned(virtual_address_base + 5*size, $encoding); + } + if (nreg > 6) { + X[21] = read_memory_xlen_aligned(virtual_address_base + 6*size, $encoding); + } + if (nreg > 7) { + X[22] = read_memory_xlen_aligned(virtual_address_base + 7*size, $encoding); + } + if (nreg > 8) { + X[23] = read_memory_xlen_aligned(virtual_address_base + 8*size, $encoding); + } + if (nreg > 9) { + X[24] = read_memory_xlen_aligned(virtual_address_base + 9*size, $encoding); + } + if (nreg > 10) { + X[25] = read_memory_xlen_aligned(virtual_address_base + 10*size, $encoding); + } + if (nreg > 11) { + X[26] = read_memory_xlen_aligned(virtual_address_base + 11*size, $encoding); + X[27] = read_memory_xlen_aligned(virtual_address_base + 12*size, $encoding); + } + + X[2] = virtual_address_new_sp; + jump(X[1]); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.popretz.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.popretz.yaml new file mode 100644 index 000000000000..62cd8930a43c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.popretz.yaml @@ -0,0 +1,88 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cm.popretz +long_name: Destroy function call stack frame, move zero to `a0` and return to `ra` +description: | + Destroys a stack frame: load `ra` and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero to `a0`, return to `ra`. + This instruction pops (loads) the registers in `reg_list` from stack memory, and then adjusts the stack pointer by `stack_adj`, move zero to `a0` and then return to `ra`. + + Restrictions on stack_adj: + + * it must be enough to store all of the listed registers + * it must be a multiple of 16 (bytes): + ** for RV32 the allowed values are: 16, 32, 48, 64, 80, 96, 112 + ** for RV64 the allowed values are: 16, 32, 48, 64, 80, 96, 112, 128, 144, 160 +definedBy: + extension: + name: Zcmp +assembly: reg_list, stack_adj +encoding: + match: 10111100------10 + variables: + - name: rlist + location: 7-4 + not: [0, 1, 2, 3] + - name: spimm + location: 3-2 + left_shift: 4 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg size = xlen() / 8; + XReg nreg = (rlist == 15) ? 13 : (rlist - 3); + XReg stack_aligned_adj = (nreg * 4 + 15) & ~0xF; + XReg virtual_address_sp = X[2]; + XReg virtual_address_new_sp = virtual_address_sp + stack_aligned_adj + spimm; + XReg virtual_address_base = virtual_address_new_sp - (nreg * size); + + X[ 1] = read_memory_xlen_aligned(virtual_address_base + 0*size, $encoding); + if (nreg > 1) { + X[ 8] = read_memory_xlen_aligned(virtual_address_base + 1*size, $encoding); + } + if (nreg > 2) { + X[ 9] = read_memory_xlen_aligned(virtual_address_base + 2*size, $encoding); + } + if (nreg > 3) { + X[18] = read_memory_xlen_aligned(virtual_address_base + 3*size, $encoding); + } + if (nreg > 4) { + X[19] = read_memory_xlen_aligned(virtual_address_base + 4*size, $encoding); + } + if (nreg > 5) { + X[20] = read_memory_xlen_aligned(virtual_address_base + 5*size, $encoding); + } + if (nreg > 6) { + X[21] = read_memory_xlen_aligned(virtual_address_base + 6*size, $encoding); + } + if (nreg > 7) { + X[22] = read_memory_xlen_aligned(virtual_address_base + 7*size, $encoding); + } + if (nreg > 8) { + X[23] = read_memory_xlen_aligned(virtual_address_base + 8*size, $encoding); + } + if (nreg > 9) { + X[24] = read_memory_xlen_aligned(virtual_address_base + 9*size, $encoding); + } + if (nreg > 10) { + X[25] = read_memory_xlen_aligned(virtual_address_base + 10*size, $encoding); + } + if (nreg > 11) { + X[26] = read_memory_xlen_aligned(virtual_address_base + 11*size, $encoding); + X[27] = read_memory_xlen_aligned(virtual_address_base + 12*size, $encoding); + } + + X[2] = virtual_address_new_sp; + X[10] = 0; + jump(X[1]); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.push.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.push.yaml new file mode 100644 index 000000000000..ba199de7b86b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcmp/cm.push.yaml @@ -0,0 +1,87 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cm.push +long_name: Create function call stack frame +description: | + Creates a stack frame: store `ra` and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space. + This instruction pushes (stores) the registers in `reg_list` to the memory below the stack pointer, + and then creates the stack frame by decrementing the stack pointer by `stack_adj`. + + Restrictions on stack_adj: + + * it must be enough to store all of the listed registers + * it must be a multiple of 16 (bytes): + ** for RV32 the allowed values are: 16, 32, 48, 64, 80, 96, 112 + ** for RV64 the allowed values are: 16, 32, 48, 64, 80, 96, 112, 128, 144, 160 +definedBy: + extension: + name: Zcmp +assembly: reg_list, -stack_adj +encoding: + match: 10111000------10 + variables: + - name: rlist + location: 7-4 + not: [0, 1, 2, 3] + - name: spimm + location: 3-2 + left_shift: 4 +access: + s: always + u: always + vs: always + vu: always +operation(): | + if (implemented?(ExtensionName::Zcmp) && (CSR[misa].C == 1'b0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg size = xlen() / 8; + XReg nreg = (rlist == 15) ? 13 : (rlist - 3); + XReg stack_aligned_adj = (nreg * 4 + 15) & ~0xF; + XReg virtual_address_sp = X[2]; + XReg virtual_address_new_sp = virtual_address_sp - stack_aligned_adj - spimm; + XReg virtual_address_base = virtual_address_sp - (nreg * size); + + write_memory_xlen_aligned(virtual_address_base + 0*size, X[ 1], $encoding); + if (nreg > 1) { + write_memory_xlen_aligned(virtual_address_base + 1*size, X[ 8], $encoding); + } + if (nreg > 2) { + write_memory_xlen_aligned(virtual_address_base + 2*size, X[ 9], $encoding); + } + if (nreg > 3) { + write_memory_xlen_aligned(virtual_address_base + 3*size, X[18], $encoding); + } + if (nreg > 4) { + write_memory_xlen_aligned(virtual_address_base + 4*size, X[19], $encoding); + } + if (nreg > 5) { + write_memory_xlen_aligned(virtual_address_base + 5*size, X[20], $encoding); + } + if (nreg > 6) { + write_memory_xlen_aligned(virtual_address_base + 6*size, X[21], $encoding); + } + if (nreg > 7) { + write_memory_xlen_aligned(virtual_address_base + 7*size, X[22], $encoding); + } + if (nreg > 8) { + write_memory_xlen_aligned(virtual_address_base + 8*size, X[23], $encoding); + } + if (nreg > 9) { + write_memory_xlen_aligned(virtual_address_base + 9*size, X[24], $encoding); + } + if (nreg > 10) { + write_memory_xlen_aligned(virtual_address_base + 10*size, X[25], $encoding); + } + if (nreg > 11) { + write_memory_xlen_aligned(virtual_address_base + 11*size, X[26], $encoding); + write_memory_xlen_aligned(virtual_address_base + 12*size, X[27], $encoding); + } + + X[2] = virtual_address_new_sp; diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcmt/cm.jalt.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcmt/cm.jalt.yaml new file mode 100644 index 000000000000..a8fd64eeb937 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcmt/cm.jalt.yaml @@ -0,0 +1,65 @@ +# Copyright (c) Ventana Micro Systems +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cm.jalt +long_name: Jump Via Table with Optional Link +description: | + Read an address from the Jump Vector Table and jump to it, linking to `ra`. +definedBy: + extension: + name: Zcmt +assembly: index +encoding: + match: 101000--------10 + variables: + - name: index + location: 9-2 + # prettier-ignore + not: [ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ] +access: + s: always + u: always + vs: always + vu: always +operation(): | + # Ensure JVT readable + check_zcmt_enabled($encoding); + + if (CSR[jvt].MODE != 0) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + # Skip over _this_ 16-bit instruction + XReg return_addr = $pc + 2; + X[1] = return_addr; + + XReg jump_table_base = { CSR[jvt].BASE, 6'b000000 }; + XReg virtual_address = jump_table_base + index `* (xlen() / 8); + XReg addr; + TranslationResult result; + + # TODO: Correct this check when we figure out what MISA can do + if (CSR[misa].S == 1) { + result = translate(virtual_address, MemoryOperation::Fetch, mode(), $encoding); + } else { + result.paddr = virtual_address; + } + + # may raise an exception + access_check(result.paddr, xlen(), $pc, MemoryOperation::Fetch, ExceptionCode::InstructionAccessFault, mode()); + + if (xlen() == 32) { + addr = read_physical_memory<32>(result.paddr); + } else { + addr = read_physical_memory<64>(result.paddr); + } # Ensure low-order bit is clear + + addr = addr & $signed(2'b10); + + jump(addr); + +sail(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zcmt/cm.jt.yaml b/pkg/ifuzz/riscv64/gen/inst/Zcmt/cm.jt.yaml new file mode 100644 index 000000000000..ed807914f672 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zcmt/cm.jt.yaml @@ -0,0 +1,60 @@ +# Copyright (c) Ventana Micro Systems +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cm.jt +long_name: Jump Via Table +description: | + Read an address from the Jump Vector Table and jump to it. +definedBy: + extension: + name: Zcmt +assembly: index +encoding: + match: 101000000-----10 + variables: + - name: index + location: 6-2 +access: + s: always + u: always + vs: always + vu: always +operation(): | + # Ensure JVT readable + check_zcmt_enabled($encoding); + + if (CSR[jvt].MODE != 0) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg jump_table_base = { CSR[jvt].BASE, 6'b000000 }; + XReg virtual_address = jump_table_base + index `* (xlen() / 8); + XReg addr; + TranslationResult result; + + # TODO: Correct this check when we figure out what MISA can do + if (CSR[misa].S == 1) { + result = translate(virtual_address, MemoryOperation::Fetch, mode(), $encoding); + } else { + result.paddr = virtual_address; + } + + # may raise an exception + access_check(result.paddr, xlen(), $pc, MemoryOperation::Fetch, ExceptionCode::InstructionAccessFault, mode()); + + if (xlen() == 32) { + addr = read_physical_memory<32>(result.paddr); + } else { + addr = read_physical_memory<64>(result.paddr); + } + + # Ensure low-order bit is clear + addr = addr & $signed(2'b10); + + jump(addr); + +sail(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfa/fli.s.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfa/fli.s.yaml new file mode 100644 index 000000000000..c6045e5af7a8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfa/fli.s.yaml @@ -0,0 +1,74 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fli.s +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zfa +assembly: fd, xs1 +encoding: + match: 111100000001-----000-----1010011 + variables: + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let bits : bits(32) = match constantidx { + 0b00000 => { 0xbf800000 }, /* -1.0 */ + 0b00001 => { 0x00800000 }, /* minimum positive normal */ + 0b00010 => { 0x37800000 }, /* 1.0 * 2^-16 */ + 0b00011 => { 0x38000000 }, /* 1.0 * 2^-15 */ + 0b00100 => { 0x3b800000 }, /* 1.0 * 2^-8 */ + 0b00101 => { 0x3c000000 }, /* 1.0 * 2^-7 */ + 0b00110 => { 0x3d800000 }, /* 1.0 * 2^-4 */ + 0b00111 => { 0x3e000000 }, /* 1.0 * 2^-3 */ + 0b01000 => { 0x3e800000 }, /* 0.25 */ + 0b01001 => { 0x3ea00000 }, /* 0.3125 */ + 0b01010 => { 0x3ec00000 }, /* 0.375 */ + 0b01011 => { 0x3ee00000 }, /* 0.4375 */ + 0b01100 => { 0x3f000000 }, /* 0.5 */ + 0b01101 => { 0x3f200000 }, /* 0.625 */ + 0b01110 => { 0x3f400000 }, /* 0.75 */ + 0b01111 => { 0x3f600000 }, /* 0.875 */ + 0b10000 => { 0x3f800000 }, /* 1.0 */ + 0b10001 => { 0x3fa00000 }, /* 1.25 */ + 0b10010 => { 0x3fc00000 }, /* 1.5 */ + 0b10011 => { 0x3fe00000 }, /* 1.75 */ + 0b10100 => { 0x40000000 }, /* 2.0 */ + 0b10101 => { 0x40200000 }, /* 2.5 */ + 0b10110 => { 0x40400000 }, /* 3 */ + 0b10111 => { 0x40800000 }, /* 4 */ + 0b11000 => { 0x41000000 }, /* 8 */ + 0b11001 => { 0x41800000 }, /* 16 */ + 0b11010 => { 0x43000000 }, /* 2^7 */ + 0b11011 => { 0x43800000 }, /* 2^8 */ + 0b11100 => { 0x47000000 }, /* 2^15 */ + 0b11101 => { 0x47800000 }, /* 2^16 */ + 0b11110 => { 0x7f800000 }, /* +inf */ + 0b11111 => { canonical_NaN_S() }, + }; + F_S(rd) = bits; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfa/fmaxm.s.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfa/fmaxm.s.yaml new file mode 100644 index 000000000000..c58b1301101d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfa/fmaxm.s.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmaxm.s +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zfa +assembly: fd, fs1, fs2 +encoding: + match: 0010100----------011-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_S(rs1); + let rs2_val_S = F_S(rs2); + + let is_quiet = true; + let (rs2_lt_rs1, fflags) = fle_S (rs2_val_S, rs1_val_S, is_quiet); + + let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S() + else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs2_val_S + else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs1_val_S + else if rs2_lt_rs1 then rs1_val_S + else /* (not rs2_lt_rs1) */ rs2_val_S; + + accrue_fflags(fflags); + F_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfa/fminm.s.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfa/fminm.s.yaml new file mode 100644 index 000000000000..e2f9ded94cd4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfa/fminm.s.yaml @@ -0,0 +1,55 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fminm.s +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zfa +assembly: fd, fs1, fs2 +encoding: + match: 0010100----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_S(rs1); + let rs2_val_S = F_S(rs2); + + let is_quiet = true; + let (rs1_lt_rs2, fflags) = fle_S (rs1_val_S, rs2_val_S, is_quiet); + + let rd_val_S = if (f_is_NaN_S(rs1_val_S) | f_is_NaN_S(rs2_val_S)) then canonical_NaN_S() + else if (f_is_neg_zero_S(rs1_val_S) & f_is_pos_zero_S(rs2_val_S)) then rs1_val_S + else if (f_is_neg_zero_S(rs2_val_S) & f_is_pos_zero_S(rs1_val_S)) then rs2_val_S + else if rs1_lt_rs2 then rs1_val_S + else /* (not rs1_lt_rs2) */ rs2_val_S; + + accrue_fflags(fflags); + F_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfa/fround.s.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfa/fround.s.yaml new file mode 100644 index 000000000000..a71f5755d741 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfa/fround.s.yaml @@ -0,0 +1,63 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fround.s +long_name: Floating-point round single-precision float to integer +description: | + Rounds the single-precision floating-point number in floating-point register _fs1_ to an integer, according to the rounding mode specified in the instruction’s _rm_ field. + + It then writes that integer, represented as a single-precision floating-point number, to floating-point register _fd_. + + Zero and infinite inputs are copied to _fd_ unmodified. + + Signaling NaN inputs cause the invalid operation exception flag to be set; no other exception flags are set. FROUND.S is encoded like FCVT.S.D, but with rs2=4. +definedBy: + extension: + name: Zfa +assembly: fd, fs1, rm +encoding: + match: 010000000100-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + check_f_ok($encoding); + RoundingMode rounding_mode = rm_to_mode(rm, $encoding); + f[fd] = round_f32_to_integral(f[fs1], rounding_mode); + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_S(rs1); + + match (select_instr_or_fcsr_rm(rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, false); + + accrue_fflags(fflags); + F_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfa/froundnx.s.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfa/froundnx.s.yaml new file mode 100644 index 000000000000..bba1ac031853 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfa/froundnx.s.yaml @@ -0,0 +1,53 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: froundnx.s +long_name: Floating-point Round Single-precision to Integer with Inexact +description: | + No description available. +definedBy: + extension: + name: Zfa +assembly: fd, fs1, rm +encoding: + match: 010000000101-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_S = F_S(rs1); + + match (select_instr_or_fcsr_rm(rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_S) = riscv_f32roundToInt(rm_3b, rs1_val_S, true); + + accrue_fflags(fflags); + F_S(rd) = rd_val_S; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfbfmin/fcvt.bf16.s.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfbfmin/fcvt.bf16.s.yaml new file mode 100644 index 000000000000..67288037704b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfbfmin/fcvt.bf16.s.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.bf16.s +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zfbfmin +assembly: fd, fs1, rm +encoding: + match: 010001001000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfbfmin/fcvt.s.bf16.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfbfmin/fcvt.s.bf16.yaml new file mode 100644 index 000000000000..34c4cb8d8a6c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfbfmin/fcvt.s.bf16.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.s.bf16 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zfbfmin +assembly: fd, fs1, rm +encoding: + match: 010000000110-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fadd.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fadd.h.yaml new file mode 100644 index 000000000000..57ecb1dabf74 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fadd.h.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fadd.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + anyOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2, rm +encoding: + match: 0000010------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fclass.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fclass.h.yaml new file mode 100644 index 000000000000..27ec0314dcb6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fclass.h.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fclass.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: xd, fs1 +encoding: + match: 111001000000-----001-----1010011 + variables: + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.d.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.d.h.yaml new file mode 100644 index 000000000000..eefa3ab3a4c3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.d.h.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.d.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - allOf: + - name: D + - name: Zfhmin + - allOf: + - name: Zdinx + - name: Zhinxmin +assembly: fd, fs1, rm +encoding: + match: 010000100010-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.d.yaml new file mode 100644 index 000000000000..a09ea3f35550 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.d.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.h.d +long_name: Floating-point Convert Double-precision to Half-precision +description: | + `fcvt.h.d` converts a Double-precision Floating-point number to a Half-precision floating-point number. +definedBy: + extension: + oneOf: + - allOf: + - name: D + - name: Zfhmin + - allOf: + - name: Zdinx + - name: Zhinxmin +assembly: fd, fs1, rm +encoding: + match: 010001000001-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.l.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.l.yaml new file mode 100644 index 000000000000..a095593a2be4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.l.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.h.l +long_name: Floating-point Convert Long to Half-precision +definedBy: + allOf: + - xlen: 64 + - extension: + oneOf: + - name: Zfh + - name: Zhinx +description: | + `fcvt.h.l` converts a 64-bit signed integer to a half-precision floating-point number. +assembly: fd, xs1, rm +encoding: + match: 110101000010-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.lu.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.lu.yaml new file mode 100644 index 000000000000..3d2552f11bb8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.lu.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.h.lu +long_name: Floating-point Convert Unsigned Long to Half-precision +definedBy: + allOf: + - xlen: 64 + - extension: + oneOf: + - name: Zfh + - name: Zhinx +description: | + `fcvt.h.lu` converts a 64-bit unsigned integer to a half-precision floating-point number. +assembly: fd, xs1, rm +encoding: + match: 110101000011-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.s.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.s.yaml new file mode 100644 index 000000000000..50fe7f45ba03 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.s.yaml @@ -0,0 +1,94 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.h.s +long_name: Convert half-precision float to a single-precision float +definedBy: + extension: + oneOf: + - name: Zfhmin + - name: Zhinxmin +assembly: fd, fs1, rm +description: | + Converts a half-precision number in floating-point register _fs1_ into a single-precision floating-point number in + floating-point register _fd_. + + `fcvt.h.s` rounds according to the _rm_ field. + + All floating-point conversion instructions set the Inexact exception flag if the rounded + result differs from the operand value and the Invalid exception flag is not set. + +encoding: + match: 010001000000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + check_f_ok($encoding); + + Bits<16> hp_value = f[fs1][15:0]; + + Bits<1> sign = hp_value[15]; + Bits<5> exp = hp_value[14:10]; + Bits<10> frac = hp_value[9:0]; + + if (exp == 0x1F) { + if (frac != 0) { + if ((hp_value & 0x0200) != 0) { + set_fp_flag(FpFlag::NV); + } + f[fd] = HP_CANONICAL_NAN; + } else { + f[fd] = packToF32UI(sign, 0xFF, 0); + } + } else { + if (exp != 0) { + if (frac != 0) { + f[fd] = packToF32UI(sign, 0, 0); + } else { + Bits<6> norm_exp; + (norm_exp, frac) = softfloat_normSubnormalF16Sig( frac ); + exp = norm_exp - 1; + f[fd] = packToF32UI(sign, exp + 0x70, frac << 13); + } + } else { + f[fd] = packToF32UI(sign, exp + 0x70, frac << 13); + } + } + + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_H) = riscv_ui64ToF16 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_H(rd) = rd_val_H; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.w.yaml new file mode 100644 index 000000000000..0d95f6dac7c1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.w.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.h.w +long_name: Floating-point Convert Word to Half-precision +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +description: | + `fcvt.h.w` converts a 32-bit signed integer to a half-precision floating-point number. +assembly: fd, xs1, rm +encoding: + match: 110101000000-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.wu.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.wu.yaml new file mode 100644 index 000000000000..1f363682b9b1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.h.wu.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.h.wu +long_name: Floating-point Convert Unsigned Word to Half-precision +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +description: | + `fcvt.h.wu` converts a 32-bit unsigned integer to a half-precision floating-point number. +assembly: fd, xs1, rm +encoding: + match: 110101000001-------------1010011 + variables: + - name: xs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.l.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.l.h.yaml new file mode 100644 index 000000000000..edfb8353b673 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.l.h.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.l.h +long_name: Floating-point Convert Half-precision to Long +definedBy: + allOf: + - xlen: 64 + - extension: + oneOf: + - name: Zfh + - name: Zhinx +description: | + `fcvt.l.h` converts a half-precision floating-point number to a signed 64-bit integer. +assembly: xd, fs1, rm +encoding: + match: 110001000010-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.lu.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.lu.h.yaml new file mode 100644 index 000000000000..cfe60cf85156 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.lu.h.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.lu.h +long_name: Floating-point Convert Half-precision to Unsigned Long +definedBy: + allOf: + - xlen: 64 + - extension: + oneOf: + - name: Zfh + - name: Zhinx +description: | + `fcvt.lu.h` converts a half-precision floating-point number to an unsigned 64-bit integer. +assembly: xd, fs1, rm +encoding: + match: 110001000011-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.s.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.s.h.yaml new file mode 100644 index 000000000000..735ed7afe60d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.s.h.yaml @@ -0,0 +1,91 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fcvt.s.h +long_name: Convert single-precision float to a half-precision float +definedBy: + extension: + oneOf: + - name: Zfhmin + - name: Zhinxmin +assembly: fd, fs1, rm +description: | + Converts a single-precision number in floating-point register _fs1_ into a half-precision floating-point number in + floating-point register _fd_. + + `fcvt.s.h` will never round, and so the 'rm' field is effectively ignored. + +encoding: + match: 010000000010-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + check_f_ok($encoding); + + Bits<32> sp_value = f[fs1][31:0]; + + Bits<1> sign = sp_value[31]; + Bits<8> exp = sp_value[30:23]; + Bits<23> frac = sp_value[22:0]; + + if (exp == 0xFF) { + if (frac != 0) { + if ((sp_value & 0x00400000) != 0) { + set_fp_flag(FpFlag::NV); + } + f[fd] = nan_box<16, FLEN>(HP_CANONICAL_NAN); + } else { + f[fd] = nan_box<16, FLEN>(packToF16UI( sign, 0x1F, 0 )); + } + } else { + + # frac is a 24-bit significand, the bottom 9 bits LSB are extracted and OR-red + # into a sticky flag, the top 15 MSBs are extracted, the LSB of this top slice + # is OR-red with the sticky + Bits<16> frac16 = (frac >> 9) | ((frac & 0x1ff) != 0 ? 1 : 0); + if ((exp | frac16) == 0) { + f[fd] = nan_box<16, FLEN>(packToF16UI( sign, 0, 0 )); + } else { + assert(false, "TODO: implement roundPackToF16"); + # f[fd] = soffloat_roundPackToF16(sign, exp - 0x71, frac16 | 0x4000); + } + + } + + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + assert(sizeof(xlen) >= 64); + let rs1_val_LU = X(rs1)[63..0]; + match (select_instr_or_fcsr_rm (rm)) { + None() => { handle_illegal(); RETIRE_FAIL }, + Some(rm') => { + let rm_3b = encdec_rounding_mode(rm'); + let (fflags, rd_val_H) = riscv_ui64ToF16 (rm_3b, rs1_val_LU); + + accrue_fflags(fflags); + F_or_X_H(rd) = rd_val_H; + RETIRE_SUCCESS + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.w.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.w.h.yaml new file mode 100644 index 000000000000..748ab0770365 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.w.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.w.h +long_name: Floating-point Convert Half-precision to Word +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +description: | + `fcvt.w.h` converts a half-precision floating-point number to a signed 32-bit integer. +assembly: xd, fs1, rm +encoding: + match: 110001000000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.wu.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.wu.h.yaml new file mode 100644 index 000000000000..1748cf936c6d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fcvt.wu.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fcvt.wu.h +long_name: Floating-point Convert Half-precision to Word +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +description: | + `fcvt.wu.h` converts a half-precision floating-point number to a signed 32-bit unsigned integer. +assembly: xd, fs1, rm +encoding: + match: 110001000001-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fdiv.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fdiv.h.yaml new file mode 100644 index 000000000000..9ab7cc983e59 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fdiv.h.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fdiv.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2, rm +encoding: + match: 0001110------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/feq.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/feq.h.yaml new file mode 100644 index 000000000000..2e09b6ff96f4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/feq.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: feq.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: xd, fs1, fs2 +encoding: + match: 1010010----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fle.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fle.h.yaml new file mode 100644 index 000000000000..5ef88b70553b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fle.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fle.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: xd, fs1, fs2 +encoding: + match: 1010010----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fleq.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fleq.h.yaml new file mode 100644 index 000000000000..2ad1caf14e61 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fleq.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fleq.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + allOf: + - name: Zfa + - name: Zfh +assembly: xd, fs1, fs2 +encoding: + match: 1010010----------100-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/flh.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/flh.yaml new file mode 100644 index 000000000000..3e581b61eda7 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/flh.yaml @@ -0,0 +1,78 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: flh +long_name: Half-precision floating-point load +description: | + The `flh` instruction loads a single-precision floating-point value from memory at address _xs1_ + _imm_ into floating-point register _xd_. + + `flh` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. + + `flh` is only guaranteed to execute atomically if the effective address is naturally aligned. + +definedBy: + extension: + name: Zfhmin +assembly: fd, imm(xs1) +encoding: + match: "-----------------001-----0000111" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + check_f_ok($encoding); + + XReg virtual_address = X[xs1] + $signed(imm); + + Bits<16> hp_value = read_memory<16>(virtual_address, $encoding); + + f[fd] = nan_box<16, FLEN>(hp_value); + + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Read(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Read(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let (aq, rl, res) = (false, false, false); + match (width) { + BYTE => { handle_illegal(); RETIRE_FAIL }, + HALF => + process_fload16(rd, vaddr, mem_read(Read(Data), addr, 2, aq, rl, res)), + WORD => + process_fload32(rd, vaddr, mem_read(Read(Data), addr, 4, aq, rl, res)), + DOUBLE if sizeof(flen) >= 64 => + process_fload64(rd, vaddr, mem_read(Read(Data), addr, 8, aq, rl, res)), + _ => report_invalid_width(__FILE__, __LINE__, width, "floating point load"), + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fli.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fli.h.yaml new file mode 100644 index 000000000000..3affd938ff86 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fli.h.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fli.h +long_name: Floating-point Load Immediate Half-precision +description: | + No description available. +definedBy: + extension: + allOf: + - name: Zfa + - name: Zfh +assembly: fd, xs1 +encoding: + match: 111101000001-----000-----1010011 + variables: + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/flt.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/flt.h.yaml new file mode 100644 index 000000000000..aa8da72d4299 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/flt.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: flt.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: xd, fs1, fs2 +encoding: + match: 1010010----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fltq.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fltq.h.yaml new file mode 100644 index 000000000000..03c4b7048ae8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fltq.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fltq.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + allOf: + - name: Zfa + - name: Zfh +assembly: xd, fs1, fs2 +encoding: + match: 1010010----------101-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fmadd.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmadd.h.yaml new file mode 100644 index 000000000000..39b4d5e0124f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmadd.h.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmadd.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----10------------------1000011" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fmax.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmax.h.yaml new file mode 100644 index 000000000000..a4b15e8a6ad6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmax.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmax.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2 +encoding: + match: 0010110----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fmaxm.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmaxm.h.yaml new file mode 100644 index 000000000000..fc05a19dccc5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmaxm.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmaxm.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + allOf: + - name: Zfa + - name: Zfh +assembly: fd, fs1, fs2 +encoding: + match: 0010110----------011-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fmin.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmin.h.yaml new file mode 100644 index 000000000000..3971eeaba5a0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmin.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmin.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2 +encoding: + match: 0010110----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fminm.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fminm.h.yaml new file mode 100644 index 000000000000..5d515e58153c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fminm.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fminm.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + allOf: + - name: Zfa + - name: Zfh +assembly: fd, fs1, fs2 +encoding: + match: 0010110----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fmsub.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmsub.h.yaml new file mode 100644 index 000000000000..2bcb2a7fcefd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmsub.h.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmsub.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----10------------------1000111" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fmul.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmul.h.yaml new file mode 100644 index 000000000000..8725c6f615bc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmul.h.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fmul.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2, rm +encoding: + match: 0001010------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fmv.h.x.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmv.h.x.yaml new file mode 100644 index 000000000000..f3fb1dabb5ad --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmv.h.x.yaml @@ -0,0 +1,51 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmv.h.x +long_name: Half-precision floating-point move from integer +description: | + Moves the half-precision value encoded in IEEE 754-2008 standard encoding + from the lower 16 bits of integer register `xs1` to the floating-point + register `fd`. The bits are not modified in the transfer, and in particular, + the payloads of non-canonical NaNs are preserved. +definedBy: + extension: + name: Zfhmin +assembly: fd, xs1 +encoding: + match: 111101000000-----000-----1010011 + variables: + - name: xs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + check_f_ok($encoding); + + Bits<16> hp_value = X[xs1][15:0]; + + f[fd] = nan_box<16, FLEN>(hp_value); + + mark_f_state_dirty(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_X = X(rs1); + let rd_val_H = rs1_val_X [15..0]; + F(rd) = nan_box (rd_val_H); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fmv.x.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmv.x.h.yaml new file mode 100644 index 000000000000..27d3bb9c3f20 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fmv.x.h.yaml @@ -0,0 +1,51 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fmv.x.h +long_name: Move half-precision value from floating-point to integer register +definedBy: + extension: + name: Zfhmin +assembly: xd, fs1 +description: | + Moves the half-precision value in floating-point register fs1 represented in IEEE 754-2008 + encoding to the lower 16 bits of integer register xd. + + The bits are not modified in the transfer, and in particular, the payloads of non-canonical + NaNs are preserved. + + The highest XLEN-16 bits of the destination register are filled with copies of the + floating-point number's sign bit. +encoding: + match: 111001000000-----000-----1010011 + variables: + - name: fs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + check_f_ok($encoding); + + X[xd] = sext(f[fs1][15:0], 16); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val_X = X(rs1); + let rd_val_H = rs1_val_X [15..0]; + F(rd) = nan_box (rd_val_H); + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fnmadd.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fnmadd.h.yaml new file mode 100644 index 000000000000..670cae8e48d6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fnmadd.h.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fnmadd.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----10------------------1001111" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fnmsub.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fnmsub.h.yaml new file mode 100644 index 000000000000..f09bd882987a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fnmsub.h.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fnmsub.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2, fs3, rm +encoding: + match: "-----10------------------1001011" + variables: + - name: fs3 + location: 31-27 + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fround.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fround.h.yaml new file mode 100644 index 000000000000..17e21c2aa0f3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fround.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fround.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + allOf: + - name: Zfa + - name: Zfh +assembly: fd, fs1, rm +encoding: + match: 010001000100-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/froundnx.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/froundnx.h.yaml new file mode 100644 index 000000000000..7d508664684f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/froundnx.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: froundnx.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + allOf: + - name: Zfa + - name: Zfh +assembly: fd, fs1, rm +encoding: + match: 010001000101-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fsgnj.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsgnj.h.yaml new file mode 100644 index 000000000000..2eee9568ab5b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsgnj.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsgnj.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2 +encoding: + match: 0010010----------000-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fsgnjn.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsgnjn.h.yaml new file mode 100644 index 000000000000..390967a3be2b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsgnjn.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsgnjn.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2 +encoding: + match: 0010010----------001-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fsgnjx.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsgnjx.h.yaml new file mode 100644 index 000000000000..cc0c459ebf2d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsgnjx.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsgnjx.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2 +encoding: + match: 0010010----------010-----1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fsh.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsh.yaml new file mode 100644 index 000000000000..f4aa9dab4778 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsh.yaml @@ -0,0 +1,89 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fsh +long_name: Half-precision floating-point store +description: | + The `fsh` instruction stores a half-precision floating-point value + from register _xd_ to memory at address _xs1_ + _imm_. + + `fsh` does not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved. + + `fsh` ignores all but the lower 16 bits in _fs2_. + + `fsh` is only guaranteed to execute atomically if the effective address is naturally aligned. + +definedBy: + extension: + name: Zfhmin +assembly: fs2, imm(xs1) +encoding: + match: "-----------------001-----0100111" + variables: + - name: imm + location: 31-25|11-7 + - name: xs1 + location: 19-15 + - name: fs2 + location: 24-20 +access: + s: always + u: always + vs: always + vu: always +operation(): | + check_f_ok($encoding); + + XReg virtual_address = X[xs1] + $signed(imm); + + Bits<16> hp_value = f[fs2][15:0]; + + write_memory<16>(virtual_address, hp_value, $encoding); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let offset : xlenbits = sign_extend(imm); + let (aq, rl, con) = (false, false, false); + /* Get the address, X(rs1) + offset. + Some extensions perform additional checks on address validity. */ + match ext_data_get_addr(rs1, offset, Write(Data), width) { + Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL }, + Ext_DataAddr_OK(vaddr) => + if check_misaligned(vaddr, width) + then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL } + else match translateAddr(vaddr, Write(Data)) { + TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + TR_Address(addr, _) => { + let eares : MemoryOpResult(unit) = match width { + BYTE => MemValue () /* bogus placeholder for illegal size */, + HALF => mem_write_ea(addr, 2, aq, rl, false), + WORD => mem_write_ea(addr, 4, aq, rl, false), + DOUBLE => mem_write_ea(addr, 8, aq, rl, false) + }; + match (eares) { + MemException(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }, + MemValue(_) => { + let rs2_val = F(rs2); + match (width) { + BYTE => { handle_illegal(); RETIRE_FAIL }, + HALF => process_fstore (vaddr, mem_write_value(addr, 2, rs2_val[15..0], aq, rl, con)), + WORD => process_fstore (vaddr, mem_write_value(addr, 4, rs2_val[31..0], aq, rl, con)), + DOUBLE if sizeof(flen) >= 64 => + process_fstore (vaddr, mem_write_value(addr, 8, rs2_val, aq, rl, con)), + _ => report_invalid_width(__FILE__, __LINE__, width, "floating point store"), + }; + } + } + } + } + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fsqrt.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsqrt.h.yaml new file mode 100644 index 000000000000..3e585c0b80ab --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsqrt.h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsqrt.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, rm +encoding: + match: 010111000000-------------1010011 + variables: + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zfh/fsub.h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsub.h.yaml new file mode 100644 index 000000000000..d3e159af0401 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zfh/fsub.h.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: fsub.h +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + oneOf: + - name: Zfh + - name: Zhinx +assembly: fd, fs1, fs2, rm +encoding: + match: 0000110------------------1010011 + variables: + - name: fs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: rm + location: 14-12 + - name: fd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicbom/cbo.clean.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicbom/cbo.clean.yaml new file mode 100644 index 000000000000..a7c2c36fc3e2 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicbom/cbo.clean.yaml @@ -0,0 +1,77 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cbo.clean +long_name: Cache Block Clean +description: | + Cleans an entire cache block globally throughout the system. + + Exactly what happens is coherence protocol-dependent, but in general it is expected that after this + operation(): + + * The cache block will be in the clean (not dirty) state in any coherent cache holding a valid copy of the line. + * The data will be cleaned to a point such that an incoherent load can observe the cleaned data. + + `cbo.clean` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`. + + <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> + Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.clean` has UNSPECIFIED behavior. + <%- end -%> + + Clean operations are treated as stores for page and access permissions. If permission checks fail, + one of the following exceptions will occur: + + <%- if ext?(:H) -%> + * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation. + <%- end -%> + * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %> + * `Store/AMO Access Fault` if a PMP or PMA access check fails + + <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> + Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP + and PMA access checks only need to check a single address in the line. + <%- end -%> + + CBO operations never raise a misaligned address fault. + +definedBy: + extension: + name: Zicbom +assembly: (xs1) +encoding: + match: 000000000001-----010000000001111 + variables: + - name: xs1 + location: 19-15 +access: + m: always + s: sometimes + u: sometimes + vs: sometimes + vu: sometimes +access_detail: | + Access is controlled through `menvcfg.CBZE`, `senvcfg.CBZE`, and `henvcfg.CBZE`. + When access is denied, the instruction either raises an `Illegal Instruction` + or `Virtual Instruction` exception according to the table below. + + [%autowidth,cols="1,1,1,1,1,1,1",separator="!"] + !=== + .2+h![.rotate]#`menvcfg.CBCFE`# .2+h! [.rotate]#`senvcfg.CBCFE`# .2+h! [.rotate]#`henvcfg.CBCFE`# + 4+^.>h! `cbo.clean` Instruction Behavior + .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode + + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes + !=== + +# operation(): | +# let cache_block_address = X[xs1] & ~(CACHE_BLOCK_SIZE-1); + +# CACHE_BLOCK_CLEAN(cache_block_address); diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicbom/cbo.flush.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicbom/cbo.flush.yaml new file mode 100644 index 000000000000..7d09f84aef84 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicbom/cbo.flush.yaml @@ -0,0 +1,75 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cbo.flush +long_name: Cache Block Flush +description: | + Flushes an entire cache block by cleaning it and then invalidating it in all caches. + + `cbo.flush` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`. + + <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> + Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.flush` has UNSPECIFIED behavior. + <%- end -%> + + Flush operations are treated as stores for page and access permissions. If permission checks fail, + one of the following exceptions will occur: + + <%- if ext?(:H) -%> + * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation. + <%- end -%> + * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %> + * `Store/AMO Access Fault` if a PMP or PMA access check fails. + + <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> + Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP + and PMA access checks only need to check a single address in the line. + <%- end -%> + + CBO operations never raise a misaligned address fault. +definedBy: + extension: + name: Zicbom +assembly: (xs1) +encoding: + match: 000000000010-----010000000001111 + variables: + - name: xs1 + location: 19-15 +access: + m: always + s: sometimes + u: sometimes + vs: sometimes + vu: sometimes +access_detail: | + Access is controlled through `menvcfg.CBZE`, `senvcfg.CBZE`, and `henvcfg.CBZE`. + When access is denied, the instruction either raises an `Illegal Instruction` + or `Virtual Instruction` exception according to the table below. + + [%autowidth,cols="1,1,1,1,1,1,1",separator="!"] + !=== + .2+h![.rotate]#`menvcfg.CBCFE`# .2+h! [.rotate]#`senvcfg.CBCFE`# .2+h! [.rotate]#`henvcfg.CBCFE`# + 4+^.>h! `cbo.flush` Instruction Behavior + .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode + + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes + !=== + +# operation(): | +# XReg cache_block_address = X[xs1] & ~(CACHE_BLOCK_SIZE-1); +# Boolean has_fault?; +# ExceptionCode code; + +# (has_fault?, code) = zero_cache_line(cache_block_address); +# if (has_fault?) { +# raise(code); +# } diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicbom/cbo.inval.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicbom/cbo.inval.yaml new file mode 100644 index 000000000000..62ba383a7e7e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicbom/cbo.inval.yaml @@ -0,0 +1,116 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: cbo.inval +long_name: Cache Block Invalidate +description: | + Either invalidates or flushes (clean + invalidate) a cache block, depending on the current mode and value of + `menvcfg.CBIE`, `senvcfg.CBIE`, and/or `henvcfg.CBIE`. + + The instruction is an invalidate (without a clean) when: + + * In M-mode + * In (H)S-mode and `menvcfg.CBIE` == 11 + * In U-mode and `menvcfg.CBIE` == 11 and `senvcfg.CBIE` == 11 + * In VS-mode and `menvcfg.CBIE` == 11 and `henvcfg.CBIE` == 11 + * In VU-mode and `menvcfg.CBIE` == 11 and `henvcfg.CBIE` == 11 and `senvcfg.CBIE` == 11 + + Otherwise, if the instruction does not trap (see Access section), the operation is a flush. + The table below summarizes the options. + + [%autowidth,cols="1,1,1,1,1,1,1,1",separator="!"] + !=== + .2+h![.rotate]#`menvcfg.CBIE`# .2+h! [.rotate]#`senvcfg.CBIE`# .2+h! [.rotate]#`henvcfg.CBIE`# + 5+^.>h! `cbe.inval` Operation + .^h! M-mode .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode + + ! 00 ! - ! - ! Invalidate ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` + ! 01 ! 00 ! 00 ! Invalidate ! Flush ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 01 ! 00 ! 01 ! Invalidate ! Flush ! `Illegal Instruction` ! Flush ! `Virtual Instruction` + ! 01 ! 00 ! 11 ! Invalidate ! Flush ! `Illegal Instruction` ! Flush ! `Virtual Instruction` + ! 01 ! 01 ! 00 ! Invalidate ! Flush ! Flush ! `Virtual Instruction` ! `Virtual Instruction` + ! 01 ! 01 ! 01 ! Invalidate ! Flush ! Flush ! Flush ! Flush + ! 01 ! 01 ! 11 ! Invalidate ! Flush ! Flush ! Flush ! Flush + ! 01 ! 11 ! 00 ! Invalidate ! Flush ! Flush ! `Virtual Instruction` ! `Virtual Instruction` + ! 01 ! 11 ! 01 ! Invalidate ! Flush ! Flush ! Flush ! Flush + ! 01 ! 11 ! 11 ! Invalidate ! Flush ! Flush ! Flush ! Flush + ! 11 ! 00 ! 00 ! Invalidate ! Invalidate ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 11 ! 00 ! 01 ! Invalidate ! Invalidate ! `Illegal Instruction` ! Flush ! `Virtual Instruction` + ! 11 ! 00 ! 11 ! Invalidate ! Invalidate ! `Illegal Instruction` ! Invalidate ! `Virtual Instruction` + ! 11 ! 01 ! 00 ! Invalidate ! Invalidate ! Flush ! `Virtual Instruction` ! `Virtual Instruction` + ! 11 ! 01 ! 01 ! Invalidate ! Invalidate ! Flush ! Flush ! Flush + ! 11 ! 01 ! 11 ! Invalidate ! Invalidate ! Flush ! Invalidate ! Flush + ! 11 ! 11 ! 00 ! Invalidate ! Invalidate ! Invalidate ! `Virtual Instruction` ! `Virtual Instruction` + ! 11 ! 11 ! 01 ! Invalidate ! Invalidate ! Invalidate ! Flush ! Flush + ! 11 ! 11 ! 11 ! Invalidate ! Invalidate ! Invalidate ! Invalidate ! Invalidate + !=== + + `cbo.inval` is ordered by `FENCE` instructions but not `FENCE.I` or `SFENCE.VMA`. + + <%- if CACHE_BLOCK_SIZE.bit_length > [PMP_GRANULARITY, PMA_GRANULARITY].min -%> + Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior. + <%- end -%> + + Invalidate operations are treated as stores for page and access permissions. If permission checks fail, + one of the following exceptions will occur: + + <%- if ext?(:H) -%> + * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation. + <%- end -%> + * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %> + * `Store/AMO Access Fault` if a PMP or PMA access check fails. + + <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> + Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP + and PMA access checks only need to check a single address in the line. + <%- end -%> + + CBO operations never raise a misaligned address fault. +definedBy: + extension: + name: Zicbom +assembly: (xs1) +encoding: + match: 000000000000-----010000000001111 + variables: + - name: xs1 + location: 19-15 +access: + m: always + s: sometimes + u: sometimes + vs: sometimes + vu: sometimes +access_detail: | + Access is controlled through `menvcfg.CBIE`, `senvcfg.CBIE`, and `henvcfg.CBIE`. + When access is denied, the instruction either raises an `Illegal Instruction` + or `Virtual Instruction` exception according to the table below. + + [NOTE] + `xenvcfg.CBIE` == 10 is reserved, and cannot be written by software. As such, that pattern is + excluded from the table below. + + [%autowidth,cols="1,1,1,1,1,1,1",separator="!"] + !=== + .2+h![.rotate]#`menvcfg.CBIE`# .2+h! [.rotate]#`senvcfg.CBIE`# .2+h! [.rotate]#`henvcfg.CBIE`# + 4+^.>h! `cbo.inval` Instruction Behavior + .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode + + ! 00 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` ! `Illegal Instruction` + ! 01/11 ! 00 ! 00 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 01/11 ! 01/11 ! 00 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 01/11 ! 00 ! 01/11 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 01/11 ! 01/11 ! 01/11 ! executes ! executes ! executes ! executes + !=== + +# operation(): | +# let cache_block_address = X[xs1] & ~(CACHE_BLOCK_SIZE-1); + +# // zeroing operation can occur in any number of independent stores +# for (i=0; i [PMP_GRANULARITY, PMA_GRANULARITY].min -%> + Both PMP and PMA access control must be the same for all bytes in the block; otherwise, `cbo.zero` has UNSPECIFIED behavior. + <%- end -%> + + Clean operations are treated as stores for page and access permissions. If permission checks fail, + one of the following exceptions will occur: + + <%- if ext?(:H) -%> + * `Store/AMO Guest-Page Fault` if virtual memory translation fails during G-stage translation. + <%- end -%> + * `Store/AMO Page Fault` if virtual memory translation fails <% if ext?(:H) %>when V=0 or during VS-stage translation<% end %> + * `Store/AMO Access Fault` if a PMP or PMA access check fails. + + <%- if CACHE_BLOCK_SIZE.bit_length <= [PMP_GRANULARITY, PMA_GRANULARITY].min -%> + Because cache blocks are naturally aligned and always fit in a single PMP or PMA regions, the PMP + and PMA access checks only need to check a single address in the line. + <%- end -%> + + CBO operations never raise a misaligned address fault. +definedBy: + extension: + name: Zicboz +assembly: (xs1) +encoding: + match: 000000000100-----010000000001111 + variables: + - name: xs1 + location: 19-15 +access: + m: always + s: sometimes + u: sometimes + vs: sometimes + vu: sometimes +access_detail: | + Access is controlled through `menvcfg.CBZE`, `senvcfg.CBZE`, and `henvcfg.CBZE`. + When access is denied, the instruction either raises an `Illegal Instruction` + or `Virtual Instruction` exception according to the table below. + + [%autowidth,cols="1,1,1,1,1,1,1",separator="!"] + !=== + .2+h![.rotate]#`menvcfg.CBZE`# .2+h! [.rotate]#`senvcfg.CBZE`# .2+h! [.rotate]#`henvcfg.CBZE`# + 4+^.>h! `cbo.zero` Instruction Behavior + .^h! S-mode .^h! U-mode .^h! VS-mode .^h! VU-mode + + ! 0 ! - ! - ! `Illegal Instruction` ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 0 ! executes ! `Illegal Instruction` ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 1 ! 0 ! executes ! executes ! `Virtual Instruction` ! `Virtual Instruction` + ! 1 ! 0 ! 1 ! executes ! `Illegal Instruction` ! executes ! `Virtual Instruction` + ! 1 ! 1 ! 1 ! executes ! executes ! executes ! executes + !=== +operation(): | + if ((mode() == PrivilegeMode::M && CSR[menvcfg].CBZE == 0) || + (mode() == PrivilegeMode::U && CSR[senvcfg].CBZE == 0)) { + raise(ExceptionCode::IllegalInstruction, mode(), $encoding); + } + else if ((mode() == PrivilegeMode::VS && CSR[henvcfg].CBZE ==0) || + (mode() == PrivilegeMode::VU && (CSR[henvcfg].CBZE | CSR[senvcfg].CBZE) == 0)) { + raise(ExceptionCode::VirtualInstruction, mode(), $encoding); + } else { + XReg mask = CACHE_BLOCK_SIZE - 1; + XReg cache_block_vaddr = X[xs1] & ~mask; + + TranslationResult result; + result = translate(cache_block_vaddr, MemoryOperation::Write, effective_ldst_mode(), $encoding); + access_check(result.paddr, CACHE_BLOCK_SIZE*8, cache_block_vaddr, MemoryOperation::Write, ExceptionCode::StoreAmoAccessFault, effective_ldst_mode()); + + cache_block_zero(result.paddr); + } diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicfilp/lpad.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicfilp/lpad.yaml new file mode 100644 index 000000000000..acf5d762f778 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicfilp/lpad.yaml @@ -0,0 +1,28 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: lpad +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zicfilp +assembly: imm +encoding: + match: "--------------------000000010111" + variables: + - name: imm + location: 31-12 + left_shift: 12 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicfiss/ssamoswap.d.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/ssamoswap.d.yaml new file mode 100644 index 000000000000..57e3c3aac683 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/ssamoswap.d.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: ssamoswap.d +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zicfiss +assembly: xd, xs2, xs1 +encoding: + match: 01001------------011-----0101111 + variables: + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicfiss/ssamoswap.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/ssamoswap.w.yaml new file mode 100644 index 000000000000..2fe8992d168d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/ssamoswap.w.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: ssamoswap.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zicfiss +assembly: xd, xs2, xs1 +encoding: + match: 01001------------010-----0101111 + variables: + - name: aq + location: 26-26 + - name: rl + location: 25-25 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspopchk.x1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspopchk.x1.yaml new file mode 100644 index 000000000000..6908993daf47 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspopchk.x1.yaml @@ -0,0 +1,25 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: sspopchk.x1 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zicfiss +assembly: sspopchk_x1 +encoding: + match: "11001101110000001100000001110011" + variables: [] +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspopchk.x5.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspopchk.x5.yaml new file mode 100644 index 000000000000..c9522174a982 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspopchk.x5.yaml @@ -0,0 +1,25 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: sspopchk.x5 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zicfiss +assembly: sspopchk_x5 +encoding: + match: "11001101110000101100000001110011" + variables: [] +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspush.x1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspush.x1.yaml new file mode 100644 index 000000000000..8dde7b7d8d87 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspush.x1.yaml @@ -0,0 +1,25 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: sspush.x1 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zicfiss +assembly: sspush_x1 +encoding: + match: "11001110000100000100000001110011" + variables: [] +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspush.x5.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspush.x5.yaml new file mode 100644 index 000000000000..586fbf664229 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/sspush.x5.yaml @@ -0,0 +1,25 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: sspush.x5 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zicfiss +assembly: sspush_x5 +encoding: + match: "11001110010100000100000001110011" + variables: [] +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicfiss/ssrdp.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/ssrdp.yaml new file mode 100644 index 000000000000..ae000b3b35e9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicfiss/ssrdp.yaml @@ -0,0 +1,28 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: ssrdp +long_name: Read ssp into a Register +description: | + No description available. +definedBy: + extension: + name: Zicfiss +assembly: xd +encoding: + match: 11001101110000000100-----1110011 + variables: + - name: xd + location: 11-7 + not: 0 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicond/czero.eqz.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicond/czero.eqz.yaml new file mode 100644 index 000000000000..b6bdf042fccc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicond/czero.eqz.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: czero.eqz +long_name: Conditional zero, if condition is equal to zero +description: | + If xs2 contains the value zero, this instruction writes the value zero to xd. Otherwise, this instruction + copies the contents of xs1 to xd. + This instruction carries a syntactic dependency from both xs1 and xs2 to xd. Furthermore, if the Zkt + extension is implemented, this instruction's timing is independent of the data values in xs1 and xs2. +definedBy: + extension: + name: Zicond +assembly: xd, xs1, xs2 +encoding: + match: 0000111----------101-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + X[xd] = (X[xs2] == 0) ? 0 : X[xs1]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let value = X(rs1); + let condition = X(rs2); + let result : xlenbits = if (condition == zeros()) then zeros() + else value; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicond/czero.nez.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicond/czero.nez.yaml new file mode 100644 index 000000000000..995f57eed657 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicond/czero.nez.yaml @@ -0,0 +1,50 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: czero.nez +long_name: Conditional zero, if condition is nonzero +description: | + If xs2 contains a nonzero value, this instruction writes the value zero to xd. Otherwise, this + instruction copies the contents of xs1 to xd. + This instruction carries a syntactic dependency from both xs1 and xs2 to xd. Furthermore, if the Zkt + extension is implemented, this instruction's timing is independent of the data values in xs1 and xs2. +definedBy: + extension: + name: Zicond +assembly: xd, xs1, xs2 +encoding: + match: 0000111----------111-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + X[xd] = (X[xs2] != 0) ? 0 : X[xs1]; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let value = X(rs1); + let condition = X(rs2); + let result : xlenbits = if (condition != zeros()) then zeros() + else value; + X(rd) = result; + RETIRE_SUCCESS + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrc.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrc.yaml new file mode 100644 index 000000000000..7ae6ad32f1f4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrc.yaml @@ -0,0 +1,68 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: csrrc +long_name: Atomic Read and Clear Bits in CSR +description: | + The CSRRC (Atomic Read and Clear Bits in CSR) instruction reads the value of the CSR, zero-extends + the value to XLEN bits, and writes it to integer register `xd`. The initial value in integer register `xs1` is + treated as a bit mask that specifies bit positions to be cleared in the CSR. Any bit that is high in `xs1` will + cause the corresponding bit to be cleared in the CSR, if that CSR bit is writable. + + For CSRRC, if `xs1=x0`, then the instruction will not write to the CSR at all, and so shall + not cause any of the side effects that might otherwise occur on a CSR write, nor raise illegal- + instruction exceptions on accesses to read-only CSRs. CSRRC always reads the addressed CSR and + cause any read side effects regardless of `xs1` and `xd` fields. + Note that if `xs1` specifies a register other than `x0`, and that register holds a zero value, + the instruction will not action any attendant per-field side effects, but will action any + side effects caused by writing to the entire CSR. +definedBy: + extension: + name: Zicsr +assembly: xd, csr, xs1 +encoding: + match: "-----------------011-----1110011" + variables: + - name: csr + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +pseudoinstructions: + - when: xd == 0 + to: csrc csr,xs1 +operation(): | + Csr csr_handle = direct_csr_lookup(csr); + + Boolean will_write = xs1 != 0; + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); + + if (xs1 != 0) { + # clear bits using the mask + # performing any WARL transformations first + XReg mask = X[xs1]; + csr_sw_write(csr_handle, initial_csr_value & ~mask); + } + + X[xd] = initial_csr_value; diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrci.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrci.yaml new file mode 100644 index 000000000000..6a6d00ecd3c6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrci.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: csrrci +long_name: Atomic Read and Clear Bits in CSR with Immediate +description: | + The CSRRCI variant is similar to CSRRC, except this updates the CSR using an XLEN-bit value obtained + by zero-extending a 5-bit unsigned immediate (imm[4:0]) field encoded in the `xs1` field instead of a + value from an integer register. For CSRRCI, if the `imm[4:0]` field is zero, then this instruction + will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on + a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. The CSRRCI will + always read the CSR and cause any read side effects regardless of `xd` and `xs1` fields. +definedBy: + extension: + name: Zicsr +assembly: xd, csr, imm +encoding: + match: "-----------------111-----1110011" + variables: + - name: csr + location: 31-20 + - name: imm + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +pseudoinstructions: + - when: xd == 0 + to: csrci csr,imm +operation(): | + Boolean will_write = imm != 0; + + Csr csr_handle = direct_csr_lookup(csr); + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); + + if (will_write) { + # set bits using the mask + # performing any WARL transformations first + XReg mask = imm; + csr_sw_write(csr_handle, initial_csr_value & ~mask); + } + + X[xd] = initial_csr_value; diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrs.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrs.yaml new file mode 100644 index 000000000000..471d41f09441 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrs.yaml @@ -0,0 +1,114 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: csrrs +long_name: Atomic Read and Set Bits in CSR +description: | + Atomically read and set bits in a CSR. + + Reads the value of the CSR, zero-extends the value to `XLEN` bits, + and writes it to integer register `xd`. The initial value in integer + register `xs1` is treated as a bit mask that specifies bit positions + to be set in the CSR. Any bit that is high in `xs1` will cause the + corresponding bit to be set in the CSR, if that CSR bit is writable. + Other bits in the CSR are not explicitly written. +definedBy: + extension: + name: Zicsr +assembly: xd, csr, xs1 +encoding: + match: "-----------------010-----1110011" + variables: + - name: csr + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +pseudoinstructions: + - when: xs1 == 0 && csr == 0x001 + to: frflags xd + - when: xs1 == 0 && csr == 0x002 + to: frrm xd + - when: xs1 == 0 && csr == 0x003 + to: frcsr xd + - when: xs1 == 0 && csr == 0xC00 + to: rdcycle xd + - when: xs1 == 0 && csr == 0xC01 + to: rdtime xd + - when: xs1 == 0 && csr == 0xC02 + to: rdinstret xd + - when: xs1 == 0 && csr == 0xC80 + to: rdcycleh xd + - when: xs1 == 0 && csr == 0xC81 + to: rdtimeh xd + - when: xs1 == 0 && csr == 0xC82 + to: rdinstreth xd + - when: xs1 == 0 + to: csrr xd,csr + - when: xd == 0 + to: csrs csr,xs1 +operation(): | + Boolean will_write = xs1 != 0; + + Csr csr_handle = direct_csr_lookup(csr); + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); + + if (will_write) { + # set bits using the mask + # performing any WARL transformations first + XReg mask = X[xs1]; + csr_sw_write(csr_handle, initial_csr_value | mask); + } + + X[xd] = initial_csr_value; + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); + let isWrite : bool = match op { + CSRRW => true, + _ => if is_imm then unsigned(rs1_val) != 0 else unsigned(rs1) != 0 + }; + if not(check_CSR(csr, cur_privilege, isWrite)) + then { handle_illegal(); RETIRE_FAIL } + else if not(ext_check_CSR(csr, cur_privilege, isWrite)) + then { ext_check_CSR_fail(); RETIRE_FAIL } + else { + let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */ + if isWrite then { + let new_val : xlenbits = match op { + CSRRW => rs1_val, + CSRRS => csr_val | rs1_val, + CSRRC => csr_val & ~(rs1_val) + }; + writeCSR(csr, new_val) + }; + X(rd) = csr_val; + RETIRE_SUCCESS + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrsi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrsi.yaml new file mode 100644 index 000000000000..4186d654c5a1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrsi.yaml @@ -0,0 +1,62 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: csrrsi +long_name: Atomic Read and Set Bits in CSR with Immediate +description: | + The CSRRSI variant is similar to CSRRS, except this updates the CSR using an XLEN-bit value obtained + by zero-extending a 5-bit unsigned immediate (imm[4:0]) field encoded in the `xs1` field instead of a + value from an integer register. For CSRRSI, if the `imm[4:0]` field is zero, then this instruction + will not write to the CSR, and shall not cause any of the side effects that might otherwise occur on + a CSR write, nor raise illegal-instruction exceptions on accesses to read-only CSRs. The CSRRSI will + always read the CSR and cause any read side effects regardless of `xd` and `xs1` fields. +definedBy: + extension: + name: Zicsr +assembly: xd, csr, imm +encoding: + match: "-----------------110-----1110011" + variables: + - name: csr + location: 31-20 + - name: imm + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +pseudoinstructions: + - when: xd == 0 + to: csrsi csr,imm +operation(): | + Boolean will_write = imm != 0; + + Csr csr_handle = direct_csr_lookup(csr); + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (will_write && csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + XReg initial_csr_value = csr_sw_read(csr_handle); + + if (will_write) { + # set bits using the mask + # performing any WARL transformations first + XReg mask = imm; + csr_sw_write(csr_handle, initial_csr_value | mask); + } + + X[xd] = initial_csr_value; diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrw.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrw.yaml new file mode 100644 index 000000000000..1716265853d4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrw.yaml @@ -0,0 +1,90 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: csrrw +long_name: Atomic Read/Write CSR +description: | + Atomically swap values in the CSRs and integer registers. + + Read the old value of the CSR, zero-extends the value to `XLEN` bits, + and then write it to integer register xd. + The initial value in xs1 is written to the CSR. + If `xd=x0`, then the instruction shall not read the CSR and shall not + cause any of the side effects that might occur on a CSR read. +definedBy: + extension: + name: Zicsr +assembly: xd, csr, xs1 +encoding: + match: "-----------------001-----1110011" + variables: + - name: csr + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +pseudoinstructions: + - when: xd == 0 + to: csrw csr,xs1 +operation(): | + Csr csr_handle = direct_csr_lookup(csr); + + Bits initial_value = X[xs1]; + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (xd != 0) { + X[xd] = csr_sw_read(csr_handle); + } + + # writes the value in X[xs1] to the CSR, + # performing any WARL transformations first + csr_sw_write(csr_handle, initial_value); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); + let isWrite : bool = match op { + CSRRW => true, + _ => if is_imm then unsigned(rs1_val) != 0 else unsigned(rs1) != 0 + }; + if not(check_CSR(csr, cur_privilege, isWrite)) + then { handle_illegal(); RETIRE_FAIL } + else if not(ext_check_CSR(csr, cur_privilege, isWrite)) + then { ext_check_CSR_fail(); RETIRE_FAIL } + else { + let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */ + if isWrite then { + let new_val : xlenbits = match op { + CSRRW => rs1_val, + CSRRS => csr_val | rs1_val, + CSRRC => csr_val & ~(rs1_val) + }; + writeCSR(csr, new_val) + }; + X(rd) = csr_val; + RETIRE_SUCCESS + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrwi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrwi.yaml new file mode 100644 index 000000000000..1e1ff5d10da3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zicsr/csrrwi.yaml @@ -0,0 +1,88 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: csrrwi +long_name: Atomic Read/Write CSR Immediate +description: | + Atomically write CSR using a 5-bit immediate, and load the previous value into 'xd'. + + Read the old value of the CSR, zero-extends the value to `XLEN` bits, + and then write it to integer register xd. + The 5-bit uimm field is zero-extended and written to the CSR. + If `xd=x0`, then the instruction shall not read the CSR and shall not + cause any of the side effects that might occur on a CSR read. +definedBy: + extension: + name: Zicsr +assembly: xd, csr, imm +encoding: + match: "-----------------101-----1110011" + variables: + - name: csr + location: 31-20 + - name: imm + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +pseudoinstructions: + - when: xd == 0 + to: csrwi csr,imm +operation(): | + Csr csr_handle = direct_csr_lookup(csr); + + # permission checks + if (csr_handle.valid == false) { + unimplemented_csr($encoding); + } else if (!compatible_mode?(csr_handle.mode, mode())) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } else if (csr_handle.writable == false) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + + if (xd != 0) { + X[xd] = csr_sw_read(csr_handle); + } + + # writes the zero-extended immediate to the CSR, + # performing any WARL transformations first + csr_sw_write(csr_handle, {{MXLEN-5{1'b0}}, imm}); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { + let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1); + let isWrite : bool = match op { + CSRRW => true, + _ => if is_imm then unsigned(rs1_val) != 0 else unsigned(rs1) != 0 + }; + if not(check_CSR(csr, cur_privilege, isWrite)) + then { handle_illegal(); RETIRE_FAIL } + else if not(ext_check_CSR(csr, cur_privilege, isWrite)) + then { ext_check_CSR_fail(); RETIRE_FAIL } + else { + let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */ + if isWrite then { + let new_val : xlenbits = match op { + CSRRW => rs1_val, + CSRRS => csr_val | rs1_val, + CSRRC => csr_val & ~(rs1_val) + }; + writeCSR(csr, new_val) + }; + X(rd) = csr_val; + RETIRE_SUCCESS + } + } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zifencei/fence.i.yaml b/pkg/ifuzz/riscv64/gen/inst/Zifencei/fence.i.yaml new file mode 100644 index 000000000000..70c4ec4798bc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zifencei/fence.i.yaml @@ -0,0 +1,65 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: fence.i +long_name: Instruction fence +description: | + The FENCE.I instruction is used to synchronize the instruction and data + streams. RISC-V does not guarantee that stores to instruction memory + will be made visible to instruction fetches on a RISC-V hart until that + hart executes a FENCE.I instruction. A FENCE.I instruction ensures that + a subsequent instruction fetch on a RISC-V hart will see any previous + data stores already visible to the same RISC-V hart. FENCE.I does _not_ + ensure that other RISC-V harts' instruction fetches will observe the + local hart's stores in a multiprocessor system. To make a store to + instruction memory visible to all RISC-V harts, the writing hart also + has to execute a data FENCE before requesting that all remote RISC-V + harts execute a FENCE.I. + + The unused fields in the FENCE.I instruction, _imm[11:0]_, _xs1_, and + _xd_, are reserved for finer-grain fences in future extensions. For + forward compatibility, base implementations shall ignore these fields, + and standard software shall zero these fields. + (((FENCE.I, finer-grained))) + (((FENCE.I, forward compatibility))) + + [NOTE] + ==== + Because FENCE.I only orders stores with a hart's own instruction + fetches, application code should only rely upon FENCE.I if the + application thread will not be migrated to a different hart. The EEI can + provide mechanisms for efficient multiprocessor instruction-stream + synchronization. + ==== +definedBy: + extension: + name: Zifencei +assembly: "" +encoding: + match: "-----------------001-----0001111" + variables: + - name: imm + location: 31-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +operation(): | + ifence(); + +# SPDX-SnippetBegin +# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model +# SPDX-License-Identifier: BSD-2-Clause +sail(): | + { /* __barrier(Barrier_RISCV_i); */ RETIRE_SUCCESS } + +# SPDX-SnippetEnd diff --git a/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.all.yaml b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.all.yaml new file mode 100644 index 000000000000..fbb2aa5707cb --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.all.yaml @@ -0,0 +1,27 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: c.ntl.all +long_name: Compressed non-temporal locality hint, all +description: | + The C.NTL.ALL instruction indicates that the immediately subsequent instruction + does not exhibit temporal locality within the capacity of any level of cache in + the memory hierarchy. C.NTL.ALL is encoded as C.ADD x0, x5. +definedBy: + extension: + allOf: + - name: Zca + - name: Zihintntl +assembly: "" +encoding: + match: "1001000000010110" +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false diff --git a/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.p1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.p1.yaml new file mode 100644 index 000000000000..82862bfdf630 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.p1.yaml @@ -0,0 +1,27 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: c.ntl.p1 +long_name: Compressed non-temporal locality hint, innermost private +description: | + The C.NTL.P1 instruction indicates that the immediately subsequent instruction + does not exhibit temporal locality within the capacity of the innermost level + of private cache in the memory hierarchy. C.NTL.P1 is encoded as C.ADD x0, x2. +definedBy: + extension: + allOf: + - name: Zca + - name: Zihintntl +assembly: "" +encoding: + match: "1001000000001010" +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false diff --git a/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.pall.yaml b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.pall.yaml new file mode 100644 index 000000000000..15b9d613d4dc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.pall.yaml @@ -0,0 +1,27 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: c.ntl.pall +long_name: Compressed non-temporal locality hint, all private +description: | + The C.NTL.PALL instruction indicates that the immediately subsequent instruction + does not exhibit temporal locality within the capacity of any level of private + cache in the memory hierarchy. C.NTL.PALL is encoded as C.ADD x0, x3. +definedBy: + extension: + allOf: + - name: Zca + - name: Zihintntl +assembly: "" +encoding: + match: "1001000000001110" +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false diff --git a/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.s1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.s1.yaml new file mode 100644 index 000000000000..ff767a616594 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/c.ntl.s1.yaml @@ -0,0 +1,27 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: c.ntl.s1 +long_name: Compressed non-temporal locality hint, innermost shared +description: | + The C.NTL.S1 instruction indicates that the immediately subsequent instruction + does not exhibit temporal locality within the capacity of the innermost level + of shared cache in the memory hierarchy. C.NTL.S1 is encoded as C.ADD x0, x4. +definedBy: + extension: + allOf: + - name: Zca + - name: Zihintntl +assembly: "" +encoding: + match: "1001000000010010" +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false diff --git a/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.all.yaml b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.all.yaml new file mode 100644 index 000000000000..03963122567e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.all.yaml @@ -0,0 +1,25 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: ntl.all +long_name: Non-temporal locality hint, all +description: | + The NTL.ALL instruction indicates that the immediately subsequent instruction + does not exhibit temporal locality within the capacity of any level of cache + in the memory hierarchy. NTL.ALL is encoded as ADD x0, x0, x5. +definedBy: + extension: + name: Zihintntl +assembly: "" +encoding: + match: "00000000010100000000000000110011" +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false diff --git a/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.p1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.p1.yaml new file mode 100644 index 000000000000..8fd695accff5 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.p1.yaml @@ -0,0 +1,25 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: ntl.p1 +long_name: Non-temporal locality hint, innermost private +description: | + The NTL.P1 instruction indicates that the immediately subsequent instruction + does not exhibit temporal locality within the capacity of the innermost level + of private cache in the memory hierarchy. NTL.P1 is encoded as ADD x0, x0, x2. +definedBy: + extension: + name: Zihintntl +assembly: "" +encoding: + match: "00000000001000000000000000110011" +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false diff --git a/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.pall.yaml b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.pall.yaml new file mode 100644 index 000000000000..7aa5bfb31e08 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.pall.yaml @@ -0,0 +1,25 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: ntl.pall +long_name: Non-temporal locality hint, all private +description: | + The NTL.PALL instruction indicates that the immediately subsequent instruction + does not exhibit temporal locality within the capacity of any level of private + cache in the memory hierarchy. NTL.PALL is encoded as ADD x0, x0, x3. +definedBy: + extension: + name: Zihintntl +assembly: "" +encoding: + match: "00000000001100000000000000110011" +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false diff --git a/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.s1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.s1.yaml new file mode 100644 index 000000000000..f53310ade76c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zihintntl/ntl.s1.yaml @@ -0,0 +1,25 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: ntl.s1 +long_name: Non-temporal locality hint, innermost shared +description: | + The NTL.S1 instruction indicates that the immediately subsequent instruction + does not exhibit temporal locality within the capacity of the innermost level + of shared cache in the memory hierarchy. NTL.S1 is encoded as ADD x0, x0, x4. +definedBy: + extension: + name: Zihintntl +assembly: "" +encoding: + match: "00000000010000000000000000110011" +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false diff --git a/pkg/ifuzz/riscv64/gen/inst/Zimop/mop.r.n.yaml b/pkg/ifuzz/riscv64/gen/inst/Zimop/mop.r.n.yaml new file mode 100644 index 000000000000..fd8789978a48 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zimop/mop.r.n.yaml @@ -0,0 +1,102 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: mop.r.n +long_name: May-be-operation (1 source register) +description: | + Unless redefined by another extension, this instructions simply writes 0 to X[xd]. + The encoding allows future extensions to define them to read X[xs1], as well as write X[xd]. +definedBy: + extension: + name: Zimop +assembly: xd, xs1 +encoding: + match: 1-00--0111-------100-----1110011 + variables: + - name: n + location: 30|27-26|21-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +hints: + - { $ref: inst/Zicfilp/sspopchk.x1.yaml# } + - { $ref: inst/Zicfilp/sspopchk.x5.yaml# } + - { $ref: inst/Zicfiss/ssrdp.yaml# } +pseudoinstructions: + - when: n == 0 + to: mop.r.0 + - when: n == 1 + to: mop.r.1 + - when: n == 2 + to: mop.r.2 + - when: n == 3 + to: mop.r.3 + - when: n == 4 + to: mop.r.4 + - when: n == 5 + to: mop.r.5 + - when: n == 6 + to: mop.r.6 + - when: n == 7 + to: mop.r.7 + - when: n == 8 + to: mop.r.8 + - when: n == 9 + to: mop.r.9 + - when: n == 10 + to: mop.r.10 + - when: n == 11 + to: mop.r.11 + - when: n == 12 + to: mop.r.12 + - when: n == 13 + to: mop.r.13 + - when: n == 14 + to: mop.r.14 + - when: n == 15 + to: mop.r.15 + - when: n == 16 + to: mop.r.16 + - when: n == 17 + to: mop.r.17 + - when: n == 18 + to: mop.r.18 + - when: n == 19 + to: mop.r.19 + - when: n == 20 + to: mop.r.20 + - when: n == 21 + to: mop.r.21 + - when: n == 22 + to: mop.r.22 + - when: n == 23 + to: mop.r.23 + - when: n == 24 + to: mop.r.24 + - when: n == 25 + to: mop.r.25 + - when: n == 26 + to: mop.r.26 + - when: n == 27 + to: mop.r.27 + - when: n == 28 + to: mop.r.28 + - when: n == 29 + to: mop.r.29 + - when: n == 30 + to: mop.r.30 + - when: n == 31 + to: mop.r.31 +operation(): | + X[xd] = 0; diff --git a/pkg/ifuzz/riscv64/gen/inst/Zimop/mop.rr.n.yaml b/pkg/ifuzz/riscv64/gen/inst/Zimop/mop.rr.n.yaml new file mode 100644 index 000000000000..d9b5e7ad08d8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zimop/mop.rr.n.yaml @@ -0,0 +1,56 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: mop.rr.n +long_name: May-be-operation (2 source registers) +description: | + The Zimop extension defines 8 MOP instructions named MOP.RR.n, where n is an integer between 0 + and 7, inclusive. Unless redefined by another extension, these instructions simply write 0 to X[xd]. + Their encoding allows future extensions to define them to read X[xs1] and X[xs2], as well as write X[xd]. +definedBy: + extension: + name: Zimop +assembly: xd, xs1, xs2 +encoding: + match: 1-00--1----------100-----1110011 + variables: + - name: n + location: 30|27-26 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +hints: + - { $ref: inst/Zicfilp/sspush.x1.yaml# } + - { $ref: inst/Zicfilp/sspush.x5.yaml# } +pseudoinstructions: + - when: n == 0 + to: mop.rr.0 + - when: n == 1 + to: mop.rr.1 + - when: n == 2 + to: mop.rr.2 + - when: n == 3 + to: mop.rr.3 + - when: n == 4 + to: mop.rr.4 + - when: n == 5 + to: mop.rr.5 + - when: n == 6 + to: mop.rr.6 + - when: n == 7 + to: mop.rr.7 +operation(): | + X[xd] = 0; diff --git a/pkg/ifuzz/riscv64/gen/inst/Zkn/aes64ks1i.yaml b/pkg/ifuzz/riscv64/gen/inst/Zkn/aes64ks1i.yaml new file mode 100644 index 000000000000..4af58b24b7c1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zkn/aes64ks1i.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes64ks1i +long_name: AES Key Schedule Instruction 1 +description: | + This instruction implements the rotation, SubBytes and Round Constant addition steps of the AES + block cipher Key Schedule. + `rnum` must be in the range `0x0..0xA`. The values `0xB..0xF` are reserved. +definedBy: + allOf: + - xlen: 64 + - extension: + anyOf: + - name: Zknd + - name: Zkne +assembly: xd, xs1, rnum +encoding: + match: 00110001---------001-----0010011 + variables: + - name: rnum + location: 23-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zkn/aes64ks2.yaml b/pkg/ifuzz/riscv64/gen/inst/Zkn/aes64ks2.yaml new file mode 100644 index 000000000000..e7f51b827ac0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zkn/aes64ks2.yaml @@ -0,0 +1,36 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes64ks2 +long_name: AES Key Schedule Instruction 2 +description: | + This instruction implements the additional XOR'ing of key words as part of the AES block cipher + Key Schedule. +definedBy: + allOf: + - xlen: 64 + - extension: + anyOf: + - name: Zknd + - name: Zkne +assembly: xd, xs1, xs2 +encoding: + match: 0111111----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknd/aes32dsi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknd/aes32dsi.yaml new file mode 100644 index 000000000000..6503a8cef91d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknd/aes32dsi.yaml @@ -0,0 +1,37 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes32dsi +long_name: AES final round decryption instruction for RV32 +description: | + Sources a single byte from `xs2` according to `bs`. To this it applies the inverse AES + SBox operation, and XOR's the result with `xs1`. This instruction must always be implemented such + that its execution latency does not depend on the data being operated on. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zknd +assembly: xd, xs1, xs2, bs +encoding: + match: --10101----------000-----0110011 + variables: + - name: bs + location: 31-30 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknd/aes32dsmi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknd/aes32dsmi.yaml new file mode 100644 index 000000000000..01ea43dfeb6c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknd/aes32dsmi.yaml @@ -0,0 +1,38 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes32dsmi +long_name: AES middle round decryption instruction for RV32 +description: | + Sources a single byte from `xs2` according to `bs`. To this it applies the inverse AES + SBox operation, and a partial inverse MixColumn, before XOR'ing the result with `xs1`. This + instruction must always be implemented such that its execution latency does not depend on the + data being operated on. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zknd +assembly: xd, xs1, xs2, bs +encoding: + match: --10111----------000-----0110011 + variables: + - name: bs + location: 31-30 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknd/aes64ds.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknd/aes64ds.yaml new file mode 100644 index 000000000000..74135569586a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknd/aes64ds.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes64ds +long_name: AES decrypt final round +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zknd +description: | + Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next + round output, applying the Inverse ShiftRows and SubBytes steps. +assembly: xd, xs1, xs2 +encoding: + match: 0011101----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknd/aes64dsm.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknd/aes64dsm.yaml new file mode 100644 index 000000000000..3dd4decf1e75 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknd/aes64dsm.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes64dsm +long_name: AES decrypt middle round +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zknd +description: | + Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next + round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps. +assembly: xd, xs1, xs2 +encoding: + match: 0011111----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknd/aes64im.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknd/aes64im.yaml new file mode 100644 index 000000000000..943b5821b33b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknd/aes64im.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes64im +long_name: AES Decrypt KeySchedule MixColumns +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zknd +description: | + The instruction applies the inverse MixColumns transformation to two columns of the state array, + packed into a single 64-bit register. It is used to create the inverse cipher KeySchedule, according to + the equivalent inverse cipher construction in (NIST, 2001) (Page 23, Section 5.3.5). +assembly: xd, xs1 +encoding: + match: 001100000000-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zkne/aes32esi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zkne/aes32esi.yaml new file mode 100644 index 000000000000..04d1245392be --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zkne/aes32esi.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes32esi +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zkne +assembly: xd, xs1, xs2, bs +encoding: + match: --10001----------000-----0110011 + variables: + - name: bs + location: 31-30 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zkne/aes32esmi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zkne/aes32esmi.yaml new file mode 100644 index 000000000000..0ed58807d928 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zkne/aes32esmi.yaml @@ -0,0 +1,35 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes32esmi +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zkne +assembly: xd, xs1, xs2, bs +encoding: + match: --10011----------000-----0110011 + variables: + - name: bs + location: 31-30 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zkne/aes64es.yaml b/pkg/ifuzz/riscv64/gen/inst/Zkne/aes64es.yaml new file mode 100644 index 000000000000..715fbb5a458a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zkne/aes64es.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes64es +long_name: AES encrypt final round +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zkne +description: | + Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next + round output, applying the ShiftRows and SubBytes steps. +assembly: xd, xs1, xs2 +encoding: + match: 0011001----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zkne/aes64esm.yaml b/pkg/ifuzz/riscv64/gen/inst/Zkne/aes64esm.yaml new file mode 100644 index 000000000000..f500e94cae33 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zkne/aes64esm.yaml @@ -0,0 +1,34 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: aes64esm +long_name: AES encrypt middle round +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zkne +description: | + Uses the two 64-bit source registers to represent the entire AES state, and produces _half_ of the next + round output, applying the Inverse ShiftRows, SubBytes and MixColumns steps. +assembly: xd, xs1, xs2 +encoding: + match: 0011011----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sig0.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sig0.yaml new file mode 100644 index 000000000000..054b4d834e2b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sig0.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha256sig0 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zknh +assembly: xd, xs1 +encoding: + match: 000100000010-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sig1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sig1.yaml new file mode 100644 index 000000000000..84a076c49188 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sig1.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha256sig1 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zknh +assembly: xd, xs1 +encoding: + match: 000100000011-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sum0.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sum0.yaml new file mode 100644 index 000000000000..8a376372562d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sum0.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha256sum0 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zknh +assembly: xd, xs1 +encoding: + match: 000100000000-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sum1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sum1.yaml new file mode 100644 index 000000000000..c3e519d8996c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha256sum1.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha256sum1 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zknh +assembly: xd, xs1 +encoding: + match: 000100000001-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig0.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig0.yaml new file mode 100644 index 000000000000..1d8b274f3f09 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig0.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha512sig0 +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zknh +assembly: xd, xs1 +encoding: + match: 000100000110-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig0h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig0h.yaml new file mode 100644 index 000000000000..9607a8d71a0a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig0h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha512sig0h +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zknh +assembly: xd, xs1, xs2 +encoding: + match: 0101110----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig0l.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig0l.yaml new file mode 100644 index 000000000000..f20edea07299 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig0l.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha512sig0l +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zknh +assembly: xd, xs1, xs2 +encoding: + match: 0101010----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig1.yaml new file mode 100644 index 000000000000..8b9f7100499a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig1.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha512sig1 +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zknh +assembly: xd, xs1 +encoding: + match: 000100000111-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig1h.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig1h.yaml new file mode 100644 index 000000000000..e5c8b398ad3a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig1h.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha512sig1h +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zknh +assembly: xd, xs1, xs2 +encoding: + match: 0101111----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig1l.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig1l.yaml new file mode 100644 index 000000000000..e38eabd6917c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sig1l.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha512sig1l +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zknh +assembly: xd, xs1, xs2 +encoding: + match: 0101011----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum0.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum0.yaml new file mode 100644 index 000000000000..cff928fe28a6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum0.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha512sum0 +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zknh +assembly: xd, xs1 +encoding: + match: 000100000100-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum0r.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum0r.yaml new file mode 100644 index 000000000000..1b4cfbbe19b4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum0r.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha512sum0r +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zknh +assembly: xd, xs1, xs2 +encoding: + match: 0101000----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum1.yaml new file mode 100644 index 000000000000..9ba6829aea8d --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum1.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha512sum1 +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 64 + - extension: + name: Zknh +assembly: xd, xs1 +encoding: + match: 000100000101-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum1r.yaml b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum1r.yaml new file mode 100644 index 000000000000..eb423f8e389b --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zknh/sha512sum1r.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sha512sum1r +long_name: No synopsis available +description: | + No description available. +definedBy: + allOf: + - xlen: 32 + - extension: + name: Zknh +assembly: xd, xs1, xs2 +encoding: + match: 0101001----------000-----0110011 + variables: + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zks/sm3p0.yaml b/pkg/ifuzz/riscv64/gen/inst/Zks/sm3p0.yaml new file mode 100644 index 000000000000..dcbd6ac1d84c --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zks/sm3p0.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sm3p0 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zksh +assembly: xd, xs1 +encoding: + match: 000100001000-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zks/sm3p1.yaml b/pkg/ifuzz/riscv64/gen/inst/Zks/sm3p1.yaml new file mode 100644 index 000000000000..92ff8f3e4162 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zks/sm3p1.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sm3p1 +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zksh +assembly: xd, xs1 +encoding: + match: 000100001001-----001-----0010011 + variables: + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zks/sm4ed.yaml b/pkg/ifuzz/riscv64/gen/inst/Zks/sm4ed.yaml new file mode 100644 index 000000000000..3aa7e6c5a6f3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zks/sm4ed.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sm4ed +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zksed +assembly: xd, xs1, xs2, bs +encoding: + match: --11000----------000-----0110011 + variables: + - name: bs + location: 31-30 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zks/sm4ks.yaml b/pkg/ifuzz/riscv64/gen/inst/Zks/sm4ks.yaml new file mode 100644 index 000000000000..007f4a8c5ca1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zks/sm4ks.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: sm4ks +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zksed +assembly: xd, xs1, xs2, bs +encoding: + match: --11010----------000-----0110011 + variables: + - name: bs + location: 31-30 + - name: xs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: xd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vandn.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vandn.vv.yaml new file mode 100644 index 000000000000..16d624c0cb46 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vandn.vv.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vandn.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, vs1, vm +encoding: + match: 000001-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vandn.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vandn.vx.yaml new file mode 100644 index 000000000000..56e72d367ad1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vandn.vx.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vandn.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, xs1, vm +encoding: + match: 000001-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vbrev.v.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vbrev.v.yaml new file mode 100644 index 000000000000..6623036cb1bd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vbrev.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vbrev.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, vm +encoding: + match: 010010------01010010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vbrev8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vbrev8.v.yaml new file mode 100644 index 000000000000..330bd7a50a66 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vbrev8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vbrev8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, vm +encoding: + match: 010010------01000010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vclz.v.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vclz.v.yaml new file mode 100644 index 000000000000..42b94667a04a --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vclz.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vclz.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, vm +encoding: + match: 010010------01100010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vcpop.v.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vcpop.v.yaml new file mode 100644 index 000000000000..61846eda4513 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vcpop.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vcpop.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, vm +encoding: + match: 010010------01110010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vctz.v.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vctz.v.yaml new file mode 100644 index 000000000000..014724bf8ee3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vctz.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vctz.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, vm +encoding: + match: 010010------01101010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vrev8.v.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vrev8.v.yaml new file mode 100644 index 000000000000..7aa2346ca285 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vrev8.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrev8.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, vm +encoding: + match: 010010------01001010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vrol.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vrol.vv.yaml new file mode 100644 index 000000000000..05c49b284ba6 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vrol.vv.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrol.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, vs1, vm +encoding: + match: 010101-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vrol.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vrol.vx.yaml new file mode 100644 index 000000000000..4a0c77880af0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vrol.vx.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vrol.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, xs1, vm +encoding: + match: 010101-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vror.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vror.vi.yaml new file mode 100644 index 000000000000..53e8a40517b4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vror.vi.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vror.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, imm, vm +encoding: + match: 01010------------011-----1010111 + variables: + - name: imm + location: 26|19-15 + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vror.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vror.vv.yaml new file mode 100644 index 000000000000..b7f246d3f84f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vror.vv.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vror.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, vs1, vm +encoding: + match: 010100-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vror.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vror.vx.yaml new file mode 100644 index 000000000000..48e85e726699 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vror.vx.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vror.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, xs1, vm +encoding: + match: 010100-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vwsll.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vwsll.vi.yaml new file mode 100644 index 000000000000..3530df44b8f4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vwsll.vi.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsll.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, imm, vm +encoding: + match: 110101-----------011-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vwsll.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vwsll.vv.yaml new file mode 100644 index 000000000000..55801dc9f83f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vwsll.vv.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsll.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, vs1, vm +encoding: + match: 110101-----------000-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbb/vwsll.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vwsll.vx.yaml new file mode 100644 index 000000000000..113747a19010 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbb/vwsll.vx.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vwsll.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbb +assembly: vd, vs2, xs1, vm +encoding: + match: 110101-----------100-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmul.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmul.vv.yaml new file mode 100644 index 000000000000..ecbe9bae9c19 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmul.vv.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vclmul.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbc +assembly: vd, vs2, vs1, vm +encoding: + match: 001100-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmul.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmul.vx.yaml new file mode 100644 index 000000000000..2f3d3863ab81 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmul.vx.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vclmul.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbc +assembly: vd, vs2, xs1, vm +encoding: + match: 001100-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmulh.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmulh.vv.yaml new file mode 100644 index 000000000000..37fff25816a3 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmulh.vv.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vclmulh.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbc +assembly: vd, vs2, vs1, vm +encoding: + match: 001101-----------010-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmulh.vx.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmulh.vx.yaml new file mode 100644 index 000000000000..d9f48cca2abd --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvbc/vclmulh.vx.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vclmulh.vx +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvbc +assembly: vd, vs2, xs1, vm +encoding: + match: 001101-----------110-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: xs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml new file mode 100644 index 000000000000..59fe7f2ada06 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvfbfmin/vfncvtbf16.f.f.w.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfncvtbf16.f.f.w +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvfbfmin +assembly: vd, vs2, vm +encoding: + match: 010010------11101001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml new file mode 100644 index 000000000000..a0bbe20c7af8 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvfbfmin/vfwcvtbf16.f.f.v.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwcvtbf16.f.f.v +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvfbfmin +assembly: vd, vs2, vm +encoding: + match: 010010------01101001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvfbfwma/vfwmaccbf16.vf.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvfbfwma/vfwmaccbf16.vf.yaml new file mode 100644 index 000000000000..a8d7324994e1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvfbfwma/vfwmaccbf16.vf.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwmaccbf16.vf +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvfbfwma +assembly: vd, fs1, vs2, vm +encoding: + match: 111011-----------101-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: fs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvfbfwma/vfwmaccbf16.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvfbfwma/vfwmaccbf16.vv.yaml new file mode 100644 index 000000000000..e550d9986fbf --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvfbfwma/vfwmaccbf16.vv.yaml @@ -0,0 +1,33 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vfwmaccbf16.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvfbfwma +assembly: vd, vs1, vs2, vm +encoding: + match: 111011-----------001-----1010111 + variables: + - name: vm + location: 25-25 + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkg/vghsh.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkg/vghsh.vv.yaml new file mode 100644 index 000000000000..8a8fea805d2e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkg/vghsh.vv.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vghsh.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkg +assembly: vd, vs2, vs1 +encoding: + match: 1011001----------010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkg/vgmul.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkg/vgmul.vv.yaml new file mode 100644 index 000000000000..80e092d2ddc9 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkg/vgmul.vv.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vgmul.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkg +assembly: vd, vs2 +encoding: + match: 1010001-----10001010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdf.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdf.vs.yaml new file mode 100644 index 000000000000..1a218ecf50c0 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdf.vs.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaesdf.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2 +encoding: + match: 1010011-----00001010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdf.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdf.vv.yaml new file mode 100644 index 000000000000..1fa5392881e1 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdf.vv.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaesdf.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2 +encoding: + match: 1010001-----00001010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdm.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdm.vs.yaml new file mode 100644 index 000000000000..61421af3cb49 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdm.vs.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaesdm.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2 +encoding: + match: 1010011-----00000010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdm.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdm.vv.yaml new file mode 100644 index 000000000000..de65d232b36e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesdm.vv.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaesdm.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2 +encoding: + match: 1010001-----00000010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesef.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesef.vs.yaml new file mode 100644 index 000000000000..8c521d825720 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesef.vs.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaesef.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2 +encoding: + match: 1010011-----00011010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesef.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesef.vv.yaml new file mode 100644 index 000000000000..5b3aff507bfc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesef.vv.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaesef.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2 +encoding: + match: 1010001-----00011010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesem.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesem.vs.yaml new file mode 100644 index 000000000000..d5959c03e052 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesem.vs.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaesem.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2 +encoding: + match: 1010011-----00010010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesem.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesem.vv.yaml new file mode 100644 index 000000000000..9e78e1d19a98 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesem.vv.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaesem.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2 +encoding: + match: 1010001-----00010010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaeskf1.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaeskf1.vi.yaml new file mode 100644 index 000000000000..068c4e448a60 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaeskf1.vi.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaeskf1.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2, imm +encoding: + match: 1000101----------010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaeskf2.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaeskf2.vi.yaml new file mode 100644 index 000000000000..0e4c73d9c3bc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaeskf2.vi.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaeskf2.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2, imm +encoding: + match: 1010101----------010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesz.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesz.vs.yaml new file mode 100644 index 000000000000..81b56d05db0e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvkned/vaesz.vs.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vaesz.vs +long_name: Vector AES round zero +description: | + No description available. +definedBy: + extension: + name: Zvkned +assembly: vd, vs2 +encoding: + match: 1010011-----00111010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvknha/vsha2ch.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvknha/vsha2ch.vv.yaml new file mode 100644 index 000000000000..ea4e8ee96901 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvknha/vsha2ch.vv.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsha2ch.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvknha +assembly: vd, vs2, vs1 +encoding: + match: 1011101----------010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvknha/vsha2cl.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvknha/vsha2cl.vv.yaml new file mode 100644 index 000000000000..2b621d5be2dc --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvknha/vsha2cl.vv.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsha2cl.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvknha +assembly: vd, vs2, vs1 +encoding: + match: 1011111----------010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvknha/vsha2ms.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvknha/vsha2ms.vv.yaml new file mode 100644 index 000000000000..f0ca129c583f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvknha/vsha2ms.vv.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsha2ms.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvknha +assembly: vd, vs2, vs1 +encoding: + match: 1011011----------010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm3c.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm3c.vi.yaml new file mode 100644 index 000000000000..765e22365799 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm3c.vi.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsm3c.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvksh +assembly: vd, vs2, imm +encoding: + match: 1010111----------010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm3me.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm3me.vv.yaml new file mode 100644 index 000000000000..d9d18b07534f --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm3me.vv.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsm3me.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvksh +assembly: vd, vs2, vs1 +encoding: + match: 1000001----------010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vs1 + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm4k.vi.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm4k.vi.yaml new file mode 100644 index 000000000000..71dde491217e --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm4k.vi.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsm4k.vi +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvksed +assembly: vd, vs2, imm +encoding: + match: 1000011----------010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: imm + location: 19-15 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm4r.vs.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm4r.vs.yaml new file mode 100644 index 000000000000..328ba1e236c4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm4r.vs.yaml @@ -0,0 +1,29 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsm4r.vs +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + name: Zvksed +assembly: vd, vs2 +encoding: + match: 1010011-----10000010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm4r.vv.yaml b/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm4r.vv.yaml new file mode 100644 index 000000000000..45f2527f54c4 --- /dev/null +++ b/pkg/ifuzz/riscv64/gen/inst/Zvks/vsm4r.vv.yaml @@ -0,0 +1,31 @@ +# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: "inst_schema.json#" +kind: instruction +name: vsm4r.vv +long_name: No synopsis available +description: | + No description available. +definedBy: + extension: + anyOf: + - name: Zvks + - name: Zvksed +assembly: vd, vs2 +encoding: + match: 1010001-----10000010-----1110111 + variables: + - name: vs2 + location: 24-20 + - name: vd + location: 11-7 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: true +operation(): | diff --git a/pkg/ifuzz/riscv64/generated/empty.go b/pkg/ifuzz/riscv64/generated/empty.go new file mode 100644 index 000000000000..e3ab8bca1d05 --- /dev/null +++ b/pkg/ifuzz/riscv64/generated/empty.go @@ -0,0 +1,6 @@ +// Copyright 2026 syzkaller project authors. All rights reserved. +// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file. + +// To unbreak build with insns.go is excluded by build tags. + +package generated diff --git a/pkg/ifuzz/riscv64/generated/insns.go b/pkg/ifuzz/riscv64/generated/insns.go new file mode 100644 index 000000000000..1f5cecd3c9a4 --- /dev/null +++ b/pkg/ifuzz/riscv64/generated/insns.go @@ -0,0 +1,6225 @@ +// Code generated by pkg/ifuzz/riscv64/gen. DO NOT EDIT. + +// go:build !codeanalysis + +package generated + +import ( + . "github.com/google/syzkaller/pkg/ifuzz/riscv64" +) + +func init() { + Register(insns_riscv64) +} + +var insns_riscv64 = []*Insn{ + {Name: "roriw", OpcodeMask: 4261441663, Opcode: 1610633243, Fields: []InsnField{ + {"shamt", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1610633243, Generator: nil}, + {Name: "fadd.d", OpcodeMask: 4261412991, Opcode: 33554515, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 33554515, Generator: nil}, + {Name: "fclass.d", OpcodeMask: 4293947519, Opcode: 3791654995, Fields: []InsnField{ + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3791654995, Generator: nil}, + {Name: "fcvt.d.l", OpcodeMask: 4293918847, Opcode: 3525312595, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3525312595, Generator: nil}, + {Name: "fcvt.d.lu", OpcodeMask: 4293918847, Opcode: 3526361171, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3526361171, Generator: nil}, + {Name: "fcvt.d.s", OpcodeMask: 4293918847, Opcode: 1107296339, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1107296339, Generator: nil}, + {Name: "fcvt.d.w", OpcodeMask: 4293918847, Opcode: 3523215443, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3523215443, Generator: nil}, + {Name: "fcvt.d.wu", OpcodeMask: 4293918847, Opcode: 3524264019, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3524264019, Generator: nil}, + {Name: "fcvt.l.d", OpcodeMask: 4293918847, Opcode: 3256877139, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3256877139, Generator: nil}, + {Name: "fcvt.lu.d", OpcodeMask: 4293918847, Opcode: 3257925715, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3257925715, Generator: nil}, + {Name: "fcvt.s.d", OpcodeMask: 4293918847, Opcode: 1074790483, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1074790483, Generator: nil}, + {Name: "fcvt.w.d", OpcodeMask: 4293918847, Opcode: 3254779987, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3254779987, Generator: nil}, + {Name: "fcvt.wu.d", OpcodeMask: 4293918847, Opcode: 3255828563, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3255828563, Generator: nil}, + {Name: "fcvtmod.w.d", OpcodeMask: 4293918847, Opcode: 3263168595, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3263168595, Generator: nil}, + {Name: "fdiv.d", OpcodeMask: 4261412991, Opcode: 436207699, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 436207699, Generator: nil}, + {Name: "feq.d", OpcodeMask: 4261441663, Opcode: 2717917267, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2717917267, Generator: nil}, + {Name: "fld", OpcodeMask: 28799, Opcode: 12295, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 12295, Generator: nil}, + {Name: "fle.d", OpcodeMask: 4261441663, Opcode: 2717909075, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2717909075, Generator: nil}, + {Name: "fleq.d", OpcodeMask: 4261441663, Opcode: 2717925459, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2717925459, Generator: nil}, + {Name: "fli.d", OpcodeMask: 4293947519, Opcode: 4061134931, Fields: []InsnField{ + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 4061134931, Generator: nil}, + {Name: "flt.d", OpcodeMask: 4261441663, Opcode: 2717913171, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2717913171, Generator: nil}, + {Name: "fltq.d", OpcodeMask: 4261441663, Opcode: 2717929555, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2717929555, Generator: nil}, + {Name: "fmadd.d", OpcodeMask: 100663423, Opcode: 33554499, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 33554499, Generator: nil}, + {Name: "fmax.d", OpcodeMask: 4261441663, Opcode: 704647251, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 704647251, Generator: nil}, + {Name: "fmaxm.d", OpcodeMask: 4261441663, Opcode: 704655443, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 704655443, Generator: nil}, + {Name: "fmin.d", OpcodeMask: 4261441663, Opcode: 704643155, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 704643155, Generator: nil}, + {Name: "fminm.d", OpcodeMask: 4261441663, Opcode: 704651347, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 704651347, Generator: nil}, + {Name: "fmsub.d", OpcodeMask: 100663423, Opcode: 33554503, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 33554503, Generator: nil}, + {Name: "fmul.d", OpcodeMask: 4261412991, Opcode: 301989971, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 301989971, Generator: nil}, + {Name: "fmv.d.x", OpcodeMask: 4293947519, Opcode: 4060086355, Fields: []InsnField{ + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 4060086355, Generator: nil}, + {Name: "fmv.x.d", OpcodeMask: 4293947519, Opcode: 3791650899, Fields: []InsnField{ + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3791650899, Generator: nil}, + {Name: "fmvh.x.d", OpcodeMask: 4293947519, Opcode: 3792699475, Fields: []InsnField{ + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3792699475, Generator: nil}, + {Name: "fmvp.d.x", OpcodeMask: 4261441663, Opcode: 2986344531, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 2986344531, Generator: nil}, + {Name: "fnmadd.d", OpcodeMask: 100663423, Opcode: 33554511, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 33554511, Generator: nil}, + {Name: "fnmsub.d", OpcodeMask: 100663423, Opcode: 33554507, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 33554507, Generator: nil}, + {Name: "fround.d", OpcodeMask: 4293918847, Opcode: 1111490643, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1111490643, Generator: nil}, + {Name: "froundnx.d", OpcodeMask: 4293918847, Opcode: 1112539219, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1112539219, Generator: nil}, + {Name: "fsd", OpcodeMask: 28799, Opcode: 12327, Fields: []InsnField{ + {"imm_31_25", 31, 7}, + {"imm_11_7", 11, 5}, + {"fs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 12327, Generator: nil}, + {Name: "fsgnj.d", OpcodeMask: 4261441663, Opcode: 570425427, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 570425427, Generator: nil}, + {Name: "fsgnjn.d", OpcodeMask: 4261441663, Opcode: 570429523, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 570429523, Generator: nil}, + {Name: "fsgnjx.d", OpcodeMask: 4261441663, Opcode: 570433619, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 570433619, Generator: nil}, + {Name: "fsqrt.d", OpcodeMask: 4293918847, Opcode: 1509949523, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1509949523, Generator: nil}, + {Name: "fsub.d", OpcodeMask: 4261412991, Opcode: 167772243, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 167772243, Generator: nil}, + {Name: "fadd.s", OpcodeMask: 4261412991, Opcode: 83, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 83, Generator: nil}, + {Name: "fclass.s", OpcodeMask: 4293947519, Opcode: 3758100563, Fields: []InsnField{ + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3758100563, Generator: nil}, + {Name: "fcvt.l.s", OpcodeMask: 4293918847, Opcode: 3223322707, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3223322707, Generator: nil}, + {Name: "fcvt.lu.s", OpcodeMask: 4293918847, Opcode: 3224371283, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3224371283, Generator: nil}, + {Name: "fcvt.s.l", OpcodeMask: 4293918847, Opcode: 3491758163, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3491758163, Generator: nil}, + {Name: "fcvt.s.lu", OpcodeMask: 4293918847, Opcode: 3492806739, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3492806739, Generator: nil}, + {Name: "fcvt.s.w", OpcodeMask: 4293918847, Opcode: 3489661011, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3489661011, Generator: nil}, + {Name: "fcvt.s.wu", OpcodeMask: 4293918847, Opcode: 3490709587, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3490709587, Generator: nil}, + {Name: "fcvt.w.s", OpcodeMask: 4293918847, Opcode: 3221225555, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3221225555, Generator: nil}, + {Name: "fcvt.wu.s", OpcodeMask: 4293918847, Opcode: 3222274131, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3222274131, Generator: nil}, + {Name: "fdiv.s", OpcodeMask: 4261412991, Opcode: 402653267, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 402653267, Generator: nil}, + {Name: "feq.s", OpcodeMask: 4261441663, Opcode: 2684362835, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2684362835, Generator: nil}, + {Name: "fle.s", OpcodeMask: 4261441663, Opcode: 2684354643, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2684354643, Generator: nil}, + {Name: "fleq.s", OpcodeMask: 4261441663, Opcode: 2684371027, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2684371027, Generator: nil}, + {Name: "flt.s", OpcodeMask: 4261441663, Opcode: 2684358739, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2684358739, Generator: nil}, + {Name: "fltq.s", OpcodeMask: 4261441663, Opcode: 2684375123, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2684375123, Generator: nil}, + {Name: "flw", OpcodeMask: 28799, Opcode: 8199, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 8199, Generator: nil}, + {Name: "fmadd.s", OpcodeMask: 100663423, Opcode: 67, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 67, Generator: nil}, + {Name: "fmax.s", OpcodeMask: 4261441663, Opcode: 671092819, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 671092819, Generator: nil}, + {Name: "fmin.s", OpcodeMask: 4261441663, Opcode: 671088723, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 671088723, Generator: nil}, + {Name: "fmsub.s", OpcodeMask: 100663423, Opcode: 71, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 71, Generator: nil}, + {Name: "fmul.s", OpcodeMask: 4261412991, Opcode: 268435539, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 268435539, Generator: nil}, + {Name: "fmv.w.x", OpcodeMask: 4293947519, Opcode: 4026531923, Fields: []InsnField{ + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 4026531923, Generator: nil}, + {Name: "fmv.x.w", OpcodeMask: 4293947519, Opcode: 3758096467, Fields: []InsnField{ + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3758096467, Generator: nil}, + {Name: "fnmadd.s", OpcodeMask: 100663423, Opcode: 79, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 79, Generator: nil}, + {Name: "fnmsub.s", OpcodeMask: 100663423, Opcode: 75, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 75, Generator: nil}, + {Name: "fsgnj.s", OpcodeMask: 4261441663, Opcode: 536870995, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 536870995, Generator: nil}, + {Name: "fsgnjn.s", OpcodeMask: 4261441663, Opcode: 536875091, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 536875091, Generator: nil}, + {Name: "fsgnjx.s", OpcodeMask: 4261441663, Opcode: 536879187, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 536879187, Generator: nil}, + {Name: "fsqrt.s", OpcodeMask: 4293918847, Opcode: 1476395091, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1476395091, Generator: nil}, + {Name: "fsub.s", OpcodeMask: 4261412991, Opcode: 134217811, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 134217811, Generator: nil}, + {Name: "fsw", OpcodeMask: 28799, Opcode: 8231, Fields: []InsnField{ + {"imm_31_25", 31, 7}, + {"imm_11_7", 11, 5}, + {"fs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 8231, Generator: nil}, + {Name: "hfence.gvma", OpcodeMask: 4261445631, Opcode: 1644167283, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 1644167283, Generator: nil}, + {Name: "hfence.vvma", OpcodeMask: 4261445631, Opcode: 570425459, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 570425459, Generator: nil}, + {Name: "hlv.b", OpcodeMask: 4293947519, Opcode: 1610629235, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1610629235, Generator: nil}, + {Name: "hlv.bu", OpcodeMask: 4293947519, Opcode: 1611677811, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1611677811, Generator: nil}, + {Name: "hlv.d", OpcodeMask: 4293947519, Opcode: 1811955827, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1811955827, Generator: nil}, + {Name: "hlv.h", OpcodeMask: 4293947519, Opcode: 1677738099, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1677738099, Generator: nil}, + {Name: "hlv.hu", OpcodeMask: 4293947519, Opcode: 1678786675, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1678786675, Generator: nil}, + {Name: "hlv.w", OpcodeMask: 4293947519, Opcode: 1744846963, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1744846963, Generator: nil}, + {Name: "hlv.wu", OpcodeMask: 4293947519, Opcode: 1745895539, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1745895539, Generator: nil}, + {Name: "hlvx.hu", OpcodeMask: 4293947519, Opcode: 1680883827, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1680883827, Generator: nil}, + {Name: "hlvx.wu", OpcodeMask: 4293947519, Opcode: 1747992691, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1747992691, Generator: nil}, + {Name: "hsv.b", OpcodeMask: 4261445631, Opcode: 1644183667, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 1644183667, Generator: nil}, + {Name: "hsv.d", OpcodeMask: 4261445631, Opcode: 1845510259, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 1845510259, Generator: nil}, + {Name: "hsv.h", OpcodeMask: 4261445631, Opcode: 1711292531, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 1711292531, Generator: nil}, + {Name: "hsv.w", OpcodeMask: 4261445631, Opcode: 1778401395, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 1778401395, Generator: nil}, + {Name: "add", OpcodeMask: 4261441663, Opcode: 51, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 51, Generator: nil}, + {Name: "addi", OpcodeMask: 28799, Opcode: 19, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 19, Generator: nil}, + {Name: "addiw", OpcodeMask: 28799, Opcode: 27, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 27, Generator: nil}, + {Name: "addw", OpcodeMask: 4261441663, Opcode: 59, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 59, Generator: nil}, + {Name: "and", OpcodeMask: 4261441663, Opcode: 28723, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 28723, Generator: nil}, + {Name: "andi", OpcodeMask: 28799, Opcode: 28691, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 28691, Generator: nil}, + {Name: "auipc", OpcodeMask: 127, Opcode: 23, Fields: []InsnField{ + {"imm", 31, 20}, + {"xd", 11, 5}, + }, AsUInt32: 23, Generator: nil}, + {Name: "ebreak", OpcodeMask: 4294967295, Opcode: 1048691, AsUInt32: 1048691, Generator: nil}, + {Name: "ecall", OpcodeMask: 4294967295, Opcode: 115, AsUInt32: 115, Generator: nil}, + {Name: "fence.tso", OpcodeMask: 4293947519, Opcode: 2200961039, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2200961039, Generator: nil}, + {Name: "fence", OpcodeMask: 28799, Opcode: 15, Fields: []InsnField{ + {"fm", 31, 4}, + {"pred", 27, 4}, + {"succ", 23, 4}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 15, Generator: nil}, + {Name: "jalr", OpcodeMask: 28799, Opcode: 103, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 103, Generator: nil}, + {Name: "lb", OpcodeMask: 28799, Opcode: 3, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3, Generator: nil}, + {Name: "lbu", OpcodeMask: 28799, Opcode: 16387, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 16387, Generator: nil}, + {Name: "lh", OpcodeMask: 28799, Opcode: 4099, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 4099, Generator: nil}, + {Name: "lhu", OpcodeMask: 28799, Opcode: 20483, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 20483, Generator: nil}, + {Name: "lui", OpcodeMask: 127, Opcode: 55, Fields: []InsnField{ + {"imm", 31, 20}, + {"xd", 11, 5}, + }, AsUInt32: 55, Generator: nil}, + {Name: "lw", OpcodeMask: 28799, Opcode: 8195, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 8195, Generator: nil}, + {Name: "lwu", OpcodeMask: 28799, Opcode: 24579, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 24579, Generator: nil}, + {Name: "mret", OpcodeMask: 4294967295, Opcode: 807403635, AsUInt32: 807403635, Priv: true, Generator: nil}, + {Name: "or", OpcodeMask: 4261441663, Opcode: 24627, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 24627, Generator: nil}, + {Name: "ori", OpcodeMask: 28799, Opcode: 24595, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 24595, Generator: nil}, + {Name: "sb", OpcodeMask: 28799, Opcode: 35, Fields: []InsnField{ + {"imm_31_25", 31, 7}, + {"imm_11_7", 11, 5}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 35, Generator: nil}, + {Name: "sh", OpcodeMask: 28799, Opcode: 4131, Fields: []InsnField{ + {"imm_31_25", 31, 7}, + {"imm_11_7", 11, 5}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 4131, Generator: nil}, + {Name: "sll", OpcodeMask: 4261441663, Opcode: 4147, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 4147, Generator: nil}, + {Name: "slliw", OpcodeMask: 4261441663, Opcode: 4123, Fields: []InsnField{ + {"shamt", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 4123, Generator: nil}, + {Name: "sllw", OpcodeMask: 4261441663, Opcode: 4155, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 4155, Generator: nil}, + {Name: "slt", OpcodeMask: 4261441663, Opcode: 8243, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 8243, Generator: nil}, + {Name: "slti", OpcodeMask: 28799, Opcode: 8211, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 8211, Generator: nil}, + {Name: "sltiu", OpcodeMask: 28799, Opcode: 12307, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 12307, Generator: nil}, + {Name: "sltu", OpcodeMask: 4261441663, Opcode: 12339, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 12339, Generator: nil}, + {Name: "sra", OpcodeMask: 4261441663, Opcode: 1073762355, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1073762355, Generator: nil}, + {Name: "sraiw", OpcodeMask: 4261441663, Opcode: 1073762331, Fields: []InsnField{ + {"shamt", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1073762331, Generator: nil}, + {Name: "sraw", OpcodeMask: 4261441663, Opcode: 1073762363, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1073762363, Generator: nil}, + {Name: "srl", OpcodeMask: 4261441663, Opcode: 20531, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 20531, Generator: nil}, + {Name: "srliw", OpcodeMask: 4261441663, Opcode: 20507, Fields: []InsnField{ + {"shamt", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 20507, Generator: nil}, + {Name: "srlw", OpcodeMask: 4261441663, Opcode: 20539, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 20539, Generator: nil}, + {Name: "sub", OpcodeMask: 4261441663, Opcode: 1073741875, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1073741875, Generator: nil}, + {Name: "subw", OpcodeMask: 4261441663, Opcode: 1073741883, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1073741883, Generator: nil}, + {Name: "sw", OpcodeMask: 28799, Opcode: 8227, Fields: []InsnField{ + {"imm_31_25", 31, 7}, + {"imm_11_7", 11, 5}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 8227, Generator: nil}, + {Name: "wfi", OpcodeMask: 4294967295, Opcode: 273678451, AsUInt32: 273678451, Generator: nil}, + {Name: "xor", OpcodeMask: 4261441663, Opcode: 16435, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 16435, Generator: nil}, + {Name: "xori", OpcodeMask: 28799, Opcode: 16403, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 16403, Generator: nil}, + {Name: "div", OpcodeMask: 4261441663, Opcode: 33570867, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33570867, Generator: nil}, + {Name: "divu", OpcodeMask: 4261441663, Opcode: 33574963, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33574963, Generator: nil}, + {Name: "divuw", OpcodeMask: 4261441663, Opcode: 33574971, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33574971, Generator: nil}, + {Name: "divw", OpcodeMask: 4261441663, Opcode: 33570875, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33570875, Generator: nil}, + {Name: "mul", OpcodeMask: 4261441663, Opcode: 33554483, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33554483, Generator: nil}, + {Name: "mulh", OpcodeMask: 4261441663, Opcode: 33558579, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33558579, Generator: nil}, + {Name: "mulhsu", OpcodeMask: 4261441663, Opcode: 33562675, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33562675, Generator: nil}, + {Name: "mulhu", OpcodeMask: 4261441663, Opcode: 33566771, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33566771, Generator: nil}, + {Name: "mulw", OpcodeMask: 4261441663, Opcode: 33554491, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33554491, Generator: nil}, + {Name: "rem", OpcodeMask: 4261441663, Opcode: 33579059, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33579059, Generator: nil}, + {Name: "remu", OpcodeMask: 4261441663, Opcode: 33583155, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33583155, Generator: nil}, + {Name: "remuw", OpcodeMask: 4261441663, Opcode: 33583163, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33583163, Generator: nil}, + {Name: "remw", OpcodeMask: 4261441663, Opcode: 33579067, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33579067, Generator: nil}, + {Name: "fadd.q", OpcodeMask: 4261412991, Opcode: 100663379, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 100663379, Generator: nil}, + {Name: "fclass.q", OpcodeMask: 4293947519, Opcode: 3858763859, Fields: []InsnField{ + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3858763859, Generator: nil}, + {Name: "fcvt.d.q", OpcodeMask: 4293918847, Opcode: 1110442067, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1110442067, Generator: nil}, + {Name: "fcvt.h.q", OpcodeMask: 4293918847, Opcode: 1143996499, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1143996499, Generator: nil}, + {Name: "fcvt.l.q", OpcodeMask: 4293918847, Opcode: 3323986003, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3323986003, Generator: nil}, + {Name: "fcvt.lu.q", OpcodeMask: 4293918847, Opcode: 3325034579, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3325034579, Generator: nil}, + {Name: "fcvt.q.d", OpcodeMask: 4293918847, Opcode: 1175453779, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1175453779, Generator: nil}, + {Name: "fcvt.q.h", OpcodeMask: 4293918847, Opcode: 1176502355, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1176502355, Generator: nil}, + {Name: "fcvt.q.l", OpcodeMask: 4293918847, Opcode: 3592421459, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3592421459, Generator: nil}, + {Name: "fcvt.q.lu", OpcodeMask: 4293918847, Opcode: 3593470035, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3593470035, Generator: nil}, + {Name: "fcvt.q.s", OpcodeMask: 4293918847, Opcode: 1174405203, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1174405203, Generator: nil}, + {Name: "fcvt.q.w", OpcodeMask: 4293918847, Opcode: 3590324307, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3590324307, Generator: nil}, + {Name: "fcvt.q.wu", OpcodeMask: 4293918847, Opcode: 3591372883, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3591372883, Generator: nil}, + {Name: "fcvt.s.q", OpcodeMask: 4293918847, Opcode: 1076887635, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1076887635, Generator: nil}, + {Name: "fcvt.w.q", OpcodeMask: 4293918847, Opcode: 3321888851, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3321888851, Generator: nil}, + {Name: "fcvt.wu.q", OpcodeMask: 4293918847, Opcode: 3322937427, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3322937427, Generator: nil}, + {Name: "fdiv.q", OpcodeMask: 4261412991, Opcode: 503316563, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 503316563, Generator: nil}, + {Name: "feq.q", OpcodeMask: 4261441663, Opcode: 2785026131, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2785026131, Generator: nil}, + {Name: "fle.q", OpcodeMask: 4261441663, Opcode: 2785017939, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2785017939, Generator: nil}, + {Name: "fleq.q", OpcodeMask: 4261441663, Opcode: 2785034323, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2785034323, Generator: nil}, + {Name: "fli.q", OpcodeMask: 4293947519, Opcode: 4128243795, Fields: []InsnField{ + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 4128243795, Generator: nil}, + {Name: "flq", OpcodeMask: 28799, Opcode: 16391, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 16391, Generator: nil}, + {Name: "flt.q", OpcodeMask: 4261441663, Opcode: 2785022035, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2785022035, Generator: nil}, + {Name: "fltq.q", OpcodeMask: 4261441663, Opcode: 2785038419, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 2785038419, Generator: nil}, + {Name: "fmadd.q", OpcodeMask: 100663423, Opcode: 100663363, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 100663363, Generator: nil}, + {Name: "fmax.q", OpcodeMask: 4261441663, Opcode: 771756115, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 771756115, Generator: nil}, + {Name: "fmaxm.q", OpcodeMask: 4261441663, Opcode: 771764307, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 771764307, Generator: nil}, + {Name: "fmin.q", OpcodeMask: 4261441663, Opcode: 771752019, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 771752019, Generator: nil}, + {Name: "fminm.q", OpcodeMask: 4261441663, Opcode: 771760211, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 771760211, Generator: nil}, + {Name: "fmsub.q", OpcodeMask: 100663423, Opcode: 100663367, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 100663367, Generator: nil}, + {Name: "fmul.q", OpcodeMask: 4261412991, Opcode: 369098835, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 369098835, Generator: nil}, + {Name: "fmvh.x.q", OpcodeMask: 4293947519, Opcode: 3859808339, Fields: []InsnField{ + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3859808339, Generator: nil}, + {Name: "fmvp.q.x", OpcodeMask: 4261441663, Opcode: 3053453395, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 3053453395, Generator: nil}, + {Name: "fnmadd.q", OpcodeMask: 100663423, Opcode: 100663375, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 100663375, Generator: nil}, + {Name: "fnmsub.q", OpcodeMask: 100663423, Opcode: 100663371, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 100663371, Generator: nil}, + {Name: "fround.q", OpcodeMask: 4293918847, Opcode: 1178599507, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1178599507, Generator: nil}, + {Name: "froundnx.q", OpcodeMask: 4293918847, Opcode: 1179648083, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1179648083, Generator: nil}, + {Name: "fsgnj.q", OpcodeMask: 4261441663, Opcode: 637534291, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 637534291, Generator: nil}, + {Name: "fsgnjn.q", OpcodeMask: 4261441663, Opcode: 637538387, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 637538387, Generator: nil}, + {Name: "fsgnjx.q", OpcodeMask: 4261441663, Opcode: 637542483, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 637542483, Generator: nil}, + {Name: "fsq", OpcodeMask: 28799, Opcode: 16423, Fields: []InsnField{ + {"imm_31_25", 31, 7}, + {"imm_11_7", 11, 5}, + {"fs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 16423, Generator: nil}, + {Name: "fsqrt.q", OpcodeMask: 4293918847, Opcode: 1577058387, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1577058387, Generator: nil}, + {Name: "fsub.q", OpcodeMask: 4261412991, Opcode: 234881107, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 234881107, Generator: nil}, + {Name: "sfence.vma", OpcodeMask: 4261445631, Opcode: 301990003, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 301990003, Priv: true, Generator: nil}, + {Name: "sret", OpcodeMask: 4294967295, Opcode: 270532723, AsUInt32: 270532723, Priv: true, Generator: nil}, + {Name: "dret", OpcodeMask: 4294967295, Opcode: 2065694835, AsUInt32: 2065694835, Generator: nil}, + {Name: "sctrclr", OpcodeMask: 4294967295, Opcode: 272629875, AsUInt32: 272629875, Generator: nil}, + {Name: "mnret", OpcodeMask: 4294967295, Opcode: 1881145459, AsUInt32: 1881145459, Generator: nil}, + {Name: "hinval.gvma", OpcodeMask: 4261445631, Opcode: 1711276147, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 1711276147, Priv: true, Generator: nil}, + {Name: "hinval.vvma", OpcodeMask: 4261445631, Opcode: 637534323, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 637534323, Priv: true, Generator: nil}, + {Name: "sfence.inval.ir", OpcodeMask: 4294967295, Opcode: 403701875, AsUInt32: 403701875, Priv: true, Generator: nil}, + {Name: "sfence.w.inval", OpcodeMask: 4294967295, Opcode: 402653299, AsUInt32: 402653299, Priv: true, Generator: nil}, + {Name: "sinval.vma", OpcodeMask: 4261445631, Opcode: 369098867, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 369098867, Priv: true, Generator: nil}, + {Name: "vaadd.vv", OpcodeMask: 4227887231, Opcode: 603988055, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 603988055, Generator: nil}, + {Name: "vaadd.vx", OpcodeMask: 4227887231, Opcode: 604004439, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 604004439, Generator: nil}, + {Name: "vaaddu.vv", OpcodeMask: 4227887231, Opcode: 536879191, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 536879191, Generator: nil}, + {Name: "vaaddu.vx", OpcodeMask: 4227887231, Opcode: 536895575, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 536895575, Generator: nil}, + {Name: "vadc.vim", OpcodeMask: 4261441663, Opcode: 1073754199, Fields: []InsnField{ + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1073754199, Generator: nil}, + {Name: "vadc.vvm", OpcodeMask: 4261441663, Opcode: 1073741911, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1073741911, Generator: nil}, + {Name: "vadc.vxm", OpcodeMask: 4261441663, Opcode: 1073758295, Fields: []InsnField{ + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1073758295, Generator: nil}, + {Name: "vadd.vi", OpcodeMask: 4227887231, Opcode: 12375, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 12375, Generator: nil}, + {Name: "vadd.vv", OpcodeMask: 4227887231, Opcode: 87, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 87, Generator: nil}, + {Name: "vadd.vx", OpcodeMask: 4227887231, Opcode: 16471, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 16471, Generator: nil}, + {Name: "vand.vi", OpcodeMask: 4227887231, Opcode: 603992151, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 603992151, Generator: nil}, + {Name: "vand.vv", OpcodeMask: 4227887231, Opcode: 603979863, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 603979863, Generator: nil}, + {Name: "vand.vx", OpcodeMask: 4227887231, Opcode: 603996247, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 603996247, Generator: nil}, + {Name: "vasub.vv", OpcodeMask: 4227887231, Opcode: 738205783, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 738205783, Generator: nil}, + {Name: "vasub.vx", OpcodeMask: 4227887231, Opcode: 738222167, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 738222167, Generator: nil}, + {Name: "vasubu.vv", OpcodeMask: 4227887231, Opcode: 671096919, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671096919, Generator: nil}, + {Name: "vasubu.vx", OpcodeMask: 4227887231, Opcode: 671113303, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671113303, Generator: nil}, + {Name: "vcompress.vm", OpcodeMask: 4261441663, Opcode: 1577066583, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1577066583, Generator: nil}, + {Name: "vcpop.m", OpcodeMask: 4228903039, Opcode: 1074274391, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1074274391, Generator: nil}, + {Name: "vdiv.vv", OpcodeMask: 4227887231, Opcode: 2214600791, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2214600791, Generator: nil}, + {Name: "vdiv.vx", OpcodeMask: 4227887231, Opcode: 2214617175, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2214617175, Generator: nil}, + {Name: "vdivu.vv", OpcodeMask: 4227887231, Opcode: 2147491927, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147491927, Generator: nil}, + {Name: "vdivu.vx", OpcodeMask: 4227887231, Opcode: 2147508311, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147508311, Generator: nil}, + {Name: "vfadd.vf", OpcodeMask: 4227887231, Opcode: 20567, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 20567, Generator: nil}, + {Name: "vfadd.vv", OpcodeMask: 4227887231, Opcode: 4183, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4183, Generator: nil}, + {Name: "vfclass.v", OpcodeMask: 4228903039, Opcode: 1275596887, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1275596887, Generator: nil}, + {Name: "vfcvt.f.x.v", OpcodeMask: 4228903039, Opcode: 1208062039, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208062039, Generator: nil}, + {Name: "vfcvt.f.xu.v", OpcodeMask: 4228903039, Opcode: 1208029271, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208029271, Generator: nil}, + {Name: "vfcvt.rtz.x.f.v", OpcodeMask: 4228903039, Opcode: 1208193111, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208193111, Generator: nil}, + {Name: "vfcvt.rtz.xu.f.v", OpcodeMask: 4228903039, Opcode: 1208160343, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208160343, Generator: nil}, + {Name: "vfcvt.x.f.v", OpcodeMask: 4228903039, Opcode: 1207996503, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1207996503, Generator: nil}, + {Name: "vfcvt.xu.f.v", OpcodeMask: 4228903039, Opcode: 1207963735, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1207963735, Generator: nil}, + {Name: "vfdiv.vf", OpcodeMask: 4227887231, Opcode: 2147504215, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147504215, Generator: nil}, + {Name: "vfdiv.vv", OpcodeMask: 4227887231, Opcode: 2147487831, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147487831, Generator: nil}, + {Name: "vfirst.m", OpcodeMask: 4228903039, Opcode: 1074307159, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1074307159, Generator: nil}, + {Name: "vfmacc.vf", OpcodeMask: 4227887231, Opcode: 2952810583, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2952810583, Generator: nil}, + {Name: "vfmacc.vv", OpcodeMask: 4227887231, Opcode: 2952794199, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2952794199, Generator: nil}, + {Name: "vfmadd.vf", OpcodeMask: 4227887231, Opcode: 2684375127, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2684375127, Generator: nil}, + {Name: "vfmadd.vv", OpcodeMask: 4227887231, Opcode: 2684358743, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2684358743, Generator: nil}, + {Name: "vfmax.vf", OpcodeMask: 4227887231, Opcode: 402673751, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 402673751, Generator: nil}, + {Name: "vfmax.vv", OpcodeMask: 4227887231, Opcode: 402657367, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 402657367, Generator: nil}, + {Name: "vfmerge.vfm", OpcodeMask: 4261441663, Opcode: 1543524439, Fields: []InsnField{ + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1543524439, Generator: nil}, + {Name: "vfmin.vf", OpcodeMask: 4227887231, Opcode: 268456023, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 268456023, Generator: nil}, + {Name: "vfmin.vv", OpcodeMask: 4227887231, Opcode: 268439639, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 268439639, Generator: nil}, + {Name: "vfmsac.vf", OpcodeMask: 4227887231, Opcode: 3087028311, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3087028311, Generator: nil}, + {Name: "vfmsac.vv", OpcodeMask: 4227887231, Opcode: 3087011927, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3087011927, Generator: nil}, + {Name: "vfmsub.vf", OpcodeMask: 4227887231, Opcode: 2818592855, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2818592855, Generator: nil}, + {Name: "vfmsub.vv", OpcodeMask: 4227887231, Opcode: 2818576471, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2818576471, Generator: nil}, + {Name: "vfmul.vf", OpcodeMask: 4227887231, Opcode: 2415939671, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2415939671, Generator: nil}, + {Name: "vfmul.vv", OpcodeMask: 4227887231, Opcode: 2415923287, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2415923287, Generator: nil}, + {Name: "vfmv.f.s", OpcodeMask: 4262457471, Opcode: 1107300439, Fields: []InsnField{ + {"vs2", 24, 5}, + {"fd", 11, 5}, + }, AsUInt32: 1107300439, Generator: nil}, + {Name: "vfmv.s.f", OpcodeMask: 4293947519, Opcode: 1107316823, Fields: []InsnField{ + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1107316823, Generator: nil}, + {Name: "vfmv.v.f", OpcodeMask: 4293947519, Opcode: 1577078871, Fields: []InsnField{ + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1577078871, Generator: nil}, + {Name: "vfncvt.f.f.w", OpcodeMask: 4228903039, Opcode: 1208619095, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208619095, Generator: nil}, + {Name: "vfncvt.f.x.w", OpcodeMask: 4228903039, Opcode: 1208586327, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208586327, Generator: nil}, + {Name: "vfncvt.f.xu.w", OpcodeMask: 4228903039, Opcode: 1208553559, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208553559, Generator: nil}, + {Name: "vfncvt.rod.f.f.w", OpcodeMask: 4228903039, Opcode: 1208651863, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208651863, Generator: nil}, + {Name: "vfncvt.rtz.x.f.w", OpcodeMask: 4228903039, Opcode: 1208717399, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208717399, Generator: nil}, + {Name: "vfncvt.rtz.xu.f.w", OpcodeMask: 4228903039, Opcode: 1208684631, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208684631, Generator: nil}, + {Name: "vfncvt.x.f.w", OpcodeMask: 4228903039, Opcode: 1208520791, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208520791, Generator: nil}, + {Name: "vfncvt.xu.f.w", OpcodeMask: 4228903039, Opcode: 1208488023, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208488023, Generator: nil}, + {Name: "vfnmacc.vf", OpcodeMask: 4227887231, Opcode: 3019919447, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3019919447, Generator: nil}, + {Name: "vfnmacc.vv", OpcodeMask: 4227887231, Opcode: 3019903063, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3019903063, Generator: nil}, + {Name: "vfnmadd.vf", OpcodeMask: 4227887231, Opcode: 2751483991, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751483991, Generator: nil}, + {Name: "vfnmadd.vv", OpcodeMask: 4227887231, Opcode: 2751467607, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751467607, Generator: nil}, + {Name: "vfnmsac.vf", OpcodeMask: 4227887231, Opcode: 3154137175, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3154137175, Generator: nil}, + {Name: "vfnmsac.vv", OpcodeMask: 4227887231, Opcode: 3154120791, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3154120791, Generator: nil}, + {Name: "vfnmsub.vf", OpcodeMask: 4227887231, Opcode: 2885701719, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885701719, Generator: nil}, + {Name: "vfnmsub.vv", OpcodeMask: 4227887231, Opcode: 2885685335, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885685335, Generator: nil}, + {Name: "vfrdiv.vf", OpcodeMask: 4227887231, Opcode: 2214613079, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2214613079, Generator: nil}, + {Name: "vfrec7.v", OpcodeMask: 4228903039, Opcode: 1275236439, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1275236439, Generator: nil}, + {Name: "vfredmax.vs", OpcodeMask: 4227887231, Opcode: 469766231, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 469766231, Generator: nil}, + {Name: "vfredmin.vs", OpcodeMask: 4227887231, Opcode: 335548503, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 335548503, Generator: nil}, + {Name: "vfredosum.vs", OpcodeMask: 4227887231, Opcode: 201330775, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 201330775, Generator: nil}, + {Name: "vfredusum.vs", OpcodeMask: 4227887231, Opcode: 67113047, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 67113047, Generator: nil}, + {Name: "vfrsqrt7.v", OpcodeMask: 4228903039, Opcode: 1275203671, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1275203671, Generator: nil}, + {Name: "vfrsub.vf", OpcodeMask: 4227887231, Opcode: 2617266263, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2617266263, Generator: nil}, + {Name: "vfsgnj.vf", OpcodeMask: 4227887231, Opcode: 536891479, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 536891479, Generator: nil}, + {Name: "vfsgnj.vv", OpcodeMask: 4227887231, Opcode: 536875095, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 536875095, Generator: nil}, + {Name: "vfsgnjn.vf", OpcodeMask: 4227887231, Opcode: 604000343, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 604000343, Generator: nil}, + {Name: "vfsgnjn.vv", OpcodeMask: 4227887231, Opcode: 603983959, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 603983959, Generator: nil}, + {Name: "vfsgnjx.vf", OpcodeMask: 4227887231, Opcode: 671109207, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671109207, Generator: nil}, + {Name: "vfsgnjx.vv", OpcodeMask: 4227887231, Opcode: 671092823, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671092823, Generator: nil}, + {Name: "vfslide1down.vf", OpcodeMask: 4227887231, Opcode: 1006653527, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1006653527, Generator: nil}, + {Name: "vfslide1up.vf", OpcodeMask: 4227887231, Opcode: 939544663, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 939544663, Generator: nil}, + {Name: "vfsqrt.v", OpcodeMask: 4228903039, Opcode: 1275072599, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1275072599, Generator: nil}, + {Name: "vfsub.vf", OpcodeMask: 4227887231, Opcode: 134238295, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 134238295, Generator: nil}, + {Name: "vfsub.vv", OpcodeMask: 4227887231, Opcode: 134221911, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 134221911, Generator: nil}, + {Name: "vfwadd.vf", OpcodeMask: 4227887231, Opcode: 3221246039, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3221246039, Generator: nil}, + {Name: "vfwadd.vv", OpcodeMask: 4227887231, Opcode: 3221229655, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3221229655, Generator: nil}, + {Name: "vfwadd.wf", OpcodeMask: 4227887231, Opcode: 3489681495, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3489681495, Generator: nil}, + {Name: "vfwadd.wv", OpcodeMask: 4227887231, Opcode: 3489665111, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3489665111, Generator: nil}, + {Name: "vfwcvt.f.f.v", OpcodeMask: 4228903039, Opcode: 1208356951, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208356951, Generator: nil}, + {Name: "vfwcvt.f.x.v", OpcodeMask: 4228903039, Opcode: 1208324183, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208324183, Generator: nil}, + {Name: "vfwcvt.f.xu.v", OpcodeMask: 4228903039, Opcode: 1208291415, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208291415, Generator: nil}, + {Name: "vfwcvt.rtz.x.f.v", OpcodeMask: 4228903039, Opcode: 1208455255, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208455255, Generator: nil}, + {Name: "vfwcvt.rtz.xu.f.v", OpcodeMask: 4228903039, Opcode: 1208422487, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208422487, Generator: nil}, + {Name: "vfwcvt.x.f.v", OpcodeMask: 4228903039, Opcode: 1208258647, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208258647, Generator: nil}, + {Name: "vfwcvt.xu.f.v", OpcodeMask: 4228903039, Opcode: 1208225879, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208225879, Generator: nil}, + {Name: "vfwmacc.vf", OpcodeMask: 4227887231, Opcode: 4026552407, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4026552407, Generator: nil}, + {Name: "vfwmacc.vv", OpcodeMask: 4227887231, Opcode: 4026536023, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4026536023, Generator: nil}, + {Name: "vfwmsac.vf", OpcodeMask: 4227887231, Opcode: 4160770135, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4160770135, Generator: nil}, + {Name: "vfwmsac.vv", OpcodeMask: 4227887231, Opcode: 4160753751, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4160753751, Generator: nil}, + {Name: "vfwmul.vf", OpcodeMask: 4227887231, Opcode: 3758116951, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3758116951, Generator: nil}, + {Name: "vfwmul.vv", OpcodeMask: 4227887231, Opcode: 3758100567, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3758100567, Generator: nil}, + {Name: "vfwnmacc.vf", OpcodeMask: 4227887231, Opcode: 4093661271, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4093661271, Generator: nil}, + {Name: "vfwnmacc.vv", OpcodeMask: 4227887231, Opcode: 4093644887, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4093644887, Generator: nil}, + {Name: "vfwnmsac.vf", OpcodeMask: 4227887231, Opcode: 4227878999, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4227878999, Generator: nil}, + {Name: "vfwnmsac.vv", OpcodeMask: 4227887231, Opcode: 4227862615, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4227862615, Generator: nil}, + {Name: "vfwredosum.vs", OpcodeMask: 4227887231, Opcode: 3422556247, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3422556247, Generator: nil}, + {Name: "vfwredusum.vs", OpcodeMask: 4227887231, Opcode: 3288338519, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3288338519, Generator: nil}, + {Name: "vfwsub.vf", OpcodeMask: 4227887231, Opcode: 3355463767, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3355463767, Generator: nil}, + {Name: "vfwsub.vv", OpcodeMask: 4227887231, Opcode: 3355447383, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3355447383, Generator: nil}, + {Name: "vfwsub.wf", OpcodeMask: 4227887231, Opcode: 3623899223, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3623899223, Generator: nil}, + {Name: "vfwsub.wv", OpcodeMask: 4227887231, Opcode: 3623882839, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3623882839, Generator: nil}, + {Name: "vid.v", OpcodeMask: 4261408895, Opcode: 1342742615, Fields: []InsnField{ + {"vm", 25, 1}, + {"vd", 11, 5}, + }, AsUInt32: 1342742615, Generator: nil}, + {Name: "viota.m", OpcodeMask: 4228903039, Opcode: 1342709847, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1342709847, Generator: nil}, + {Name: "vl1re16.v", OpcodeMask: 4293947519, Opcode: 41963527, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 41963527, Generator: nil}, + {Name: "vl1re32.v", OpcodeMask: 4293947519, Opcode: 41967623, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 41967623, Generator: nil}, + {Name: "vl1re64.v", OpcodeMask: 4293947519, Opcode: 41971719, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 41971719, Generator: nil}, + {Name: "vl1re8.v", OpcodeMask: 4293947519, Opcode: 41943047, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 41943047, Generator: nil}, + {Name: "vl2re16.v", OpcodeMask: 4293947519, Opcode: 578834439, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 578834439, Generator: nil}, + {Name: "vl2re32.v", OpcodeMask: 4293947519, Opcode: 578838535, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 578838535, Generator: nil}, + {Name: "vl2re64.v", OpcodeMask: 4293947519, Opcode: 578842631, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 578842631, Generator: nil}, + {Name: "vl2re8.v", OpcodeMask: 4293947519, Opcode: 578813959, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 578813959, Generator: nil}, + {Name: "vl4re16.v", OpcodeMask: 4293947519, Opcode: 1652576263, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1652576263, Generator: nil}, + {Name: "vl4re32.v", OpcodeMask: 4293947519, Opcode: 1652580359, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1652580359, Generator: nil}, + {Name: "vl4re64.v", OpcodeMask: 4293947519, Opcode: 1652584455, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1652584455, Generator: nil}, + {Name: "vl4re8.v", OpcodeMask: 4293947519, Opcode: 1652555783, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1652555783, Generator: nil}, + {Name: "vl8re16.v", OpcodeMask: 4293947519, Opcode: 3800059911, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3800059911, Generator: nil}, + {Name: "vl8re32.v", OpcodeMask: 4293947519, Opcode: 3800064007, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3800064007, Generator: nil}, + {Name: "vl8re64.v", OpcodeMask: 4293947519, Opcode: 3800068103, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3800068103, Generator: nil}, + {Name: "vl8re8.v", OpcodeMask: 4293947519, Opcode: 3800039431, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3800039431, Generator: nil}, + {Name: "vle16.v", OpcodeMask: 4260393087, Opcode: 20487, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 20487, Generator: nil}, + {Name: "vle16ff.v", OpcodeMask: 4260393087, Opcode: 16797703, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 16797703, Generator: nil}, + {Name: "vle32.v", OpcodeMask: 4260393087, Opcode: 24583, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 24583, Generator: nil}, + {Name: "vle32ff.v", OpcodeMask: 4260393087, Opcode: 16801799, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 16801799, Generator: nil}, + {Name: "vle64.v", OpcodeMask: 4260393087, Opcode: 28679, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 28679, Generator: nil}, + {Name: "vle64ff.v", OpcodeMask: 4260393087, Opcode: 16805895, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 16805895, Generator: nil}, + {Name: "vle8.v", OpcodeMask: 4260393087, Opcode: 7, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 7, Generator: nil}, + {Name: "vle8ff.v", OpcodeMask: 4260393087, Opcode: 16777223, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 16777223, Generator: nil}, + {Name: "vlm.v", OpcodeMask: 4293947519, Opcode: 45088775, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 45088775, Generator: nil}, + {Name: "vloxei16.v", OpcodeMask: 4227887231, Opcode: 201347079, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 201347079, Generator: nil}, + {Name: "vloxei32.v", OpcodeMask: 4227887231, Opcode: 201351175, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 201351175, Generator: nil}, + {Name: "vloxei64.v", OpcodeMask: 4227887231, Opcode: 201355271, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 201355271, Generator: nil}, + {Name: "vloxei8.v", OpcodeMask: 4227887231, Opcode: 201326599, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 201326599, Generator: nil}, + {Name: "vloxseg2ei16.v", OpcodeMask: 4227887231, Opcode: 738217991, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 738217991, Generator: nil}, + {Name: "vloxseg2ei32.v", OpcodeMask: 4227887231, Opcode: 738222087, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 738222087, Generator: nil}, + {Name: "vloxseg2ei64.v", OpcodeMask: 4227887231, Opcode: 738226183, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 738226183, Generator: nil}, + {Name: "vloxseg2ei8.v", OpcodeMask: 4227887231, Opcode: 738197511, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 738197511, Generator: nil}, + {Name: "vloxseg3ei16.v", OpcodeMask: 4227887231, Opcode: 1275088903, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1275088903, Generator: nil}, + {Name: "vloxseg3ei32.v", OpcodeMask: 4227887231, Opcode: 1275092999, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1275092999, Generator: nil}, + {Name: "vloxseg3ei64.v", OpcodeMask: 4227887231, Opcode: 1275097095, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1275097095, Generator: nil}, + {Name: "vloxseg3ei8.v", OpcodeMask: 4227887231, Opcode: 1275068423, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1275068423, Generator: nil}, + {Name: "vloxseg4ei16.v", OpcodeMask: 4227887231, Opcode: 1811959815, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1811959815, Generator: nil}, + {Name: "vloxseg4ei32.v", OpcodeMask: 4227887231, Opcode: 1811963911, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1811963911, Generator: nil}, + {Name: "vloxseg4ei64.v", OpcodeMask: 4227887231, Opcode: 1811968007, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1811968007, Generator: nil}, + {Name: "vloxseg4ei8.v", OpcodeMask: 4227887231, Opcode: 1811939335, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1811939335, Generator: nil}, + {Name: "vloxseg5ei16.v", OpcodeMask: 4227887231, Opcode: 2348830727, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2348830727, Generator: nil}, + {Name: "vloxseg5ei32.v", OpcodeMask: 4227887231, Opcode: 2348834823, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2348834823, Generator: nil}, + {Name: "vloxseg5ei64.v", OpcodeMask: 4227887231, Opcode: 2348838919, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2348838919, Generator: nil}, + {Name: "vloxseg5ei8.v", OpcodeMask: 4227887231, Opcode: 2348810247, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2348810247, Generator: nil}, + {Name: "vloxseg6ei16.v", OpcodeMask: 4227887231, Opcode: 2885701639, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885701639, Generator: nil}, + {Name: "vloxseg6ei32.v", OpcodeMask: 4227887231, Opcode: 2885705735, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885705735, Generator: nil}, + {Name: "vloxseg6ei64.v", OpcodeMask: 4227887231, Opcode: 2885709831, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885709831, Generator: nil}, + {Name: "vloxseg6ei8.v", OpcodeMask: 4227887231, Opcode: 2885681159, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885681159, Generator: nil}, + {Name: "vloxseg7ei16.v", OpcodeMask: 4227887231, Opcode: 3422572551, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3422572551, Generator: nil}, + {Name: "vloxseg7ei32.v", OpcodeMask: 4227887231, Opcode: 3422576647, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3422576647, Generator: nil}, + {Name: "vloxseg7ei64.v", OpcodeMask: 4227887231, Opcode: 3422580743, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3422580743, Generator: nil}, + {Name: "vloxseg7ei8.v", OpcodeMask: 4227887231, Opcode: 3422552071, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3422552071, Generator: nil}, + {Name: "vloxseg8ei16.v", OpcodeMask: 4227887231, Opcode: 3959443463, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3959443463, Generator: nil}, + {Name: "vloxseg8ei32.v", OpcodeMask: 4227887231, Opcode: 3959447559, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3959447559, Generator: nil}, + {Name: "vloxseg8ei64.v", OpcodeMask: 4227887231, Opcode: 3959451655, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3959451655, Generator: nil}, + {Name: "vloxseg8ei8.v", OpcodeMask: 4227887231, Opcode: 3959422983, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3959422983, Generator: nil}, + {Name: "vlse16.v", OpcodeMask: 4227887231, Opcode: 134238215, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 134238215, Generator: nil}, + {Name: "vlse32.v", OpcodeMask: 4227887231, Opcode: 134242311, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 134242311, Generator: nil}, + {Name: "vlse64.v", OpcodeMask: 4227887231, Opcode: 134246407, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 134246407, Generator: nil}, + {Name: "vlse8.v", OpcodeMask: 4227887231, Opcode: 134217735, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 134217735, Generator: nil}, + {Name: "vlseg2e16.v", OpcodeMask: 4260393087, Opcode: 536891399, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 536891399, Generator: nil}, + {Name: "vlseg2e16ff.v", OpcodeMask: 4260393087, Opcode: 553668615, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 553668615, Generator: nil}, + {Name: "vlseg2e32.v", OpcodeMask: 4260393087, Opcode: 536895495, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 536895495, Generator: nil}, + {Name: "vlseg2e32ff.v", OpcodeMask: 4260393087, Opcode: 553672711, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 553672711, Generator: nil}, + {Name: "vlseg2e64.v", OpcodeMask: 4260393087, Opcode: 536899591, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 536899591, Generator: nil}, + {Name: "vlseg2e64ff.v", OpcodeMask: 4260393087, Opcode: 553676807, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 553676807, Generator: nil}, + {Name: "vlseg2e8.v", OpcodeMask: 4260393087, Opcode: 536870919, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 536870919, Generator: nil}, + {Name: "vlseg2e8ff.v", OpcodeMask: 4260393087, Opcode: 553648135, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 553648135, Generator: nil}, + {Name: "vlseg3e16.v", OpcodeMask: 4260393087, Opcode: 1073762311, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1073762311, Generator: nil}, + {Name: "vlseg3e16ff.v", OpcodeMask: 4260393087, Opcode: 1090539527, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1090539527, Generator: nil}, + {Name: "vlseg3e32.v", OpcodeMask: 4260393087, Opcode: 1073766407, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1073766407, Generator: nil}, + {Name: "vlseg3e32ff.v", OpcodeMask: 4260393087, Opcode: 1090543623, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1090543623, Generator: nil}, + {Name: "vlseg3e64.v", OpcodeMask: 4260393087, Opcode: 1073770503, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1073770503, Generator: nil}, + {Name: "vlseg3e64ff.v", OpcodeMask: 4260393087, Opcode: 1090547719, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1090547719, Generator: nil}, + {Name: "vlseg3e8.v", OpcodeMask: 4260393087, Opcode: 1073741831, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1073741831, Generator: nil}, + {Name: "vlseg3e8ff.v", OpcodeMask: 4260393087, Opcode: 1090519047, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1090519047, Generator: nil}, + {Name: "vlseg4e16.v", OpcodeMask: 4260393087, Opcode: 1610633223, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1610633223, Generator: nil}, + {Name: "vlseg4e16ff.v", OpcodeMask: 4260393087, Opcode: 1627410439, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1627410439, Generator: nil}, + {Name: "vlseg4e32.v", OpcodeMask: 4260393087, Opcode: 1610637319, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1610637319, Generator: nil}, + {Name: "vlseg4e32ff.v", OpcodeMask: 4260393087, Opcode: 1627414535, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1627414535, Generator: nil}, + {Name: "vlseg4e64.v", OpcodeMask: 4260393087, Opcode: 1610641415, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1610641415, Generator: nil}, + {Name: "vlseg4e64ff.v", OpcodeMask: 4260393087, Opcode: 1627418631, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1627418631, Generator: nil}, + {Name: "vlseg4e8.v", OpcodeMask: 4260393087, Opcode: 1610612743, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1610612743, Generator: nil}, + {Name: "vlseg4e8ff.v", OpcodeMask: 4260393087, Opcode: 1627389959, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1627389959, Generator: nil}, + {Name: "vlseg5e16.v", OpcodeMask: 4260393087, Opcode: 2147504135, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147504135, Generator: nil}, + {Name: "vlseg5e16ff.v", OpcodeMask: 4260393087, Opcode: 2164281351, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2164281351, Generator: nil}, + {Name: "vlseg5e32.v", OpcodeMask: 4260393087, Opcode: 2147508231, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147508231, Generator: nil}, + {Name: "vlseg5e32ff.v", OpcodeMask: 4260393087, Opcode: 2164285447, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2164285447, Generator: nil}, + {Name: "vlseg5e64.v", OpcodeMask: 4260393087, Opcode: 2147512327, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147512327, Generator: nil}, + {Name: "vlseg5e64ff.v", OpcodeMask: 4260393087, Opcode: 2164289543, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2164289543, Generator: nil}, + {Name: "vlseg5e8.v", OpcodeMask: 4260393087, Opcode: 2147483655, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147483655, Generator: nil}, + {Name: "vlseg5e8ff.v", OpcodeMask: 4260393087, Opcode: 2164260871, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2164260871, Generator: nil}, + {Name: "vlseg6e16.v", OpcodeMask: 4260393087, Opcode: 2684375047, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2684375047, Generator: nil}, + {Name: "vlseg6e16ff.v", OpcodeMask: 4260393087, Opcode: 2701152263, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2701152263, Generator: nil}, + {Name: "vlseg6e32.v", OpcodeMask: 4260393087, Opcode: 2684379143, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2684379143, Generator: nil}, + {Name: "vlseg6e32ff.v", OpcodeMask: 4260393087, Opcode: 2701156359, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2701156359, Generator: nil}, + {Name: "vlseg6e64.v", OpcodeMask: 4260393087, Opcode: 2684383239, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2684383239, Generator: nil}, + {Name: "vlseg6e64ff.v", OpcodeMask: 4260393087, Opcode: 2701160455, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2701160455, Generator: nil}, + {Name: "vlseg6e8.v", OpcodeMask: 4260393087, Opcode: 2684354567, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2684354567, Generator: nil}, + {Name: "vlseg6e8ff.v", OpcodeMask: 4260393087, Opcode: 2701131783, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2701131783, Generator: nil}, + {Name: "vlseg7e16.v", OpcodeMask: 4260393087, Opcode: 3221245959, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3221245959, Generator: nil}, + {Name: "vlseg7e16ff.v", OpcodeMask: 4260393087, Opcode: 3238023175, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3238023175, Generator: nil}, + {Name: "vlseg7e32.v", OpcodeMask: 4260393087, Opcode: 3221250055, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3221250055, Generator: nil}, + {Name: "vlseg7e32ff.v", OpcodeMask: 4260393087, Opcode: 3238027271, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3238027271, Generator: nil}, + {Name: "vlseg7e64.v", OpcodeMask: 4260393087, Opcode: 3221254151, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3221254151, Generator: nil}, + {Name: "vlseg7e64ff.v", OpcodeMask: 4260393087, Opcode: 3238031367, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3238031367, Generator: nil}, + {Name: "vlseg7e8.v", OpcodeMask: 4260393087, Opcode: 3221225479, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3221225479, Generator: nil}, + {Name: "vlseg7e8ff.v", OpcodeMask: 4260393087, Opcode: 3238002695, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3238002695, Generator: nil}, + {Name: "vlseg8e16.v", OpcodeMask: 4260393087, Opcode: 3758116871, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3758116871, Generator: nil}, + {Name: "vlseg8e16ff.v", OpcodeMask: 4260393087, Opcode: 3774894087, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3774894087, Generator: nil}, + {Name: "vlseg8e32.v", OpcodeMask: 4260393087, Opcode: 3758120967, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3758120967, Generator: nil}, + {Name: "vlseg8e32ff.v", OpcodeMask: 4260393087, Opcode: 3774898183, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3774898183, Generator: nil}, + {Name: "vlseg8e64.v", OpcodeMask: 4260393087, Opcode: 3758125063, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3758125063, Generator: nil}, + {Name: "vlseg8e64ff.v", OpcodeMask: 4260393087, Opcode: 3774902279, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3774902279, Generator: nil}, + {Name: "vlseg8e8.v", OpcodeMask: 4260393087, Opcode: 3758096391, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3758096391, Generator: nil}, + {Name: "vlseg8e8ff.v", OpcodeMask: 4260393087, Opcode: 3774873607, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3774873607, Generator: nil}, + {Name: "vlsseg2e16.v", OpcodeMask: 4227887231, Opcode: 671109127, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671109127, Generator: nil}, + {Name: "vlsseg2e32.v", OpcodeMask: 4227887231, Opcode: 671113223, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671113223, Generator: nil}, + {Name: "vlsseg2e64.v", OpcodeMask: 4227887231, Opcode: 671117319, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671117319, Generator: nil}, + {Name: "vlsseg2e8.v", OpcodeMask: 4227887231, Opcode: 671088647, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671088647, Generator: nil}, + {Name: "vlsseg3e16.v", OpcodeMask: 4227887231, Opcode: 1207980039, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1207980039, Generator: nil}, + {Name: "vlsseg3e32.v", OpcodeMask: 4227887231, Opcode: 1207984135, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1207984135, Generator: nil}, + {Name: "vlsseg3e64.v", OpcodeMask: 4227887231, Opcode: 1207988231, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1207988231, Generator: nil}, + {Name: "vlsseg3e8.v", OpcodeMask: 4227887231, Opcode: 1207959559, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1207959559, Generator: nil}, + {Name: "vlsseg4e16.v", OpcodeMask: 4227887231, Opcode: 1744850951, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1744850951, Generator: nil}, + {Name: "vlsseg4e32.v", OpcodeMask: 4227887231, Opcode: 1744855047, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1744855047, Generator: nil}, + {Name: "vlsseg4e64.v", OpcodeMask: 4227887231, Opcode: 1744859143, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1744859143, Generator: nil}, + {Name: "vlsseg4e8.v", OpcodeMask: 4227887231, Opcode: 1744830471, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1744830471, Generator: nil}, + {Name: "vlsseg5e16.v", OpcodeMask: 4227887231, Opcode: 2281721863, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2281721863, Generator: nil}, + {Name: "vlsseg5e32.v", OpcodeMask: 4227887231, Opcode: 2281725959, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2281725959, Generator: nil}, + {Name: "vlsseg5e64.v", OpcodeMask: 4227887231, Opcode: 2281730055, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2281730055, Generator: nil}, + {Name: "vlsseg5e8.v", OpcodeMask: 4227887231, Opcode: 2281701383, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2281701383, Generator: nil}, + {Name: "vlsseg6e16.v", OpcodeMask: 4227887231, Opcode: 2818592775, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2818592775, Generator: nil}, + {Name: "vlsseg6e32.v", OpcodeMask: 4227887231, Opcode: 2818596871, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2818596871, Generator: nil}, + {Name: "vlsseg6e64.v", OpcodeMask: 4227887231, Opcode: 2818600967, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2818600967, Generator: nil}, + {Name: "vlsseg6e8.v", OpcodeMask: 4227887231, Opcode: 2818572295, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2818572295, Generator: nil}, + {Name: "vlsseg7e16.v", OpcodeMask: 4227887231, Opcode: 3355463687, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3355463687, Generator: nil}, + {Name: "vlsseg7e32.v", OpcodeMask: 4227887231, Opcode: 3355467783, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3355467783, Generator: nil}, + {Name: "vlsseg7e64.v", OpcodeMask: 4227887231, Opcode: 3355471879, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3355471879, Generator: nil}, + {Name: "vlsseg7e8.v", OpcodeMask: 4227887231, Opcode: 3355443207, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3355443207, Generator: nil}, + {Name: "vlsseg8e16.v", OpcodeMask: 4227887231, Opcode: 3892334599, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3892334599, Generator: nil}, + {Name: "vlsseg8e32.v", OpcodeMask: 4227887231, Opcode: 3892338695, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3892338695, Generator: nil}, + {Name: "vlsseg8e64.v", OpcodeMask: 4227887231, Opcode: 3892342791, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3892342791, Generator: nil}, + {Name: "vlsseg8e8.v", OpcodeMask: 4227887231, Opcode: 3892314119, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3892314119, Generator: nil}, + {Name: "vluxei16.v", OpcodeMask: 4227887231, Opcode: 67129351, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 67129351, Generator: nil}, + {Name: "vluxei32.v", OpcodeMask: 4227887231, Opcode: 67133447, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 67133447, Generator: nil}, + {Name: "vluxei64.v", OpcodeMask: 4227887231, Opcode: 67137543, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 67137543, Generator: nil}, + {Name: "vluxei8.v", OpcodeMask: 4227887231, Opcode: 67108871, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 67108871, Generator: nil}, + {Name: "vluxseg2ei16.v", OpcodeMask: 4227887231, Opcode: 604000263, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 604000263, Generator: nil}, + {Name: "vluxseg2ei32.v", OpcodeMask: 4227887231, Opcode: 604004359, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 604004359, Generator: nil}, + {Name: "vluxseg2ei64.v", OpcodeMask: 4227887231, Opcode: 604008455, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 604008455, Generator: nil}, + {Name: "vluxseg2ei8.v", OpcodeMask: 4227887231, Opcode: 603979783, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 603979783, Generator: nil}, + {Name: "vluxseg3ei16.v", OpcodeMask: 4227887231, Opcode: 1140871175, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1140871175, Generator: nil}, + {Name: "vluxseg3ei32.v", OpcodeMask: 4227887231, Opcode: 1140875271, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1140875271, Generator: nil}, + {Name: "vluxseg3ei64.v", OpcodeMask: 4227887231, Opcode: 1140879367, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1140879367, Generator: nil}, + {Name: "vluxseg3ei8.v", OpcodeMask: 4227887231, Opcode: 1140850695, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1140850695, Generator: nil}, + {Name: "vluxseg4ei16.v", OpcodeMask: 4227887231, Opcode: 1677742087, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1677742087, Generator: nil}, + {Name: "vluxseg4ei32.v", OpcodeMask: 4227887231, Opcode: 1677746183, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1677746183, Generator: nil}, + {Name: "vluxseg4ei64.v", OpcodeMask: 4227887231, Opcode: 1677750279, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1677750279, Generator: nil}, + {Name: "vluxseg4ei8.v", OpcodeMask: 4227887231, Opcode: 1677721607, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1677721607, Generator: nil}, + {Name: "vluxseg5ei16.v", OpcodeMask: 4227887231, Opcode: 2214612999, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2214612999, Generator: nil}, + {Name: "vluxseg5ei32.v", OpcodeMask: 4227887231, Opcode: 2214617095, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2214617095, Generator: nil}, + {Name: "vluxseg5ei64.v", OpcodeMask: 4227887231, Opcode: 2214621191, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2214621191, Generator: nil}, + {Name: "vluxseg5ei8.v", OpcodeMask: 4227887231, Opcode: 2214592519, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2214592519, Generator: nil}, + {Name: "vluxseg6ei16.v", OpcodeMask: 4227887231, Opcode: 2751483911, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751483911, Generator: nil}, + {Name: "vluxseg6ei32.v", OpcodeMask: 4227887231, Opcode: 2751488007, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751488007, Generator: nil}, + {Name: "vluxseg6ei64.v", OpcodeMask: 4227887231, Opcode: 2751492103, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751492103, Generator: nil}, + {Name: "vluxseg6ei8.v", OpcodeMask: 4227887231, Opcode: 2751463431, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751463431, Generator: nil}, + {Name: "vluxseg7ei16.v", OpcodeMask: 4227887231, Opcode: 3288354823, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3288354823, Generator: nil}, + {Name: "vluxseg7ei32.v", OpcodeMask: 4227887231, Opcode: 3288358919, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3288358919, Generator: nil}, + {Name: "vluxseg7ei64.v", OpcodeMask: 4227887231, Opcode: 3288363015, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3288363015, Generator: nil}, + {Name: "vluxseg7ei8.v", OpcodeMask: 4227887231, Opcode: 3288334343, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3288334343, Generator: nil}, + {Name: "vluxseg8ei16.v", OpcodeMask: 4227887231, Opcode: 3825225735, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3825225735, Generator: nil}, + {Name: "vluxseg8ei32.v", OpcodeMask: 4227887231, Opcode: 3825229831, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3825229831, Generator: nil}, + {Name: "vluxseg8ei64.v", OpcodeMask: 4227887231, Opcode: 3825233927, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3825233927, Generator: nil}, + {Name: "vluxseg8ei8.v", OpcodeMask: 4227887231, Opcode: 3825205255, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3825205255, Generator: nil}, + {Name: "vmacc.vv", OpcodeMask: 4227887231, Opcode: 3019907159, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3019907159, Generator: nil}, + {Name: "vmacc.vx", OpcodeMask: 4227887231, Opcode: 3019923543, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3019923543, Generator: nil}, + {Name: "vmadc.vi", OpcodeMask: 4261441663, Opcode: 1174417495, Fields: []InsnField{ + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1174417495, Generator: nil}, + {Name: "vmadc.vim", OpcodeMask: 4261441663, Opcode: 1140863063, Fields: []InsnField{ + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1140863063, Generator: nil}, + {Name: "vmadc.vv", OpcodeMask: 4261441663, Opcode: 1174405207, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1174405207, Generator: nil}, + {Name: "vmadc.vvm", OpcodeMask: 4261441663, Opcode: 1140850775, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1140850775, Generator: nil}, + {Name: "vmadc.vx", OpcodeMask: 4261441663, Opcode: 1174421591, Fields: []InsnField{ + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1174421591, Generator: nil}, + {Name: "vmadc.vxm", OpcodeMask: 4261441663, Opcode: 1140867159, Fields: []InsnField{ + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1140867159, Generator: nil}, + {Name: "vmadd.vv", OpcodeMask: 4227887231, Opcode: 2751471703, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751471703, Generator: nil}, + {Name: "vmadd.vx", OpcodeMask: 4227887231, Opcode: 2751488087, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751488087, Generator: nil}, + {Name: "vmand.mm", OpcodeMask: 4261441663, Opcode: 1711284311, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1711284311, Generator: nil}, + {Name: "vmandn.mm", OpcodeMask: 4261441663, Opcode: 1644175447, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1644175447, Generator: nil}, + {Name: "vmax.vv", OpcodeMask: 4227887231, Opcode: 469762135, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 469762135, Generator: nil}, + {Name: "vmax.vx", OpcodeMask: 4227887231, Opcode: 469778519, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 469778519, Generator: nil}, + {Name: "vmaxu.vv", OpcodeMask: 4227887231, Opcode: 402653271, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 402653271, Generator: nil}, + {Name: "vmaxu.vx", OpcodeMask: 4227887231, Opcode: 402669655, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 402669655, Generator: nil}, + {Name: "vmerge.vim", OpcodeMask: 4261441663, Opcode: 1543516247, Fields: []InsnField{ + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1543516247, Generator: nil}, + {Name: "vmerge.vvm", OpcodeMask: 4261441663, Opcode: 1543503959, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1543503959, Generator: nil}, + {Name: "vmerge.vxm", OpcodeMask: 4261441663, Opcode: 1543520343, Fields: []InsnField{ + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1543520343, Generator: nil}, + {Name: "vmfeq.vf", OpcodeMask: 4227887231, Opcode: 1610633303, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1610633303, Generator: nil}, + {Name: "vmfeq.vv", OpcodeMask: 4227887231, Opcode: 1610616919, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1610616919, Generator: nil}, + {Name: "vmfge.vf", OpcodeMask: 4227887231, Opcode: 2080395351, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2080395351, Generator: nil}, + {Name: "vmfgt.vf", OpcodeMask: 4227887231, Opcode: 1946177623, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1946177623, Generator: nil}, + {Name: "vmfle.vf", OpcodeMask: 4227887231, Opcode: 1677742167, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1677742167, Generator: nil}, + {Name: "vmfle.vv", OpcodeMask: 4227887231, Opcode: 1677725783, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1677725783, Generator: nil}, + {Name: "vmflt.vf", OpcodeMask: 4227887231, Opcode: 1811959895, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1811959895, Generator: nil}, + {Name: "vmflt.vv", OpcodeMask: 4227887231, Opcode: 1811943511, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1811943511, Generator: nil}, + {Name: "vmfne.vf", OpcodeMask: 4227887231, Opcode: 1879068759, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1879068759, Generator: nil}, + {Name: "vmfne.vv", OpcodeMask: 4227887231, Opcode: 1879052375, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1879052375, Generator: nil}, + {Name: "vmin.vv", OpcodeMask: 4227887231, Opcode: 335544407, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 335544407, Generator: nil}, + {Name: "vmin.vx", OpcodeMask: 4227887231, Opcode: 335560791, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 335560791, Generator: nil}, + {Name: "vminu.vv", OpcodeMask: 4227887231, Opcode: 268435543, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 268435543, Generator: nil}, + {Name: "vminu.vx", OpcodeMask: 4227887231, Opcode: 268451927, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 268451927, Generator: nil}, + {Name: "vmnand.mm", OpcodeMask: 4261441663, Opcode: 1979719767, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1979719767, Generator: nil}, + {Name: "vmnor.mm", OpcodeMask: 4261441663, Opcode: 2046828631, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2046828631, Generator: nil}, + {Name: "vmor.mm", OpcodeMask: 4261441663, Opcode: 1778393175, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1778393175, Generator: nil}, + {Name: "vmorn.mm", OpcodeMask: 4261441663, Opcode: 1912610903, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1912610903, Generator: nil}, + {Name: "vmsbc.vv", OpcodeMask: 4261441663, Opcode: 1308622935, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1308622935, Generator: nil}, + {Name: "vmsbc.vvm", OpcodeMask: 4261441663, Opcode: 1275068503, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1275068503, Generator: nil}, + {Name: "vmsbc.vx", OpcodeMask: 4261441663, Opcode: 1308639319, Fields: []InsnField{ + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1308639319, Generator: nil}, + {Name: "vmsbc.vxm", OpcodeMask: 4261441663, Opcode: 1275084887, Fields: []InsnField{ + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1275084887, Generator: nil}, + {Name: "vmsbf.m", OpcodeMask: 4228903039, Opcode: 1342218327, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1342218327, Generator: nil}, + {Name: "vmseq.vi", OpcodeMask: 4227887231, Opcode: 1610625111, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1610625111, Generator: nil}, + {Name: "vmseq.vv", OpcodeMask: 4227887231, Opcode: 1610612823, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1610612823, Generator: nil}, + {Name: "vmseq.vx", OpcodeMask: 4227887231, Opcode: 1610629207, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1610629207, Generator: nil}, + {Name: "vmsgt.vi", OpcodeMask: 4227887231, Opcode: 2080387159, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2080387159, Generator: nil}, + {Name: "vmsgt.vx", OpcodeMask: 4227887231, Opcode: 2080391255, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2080391255, Generator: nil}, + {Name: "vmsgtu.vi", OpcodeMask: 4227887231, Opcode: 2013278295, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2013278295, Generator: nil}, + {Name: "vmsgtu.vx", OpcodeMask: 4227887231, Opcode: 2013282391, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2013282391, Generator: nil}, + {Name: "vmsif.m", OpcodeMask: 4228903039, Opcode: 1342283863, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1342283863, Generator: nil}, + {Name: "vmsle.vi", OpcodeMask: 4227887231, Opcode: 1946169431, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1946169431, Generator: nil}, + {Name: "vmsle.vv", OpcodeMask: 4227887231, Opcode: 1946157143, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1946157143, Generator: nil}, + {Name: "vmsle.vx", OpcodeMask: 4227887231, Opcode: 1946173527, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1946173527, Generator: nil}, + {Name: "vmsleu.vi", OpcodeMask: 4227887231, Opcode: 1879060567, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1879060567, Generator: nil}, + {Name: "vmsleu.vv", OpcodeMask: 4227887231, Opcode: 1879048279, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1879048279, Generator: nil}, + {Name: "vmsleu.vx", OpcodeMask: 4227887231, Opcode: 1879064663, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1879064663, Generator: nil}, + {Name: "vmslt.vv", OpcodeMask: 4227887231, Opcode: 1811939415, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1811939415, Generator: nil}, + {Name: "vmslt.vx", OpcodeMask: 4227887231, Opcode: 1811955799, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1811955799, Generator: nil}, + {Name: "vmsltu.vv", OpcodeMask: 4227887231, Opcode: 1744830551, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1744830551, Generator: nil}, + {Name: "vmsltu.vx", OpcodeMask: 4227887231, Opcode: 1744846935, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1744846935, Generator: nil}, + {Name: "vmsne.vi", OpcodeMask: 4227887231, Opcode: 1677733975, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1677733975, Generator: nil}, + {Name: "vmsne.vv", OpcodeMask: 4227887231, Opcode: 1677721687, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1677721687, Generator: nil}, + {Name: "vmsne.vx", OpcodeMask: 4227887231, Opcode: 1677738071, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1677738071, Generator: nil}, + {Name: "vmsof.m", OpcodeMask: 4228903039, Opcode: 1342251095, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1342251095, Generator: nil}, + {Name: "vmul.vv", OpcodeMask: 4227887231, Opcode: 2483036247, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2483036247, Generator: nil}, + {Name: "vmul.vx", OpcodeMask: 4227887231, Opcode: 2483052631, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2483052631, Generator: nil}, + {Name: "vmulh.vv", OpcodeMask: 4227887231, Opcode: 2617253975, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2617253975, Generator: nil}, + {Name: "vmulh.vx", OpcodeMask: 4227887231, Opcode: 2617270359, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2617270359, Generator: nil}, + {Name: "vmulhsu.vv", OpcodeMask: 4227887231, Opcode: 2550145111, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2550145111, Generator: nil}, + {Name: "vmulhsu.vx", OpcodeMask: 4227887231, Opcode: 2550161495, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2550161495, Generator: nil}, + {Name: "vmulhu.vv", OpcodeMask: 4227887231, Opcode: 2415927383, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2415927383, Generator: nil}, + {Name: "vmulhu.vx", OpcodeMask: 4227887231, Opcode: 2415943767, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2415943767, Generator: nil}, + {Name: "vmv.s.x", OpcodeMask: 4293947519, Opcode: 1107320919, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1107320919, Generator: nil}, + {Name: "vmv.v.i", OpcodeMask: 4293947519, Opcode: 1577070679, Fields: []InsnField{ + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1577070679, Generator: nil}, + {Name: "vmv.v.v", OpcodeMask: 4293947519, Opcode: 1577058391, Fields: []InsnField{ + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1577058391, Generator: nil}, + {Name: "vmv.v.x", OpcodeMask: 4293947519, Opcode: 1577074775, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1577074775, Generator: nil}, + {Name: "vmv.x.s", OpcodeMask: 4262457471, Opcode: 1107304535, Fields: []InsnField{ + {"vs2", 24, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1107304535, Generator: nil}, + {Name: "vmv1r.v", OpcodeMask: 4262457471, Opcode: 2650812503, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2650812503, Generator: nil}, + {Name: "vmv2r.v", OpcodeMask: 4262457471, Opcode: 2650845271, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2650845271, Generator: nil}, + {Name: "vmv4r.v", OpcodeMask: 4262457471, Opcode: 2650910807, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2650910807, Generator: nil}, + {Name: "vmv8r.v", OpcodeMask: 4262457471, Opcode: 2651041879, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2651041879, Generator: nil}, + {Name: "vmxnor.mm", OpcodeMask: 4261441663, Opcode: 2113937495, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2113937495, Generator: nil}, + {Name: "vmxor.mm", OpcodeMask: 4261441663, Opcode: 1845502039, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1845502039, Generator: nil}, + {Name: "vnclip.wi", OpcodeMask: 4227887231, Opcode: 3154128983, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3154128983, Generator: nil}, + {Name: "vnclip.wv", OpcodeMask: 4227887231, Opcode: 3154116695, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3154116695, Generator: nil}, + {Name: "vnclip.wx", OpcodeMask: 4227887231, Opcode: 3154133079, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3154133079, Generator: nil}, + {Name: "vnclipu.wi", OpcodeMask: 4227887231, Opcode: 3087020119, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3087020119, Generator: nil}, + {Name: "vnclipu.wv", OpcodeMask: 4227887231, Opcode: 3087007831, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3087007831, Generator: nil}, + {Name: "vnclipu.wx", OpcodeMask: 4227887231, Opcode: 3087024215, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3087024215, Generator: nil}, + {Name: "vnmsac.vv", OpcodeMask: 4227887231, Opcode: 3154124887, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3154124887, Generator: nil}, + {Name: "vnmsac.vx", OpcodeMask: 4227887231, Opcode: 3154141271, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3154141271, Generator: nil}, + {Name: "vnmsub.vv", OpcodeMask: 4227887231, Opcode: 2885689431, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885689431, Generator: nil}, + {Name: "vnmsub.vx", OpcodeMask: 4227887231, Opcode: 2885705815, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885705815, Generator: nil}, + {Name: "vnsra.wi", OpcodeMask: 4227887231, Opcode: 3019911255, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3019911255, Generator: nil}, + {Name: "vnsra.wv", OpcodeMask: 4227887231, Opcode: 3019898967, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3019898967, Generator: nil}, + {Name: "vnsra.wx", OpcodeMask: 4227887231, Opcode: 3019915351, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3019915351, Generator: nil}, + {Name: "vnsrl.wi", OpcodeMask: 4227887231, Opcode: 2952802391, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2952802391, Generator: nil}, + {Name: "vnsrl.wv", OpcodeMask: 4227887231, Opcode: 2952790103, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2952790103, Generator: nil}, + {Name: "vnsrl.wx", OpcodeMask: 4227887231, Opcode: 2952806487, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2952806487, Generator: nil}, + {Name: "vor.vi", OpcodeMask: 4227887231, Opcode: 671101015, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671101015, Generator: nil}, + {Name: "vor.vv", OpcodeMask: 4227887231, Opcode: 671088727, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671088727, Generator: nil}, + {Name: "vor.vx", OpcodeMask: 4227887231, Opcode: 671105111, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 671105111, Generator: nil}, + {Name: "vredand.vs", OpcodeMask: 4227887231, Opcode: 67117143, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 67117143, Generator: nil}, + {Name: "vredmax.vs", OpcodeMask: 4227887231, Opcode: 469770327, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 469770327, Generator: nil}, + {Name: "vredmaxu.vs", OpcodeMask: 4227887231, Opcode: 402661463, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 402661463, Generator: nil}, + {Name: "vredmin.vs", OpcodeMask: 4227887231, Opcode: 335552599, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 335552599, Generator: nil}, + {Name: "vredminu.vs", OpcodeMask: 4227887231, Opcode: 268443735, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 268443735, Generator: nil}, + {Name: "vredor.vs", OpcodeMask: 4227887231, Opcode: 134226007, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 134226007, Generator: nil}, + {Name: "vredsum.vs", OpcodeMask: 4227887231, Opcode: 8279, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 8279, Generator: nil}, + {Name: "vredxor.vs", OpcodeMask: 4227887231, Opcode: 201334871, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 201334871, Generator: nil}, + {Name: "vrem.vv", OpcodeMask: 4227887231, Opcode: 2348818519, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2348818519, Generator: nil}, + {Name: "vrem.vx", OpcodeMask: 4227887231, Opcode: 2348834903, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2348834903, Generator: nil}, + {Name: "vremu.vv", OpcodeMask: 4227887231, Opcode: 2281709655, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2281709655, Generator: nil}, + {Name: "vremu.vx", OpcodeMask: 4227887231, Opcode: 2281726039, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2281726039, Generator: nil}, + {Name: "vrgather.vi", OpcodeMask: 4227887231, Opcode: 805318743, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 805318743, Generator: nil}, + {Name: "vrgather.vv", OpcodeMask: 4227887231, Opcode: 805306455, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 805306455, Generator: nil}, + {Name: "vrgather.vx", OpcodeMask: 4227887231, Opcode: 805322839, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 805322839, Generator: nil}, + {Name: "vrgatherei16.vv", OpcodeMask: 4227887231, Opcode: 939524183, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 939524183, Generator: nil}, + {Name: "vrsub.vi", OpcodeMask: 4227887231, Opcode: 201338967, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 201338967, Generator: nil}, + {Name: "vrsub.vx", OpcodeMask: 4227887231, Opcode: 201343063, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 201343063, Generator: nil}, + {Name: "vs1r.v", OpcodeMask: 4293947519, Opcode: 41943079, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 41943079, Generator: nil}, + {Name: "vs2r.v", OpcodeMask: 4293947519, Opcode: 578813991, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 578813991, Generator: nil}, + {Name: "vs4r.v", OpcodeMask: 4293947519, Opcode: 1652555815, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1652555815, Generator: nil}, + {Name: "vs8r.v", OpcodeMask: 4293947519, Opcode: 3800039463, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3800039463, Generator: nil}, + {Name: "vsadd.vi", OpcodeMask: 4227887231, Opcode: 2214604887, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2214604887, Generator: nil}, + {Name: "vsadd.vv", OpcodeMask: 4227887231, Opcode: 2214592599, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2214592599, Generator: nil}, + {Name: "vsadd.vx", OpcodeMask: 4227887231, Opcode: 2214608983, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2214608983, Generator: nil}, + {Name: "vsaddu.vi", OpcodeMask: 4227887231, Opcode: 2147496023, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147496023, Generator: nil}, + {Name: "vsaddu.vv", OpcodeMask: 4227887231, Opcode: 2147483735, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147483735, Generator: nil}, + {Name: "vsaddu.vx", OpcodeMask: 4227887231, Opcode: 2147500119, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2147500119, Generator: nil}, + {Name: "vsbc.vvm", OpcodeMask: 4261441663, Opcode: 1207959639, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1207959639, Generator: nil}, + {Name: "vsbc.vxm", OpcodeMask: 4261441663, Opcode: 1207976023, Fields: []InsnField{ + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1207976023, Generator: nil}, + {Name: "vse16.v", OpcodeMask: 4260393087, Opcode: 20519, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 20519, Generator: nil}, + {Name: "vse32.v", OpcodeMask: 4260393087, Opcode: 24615, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 24615, Generator: nil}, + {Name: "vse64.v", OpcodeMask: 4260393087, Opcode: 28711, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 28711, Generator: nil}, + {Name: "vse8.v", OpcodeMask: 4260393087, Opcode: 39, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 39, Generator: nil}, + {Name: "vsetivli", OpcodeMask: 3221254271, Opcode: 3221254231, Fields: []InsnField{ + {"vtypei", 29, 10}, + {"uimm", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3221254231, Generator: nil}, + {Name: "vsetvl", OpcodeMask: 4261441663, Opcode: 2147512407, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2147512407, Generator: nil}, + {Name: "vsetvli", OpcodeMask: 2147512447, Opcode: 28759, Fields: []InsnField{ + {"vtypei", 30, 11}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 28759, Generator: nil}, + {Name: "vsext.vf2", OpcodeMask: 4228903039, Opcode: 1208197207, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208197207, Generator: nil}, + {Name: "vsext.vf4", OpcodeMask: 4228903039, Opcode: 1208131671, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208131671, Generator: nil}, + {Name: "vsext.vf8", OpcodeMask: 4228903039, Opcode: 1208066135, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208066135, Generator: nil}, + {Name: "vslide1down.vx", OpcodeMask: 4227887231, Opcode: 1006657623, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1006657623, Generator: nil}, + {Name: "vslide1up.vx", OpcodeMask: 4227887231, Opcode: 939548759, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 939548759, Generator: nil}, + {Name: "vslidedown.vi", OpcodeMask: 4227887231, Opcode: 1006645335, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1006645335, Generator: nil}, + {Name: "vslidedown.vx", OpcodeMask: 4227887231, Opcode: 1006649431, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1006649431, Generator: nil}, + {Name: "vslideup.vi", OpcodeMask: 4227887231, Opcode: 939536471, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 939536471, Generator: nil}, + {Name: "vslideup.vx", OpcodeMask: 4227887231, Opcode: 939540567, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 939540567, Generator: nil}, + {Name: "vsll.vi", OpcodeMask: 4227887231, Opcode: 2483040343, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2483040343, Generator: nil}, + {Name: "vsll.vv", OpcodeMask: 4227887231, Opcode: 2483028055, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2483028055, Generator: nil}, + {Name: "vsll.vx", OpcodeMask: 4227887231, Opcode: 2483044439, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2483044439, Generator: nil}, + {Name: "vsm.v", OpcodeMask: 4293947519, Opcode: 45088807, Fields: []InsnField{ + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 45088807, Generator: nil}, + {Name: "vsmul.vv", OpcodeMask: 4227887231, Opcode: 2617245783, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2617245783, Generator: nil}, + {Name: "vsmul.vx", OpcodeMask: 4227887231, Opcode: 2617262167, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2617262167, Generator: nil}, + {Name: "vsoxei16.v", OpcodeMask: 4227887231, Opcode: 201347111, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 201347111, Generator: nil}, + {Name: "vsoxei32.v", OpcodeMask: 4227887231, Opcode: 201351207, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 201351207, Generator: nil}, + {Name: "vsoxei64.v", OpcodeMask: 4227887231, Opcode: 201355303, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 201355303, Generator: nil}, + {Name: "vsoxei8.v", OpcodeMask: 4227887231, Opcode: 201326631, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 201326631, Generator: nil}, + {Name: "vsoxseg2ei16.v", OpcodeMask: 4227887231, Opcode: 738218023, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 738218023, Generator: nil}, + {Name: "vsoxseg2ei32.v", OpcodeMask: 4227887231, Opcode: 738222119, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 738222119, Generator: nil}, + {Name: "vsoxseg2ei64.v", OpcodeMask: 4227887231, Opcode: 738226215, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 738226215, Generator: nil}, + {Name: "vsoxseg2ei8.v", OpcodeMask: 4227887231, Opcode: 738197543, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 738197543, Generator: nil}, + {Name: "vsoxseg3ei16.v", OpcodeMask: 4227887231, Opcode: 1275088935, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1275088935, Generator: nil}, + {Name: "vsoxseg3ei32.v", OpcodeMask: 4227887231, Opcode: 1275093031, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1275093031, Generator: nil}, + {Name: "vsoxseg3ei64.v", OpcodeMask: 4227887231, Opcode: 1275097127, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1275097127, Generator: nil}, + {Name: "vsoxseg3ei8.v", OpcodeMask: 4227887231, Opcode: 1275068455, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1275068455, Generator: nil}, + {Name: "vsoxseg4ei16.v", OpcodeMask: 4227887231, Opcode: 1811959847, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1811959847, Generator: nil}, + {Name: "vsoxseg4ei32.v", OpcodeMask: 4227887231, Opcode: 1811963943, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1811963943, Generator: nil}, + {Name: "vsoxseg4ei64.v", OpcodeMask: 4227887231, Opcode: 1811968039, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1811968039, Generator: nil}, + {Name: "vsoxseg4ei8.v", OpcodeMask: 4227887231, Opcode: 1811939367, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1811939367, Generator: nil}, + {Name: "vsoxseg5ei16.v", OpcodeMask: 4227887231, Opcode: 2348830759, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2348830759, Generator: nil}, + {Name: "vsoxseg5ei32.v", OpcodeMask: 4227887231, Opcode: 2348834855, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2348834855, Generator: nil}, + {Name: "vsoxseg5ei64.v", OpcodeMask: 4227887231, Opcode: 2348838951, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2348838951, Generator: nil}, + {Name: "vsoxseg5ei8.v", OpcodeMask: 4227887231, Opcode: 2348810279, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2348810279, Generator: nil}, + {Name: "vsoxseg6ei16.v", OpcodeMask: 4227887231, Opcode: 2885701671, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2885701671, Generator: nil}, + {Name: "vsoxseg6ei32.v", OpcodeMask: 4227887231, Opcode: 2885705767, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2885705767, Generator: nil}, + {Name: "vsoxseg6ei64.v", OpcodeMask: 4227887231, Opcode: 2885709863, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2885709863, Generator: nil}, + {Name: "vsoxseg6ei8.v", OpcodeMask: 4227887231, Opcode: 2885681191, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2885681191, Generator: nil}, + {Name: "vsoxseg7ei16.v", OpcodeMask: 4227887231, Opcode: 3422572583, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3422572583, Generator: nil}, + {Name: "vsoxseg7ei32.v", OpcodeMask: 4227887231, Opcode: 3422576679, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3422576679, Generator: nil}, + {Name: "vsoxseg7ei64.v", OpcodeMask: 4227887231, Opcode: 3422580775, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3422580775, Generator: nil}, + {Name: "vsoxseg7ei8.v", OpcodeMask: 4227887231, Opcode: 3422552103, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3422552103, Generator: nil}, + {Name: "vsoxseg8ei16.v", OpcodeMask: 4227887231, Opcode: 3959443495, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3959443495, Generator: nil}, + {Name: "vsoxseg8ei32.v", OpcodeMask: 4227887231, Opcode: 3959447591, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3959447591, Generator: nil}, + {Name: "vsoxseg8ei64.v", OpcodeMask: 4227887231, Opcode: 3959451687, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3959451687, Generator: nil}, + {Name: "vsoxseg8ei8.v", OpcodeMask: 4227887231, Opcode: 3959423015, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3959423015, Generator: nil}, + {Name: "vsra.vi", OpcodeMask: 4227887231, Opcode: 2751475799, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751475799, Generator: nil}, + {Name: "vsra.vv", OpcodeMask: 4227887231, Opcode: 2751463511, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751463511, Generator: nil}, + {Name: "vsra.vx", OpcodeMask: 4227887231, Opcode: 2751479895, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2751479895, Generator: nil}, + {Name: "vsrl.vi", OpcodeMask: 4227887231, Opcode: 2684366935, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2684366935, Generator: nil}, + {Name: "vsrl.vv", OpcodeMask: 4227887231, Opcode: 2684354647, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2684354647, Generator: nil}, + {Name: "vsrl.vx", OpcodeMask: 4227887231, Opcode: 2684371031, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2684371031, Generator: nil}, + {Name: "vsse16.v", OpcodeMask: 4227887231, Opcode: 134238247, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 134238247, Generator: nil}, + {Name: "vsse32.v", OpcodeMask: 4227887231, Opcode: 134242343, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 134242343, Generator: nil}, + {Name: "vsse64.v", OpcodeMask: 4227887231, Opcode: 134246439, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 134246439, Generator: nil}, + {Name: "vsse8.v", OpcodeMask: 4227887231, Opcode: 134217767, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 134217767, Generator: nil}, + {Name: "vsseg2e16.v", OpcodeMask: 4260393087, Opcode: 536891431, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 536891431, Generator: nil}, + {Name: "vsseg2e32.v", OpcodeMask: 4260393087, Opcode: 536895527, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 536895527, Generator: nil}, + {Name: "vsseg2e64.v", OpcodeMask: 4260393087, Opcode: 536899623, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 536899623, Generator: nil}, + {Name: "vsseg2e8.v", OpcodeMask: 4260393087, Opcode: 536870951, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 536870951, Generator: nil}, + {Name: "vsseg3e16.v", OpcodeMask: 4260393087, Opcode: 1073762343, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1073762343, Generator: nil}, + {Name: "vsseg3e32.v", OpcodeMask: 4260393087, Opcode: 1073766439, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1073766439, Generator: nil}, + {Name: "vsseg3e64.v", OpcodeMask: 4260393087, Opcode: 1073770535, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1073770535, Generator: nil}, + {Name: "vsseg3e8.v", OpcodeMask: 4260393087, Opcode: 1073741863, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1073741863, Generator: nil}, + {Name: "vsseg4e16.v", OpcodeMask: 4260393087, Opcode: 1610633255, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1610633255, Generator: nil}, + {Name: "vsseg4e32.v", OpcodeMask: 4260393087, Opcode: 1610637351, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1610637351, Generator: nil}, + {Name: "vsseg4e64.v", OpcodeMask: 4260393087, Opcode: 1610641447, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1610641447, Generator: nil}, + {Name: "vsseg4e8.v", OpcodeMask: 4260393087, Opcode: 1610612775, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1610612775, Generator: nil}, + {Name: "vsseg5e16.v", OpcodeMask: 4260393087, Opcode: 2147504167, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2147504167, Generator: nil}, + {Name: "vsseg5e32.v", OpcodeMask: 4260393087, Opcode: 2147508263, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2147508263, Generator: nil}, + {Name: "vsseg5e64.v", OpcodeMask: 4260393087, Opcode: 2147512359, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2147512359, Generator: nil}, + {Name: "vsseg5e8.v", OpcodeMask: 4260393087, Opcode: 2147483687, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2147483687, Generator: nil}, + {Name: "vsseg6e16.v", OpcodeMask: 4260393087, Opcode: 2684375079, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2684375079, Generator: nil}, + {Name: "vsseg6e32.v", OpcodeMask: 4260393087, Opcode: 2684379175, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2684379175, Generator: nil}, + {Name: "vsseg6e64.v", OpcodeMask: 4260393087, Opcode: 2684383271, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2684383271, Generator: nil}, + {Name: "vsseg6e8.v", OpcodeMask: 4260393087, Opcode: 2684354599, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2684354599, Generator: nil}, + {Name: "vsseg7e16.v", OpcodeMask: 4260393087, Opcode: 3221245991, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3221245991, Generator: nil}, + {Name: "vsseg7e32.v", OpcodeMask: 4260393087, Opcode: 3221250087, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3221250087, Generator: nil}, + {Name: "vsseg7e64.v", OpcodeMask: 4260393087, Opcode: 3221254183, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3221254183, Generator: nil}, + {Name: "vsseg7e8.v", OpcodeMask: 4260393087, Opcode: 3221225511, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3221225511, Generator: nil}, + {Name: "vsseg8e16.v", OpcodeMask: 4260393087, Opcode: 3758116903, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3758116903, Generator: nil}, + {Name: "vsseg8e32.v", OpcodeMask: 4260393087, Opcode: 3758120999, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3758120999, Generator: nil}, + {Name: "vsseg8e64.v", OpcodeMask: 4260393087, Opcode: 3758125095, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3758125095, Generator: nil}, + {Name: "vsseg8e8.v", OpcodeMask: 4260393087, Opcode: 3758096423, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3758096423, Generator: nil}, + {Name: "vssra.vi", OpcodeMask: 4227887231, Opcode: 2885693527, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885693527, Generator: nil}, + {Name: "vssra.vv", OpcodeMask: 4227887231, Opcode: 2885681239, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885681239, Generator: nil}, + {Name: "vssra.vx", OpcodeMask: 4227887231, Opcode: 2885697623, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2885697623, Generator: nil}, + {Name: "vssrl.vi", OpcodeMask: 4227887231, Opcode: 2818584663, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2818584663, Generator: nil}, + {Name: "vssrl.vv", OpcodeMask: 4227887231, Opcode: 2818572375, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2818572375, Generator: nil}, + {Name: "vssrl.vx", OpcodeMask: 4227887231, Opcode: 2818588759, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2818588759, Generator: nil}, + {Name: "vssseg2e16.v", OpcodeMask: 4227887231, Opcode: 671109159, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 671109159, Generator: nil}, + {Name: "vssseg2e32.v", OpcodeMask: 4227887231, Opcode: 671113255, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 671113255, Generator: nil}, + {Name: "vssseg2e64.v", OpcodeMask: 4227887231, Opcode: 671117351, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 671117351, Generator: nil}, + {Name: "vssseg2e8.v", OpcodeMask: 4227887231, Opcode: 671088679, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 671088679, Generator: nil}, + {Name: "vssseg3e16.v", OpcodeMask: 4227887231, Opcode: 1207980071, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1207980071, Generator: nil}, + {Name: "vssseg3e32.v", OpcodeMask: 4227887231, Opcode: 1207984167, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1207984167, Generator: nil}, + {Name: "vssseg3e64.v", OpcodeMask: 4227887231, Opcode: 1207988263, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1207988263, Generator: nil}, + {Name: "vssseg3e8.v", OpcodeMask: 4227887231, Opcode: 1207959591, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1207959591, Generator: nil}, + {Name: "vssseg4e16.v", OpcodeMask: 4227887231, Opcode: 1744850983, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1744850983, Generator: nil}, + {Name: "vssseg4e32.v", OpcodeMask: 4227887231, Opcode: 1744855079, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1744855079, Generator: nil}, + {Name: "vssseg4e64.v", OpcodeMask: 4227887231, Opcode: 1744859175, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1744859175, Generator: nil}, + {Name: "vssseg4e8.v", OpcodeMask: 4227887231, Opcode: 1744830503, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1744830503, Generator: nil}, + {Name: "vssseg5e16.v", OpcodeMask: 4227887231, Opcode: 2281721895, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2281721895, Generator: nil}, + {Name: "vssseg5e32.v", OpcodeMask: 4227887231, Opcode: 2281725991, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2281725991, Generator: nil}, + {Name: "vssseg5e64.v", OpcodeMask: 4227887231, Opcode: 2281730087, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2281730087, Generator: nil}, + {Name: "vssseg5e8.v", OpcodeMask: 4227887231, Opcode: 2281701415, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2281701415, Generator: nil}, + {Name: "vssseg6e16.v", OpcodeMask: 4227887231, Opcode: 2818592807, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2818592807, Generator: nil}, + {Name: "vssseg6e32.v", OpcodeMask: 4227887231, Opcode: 2818596903, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2818596903, Generator: nil}, + {Name: "vssseg6e64.v", OpcodeMask: 4227887231, Opcode: 2818600999, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2818600999, Generator: nil}, + {Name: "vssseg6e8.v", OpcodeMask: 4227887231, Opcode: 2818572327, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2818572327, Generator: nil}, + {Name: "vssseg7e16.v", OpcodeMask: 4227887231, Opcode: 3355463719, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3355463719, Generator: nil}, + {Name: "vssseg7e32.v", OpcodeMask: 4227887231, Opcode: 3355467815, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3355467815, Generator: nil}, + {Name: "vssseg7e64.v", OpcodeMask: 4227887231, Opcode: 3355471911, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3355471911, Generator: nil}, + {Name: "vssseg7e8.v", OpcodeMask: 4227887231, Opcode: 3355443239, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3355443239, Generator: nil}, + {Name: "vssseg8e16.v", OpcodeMask: 4227887231, Opcode: 3892334631, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3892334631, Generator: nil}, + {Name: "vssseg8e32.v", OpcodeMask: 4227887231, Opcode: 3892338727, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3892338727, Generator: nil}, + {Name: "vssseg8e64.v", OpcodeMask: 4227887231, Opcode: 3892342823, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3892342823, Generator: nil}, + {Name: "vssseg8e8.v", OpcodeMask: 4227887231, Opcode: 3892314151, Fields: []InsnField{ + {"vm", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3892314151, Generator: nil}, + {Name: "vssub.vv", OpcodeMask: 4227887231, Opcode: 2348810327, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2348810327, Generator: nil}, + {Name: "vssub.vx", OpcodeMask: 4227887231, Opcode: 2348826711, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2348826711, Generator: nil}, + {Name: "vssubu.vv", OpcodeMask: 4227887231, Opcode: 2281701463, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2281701463, Generator: nil}, + {Name: "vssubu.vx", OpcodeMask: 4227887231, Opcode: 2281717847, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2281717847, Generator: nil}, + {Name: "vsub.vv", OpcodeMask: 4227887231, Opcode: 134217815, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 134217815, Generator: nil}, + {Name: "vsub.vx", OpcodeMask: 4227887231, Opcode: 134234199, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 134234199, Generator: nil}, + {Name: "vsuxei16.v", OpcodeMask: 4227887231, Opcode: 67129383, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 67129383, Generator: nil}, + {Name: "vsuxei32.v", OpcodeMask: 4227887231, Opcode: 67133479, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 67133479, Generator: nil}, + {Name: "vsuxei64.v", OpcodeMask: 4227887231, Opcode: 67137575, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 67137575, Generator: nil}, + {Name: "vsuxei8.v", OpcodeMask: 4227887231, Opcode: 67108903, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 67108903, Generator: nil}, + {Name: "vsuxseg2ei16.v", OpcodeMask: 4227887231, Opcode: 604000295, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 604000295, Generator: nil}, + {Name: "vsuxseg2ei32.v", OpcodeMask: 4227887231, Opcode: 604004391, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 604004391, Generator: nil}, + {Name: "vsuxseg2ei64.v", OpcodeMask: 4227887231, Opcode: 604008487, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 604008487, Generator: nil}, + {Name: "vsuxseg2ei8.v", OpcodeMask: 4227887231, Opcode: 603979815, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 603979815, Generator: nil}, + {Name: "vsuxseg3ei16.v", OpcodeMask: 4227887231, Opcode: 1140871207, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1140871207, Generator: nil}, + {Name: "vsuxseg3ei32.v", OpcodeMask: 4227887231, Opcode: 1140875303, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1140875303, Generator: nil}, + {Name: "vsuxseg3ei64.v", OpcodeMask: 4227887231, Opcode: 1140879399, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1140879399, Generator: nil}, + {Name: "vsuxseg3ei8.v", OpcodeMask: 4227887231, Opcode: 1140850727, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1140850727, Generator: nil}, + {Name: "vsuxseg4ei16.v", OpcodeMask: 4227887231, Opcode: 1677742119, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1677742119, Generator: nil}, + {Name: "vsuxseg4ei32.v", OpcodeMask: 4227887231, Opcode: 1677746215, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1677746215, Generator: nil}, + {Name: "vsuxseg4ei64.v", OpcodeMask: 4227887231, Opcode: 1677750311, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1677750311, Generator: nil}, + {Name: "vsuxseg4ei8.v", OpcodeMask: 4227887231, Opcode: 1677721639, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 1677721639, Generator: nil}, + {Name: "vsuxseg5ei16.v", OpcodeMask: 4227887231, Opcode: 2214613031, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2214613031, Generator: nil}, + {Name: "vsuxseg5ei32.v", OpcodeMask: 4227887231, Opcode: 2214617127, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2214617127, Generator: nil}, + {Name: "vsuxseg5ei64.v", OpcodeMask: 4227887231, Opcode: 2214621223, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2214621223, Generator: nil}, + {Name: "vsuxseg5ei8.v", OpcodeMask: 4227887231, Opcode: 2214592551, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2214592551, Generator: nil}, + {Name: "vsuxseg6ei16.v", OpcodeMask: 4227887231, Opcode: 2751483943, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2751483943, Generator: nil}, + {Name: "vsuxseg6ei32.v", OpcodeMask: 4227887231, Opcode: 2751488039, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2751488039, Generator: nil}, + {Name: "vsuxseg6ei64.v", OpcodeMask: 4227887231, Opcode: 2751492135, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2751492135, Generator: nil}, + {Name: "vsuxseg6ei8.v", OpcodeMask: 4227887231, Opcode: 2751463463, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 2751463463, Generator: nil}, + {Name: "vsuxseg7ei16.v", OpcodeMask: 4227887231, Opcode: 3288354855, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3288354855, Generator: nil}, + {Name: "vsuxseg7ei32.v", OpcodeMask: 4227887231, Opcode: 3288358951, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3288358951, Generator: nil}, + {Name: "vsuxseg7ei64.v", OpcodeMask: 4227887231, Opcode: 3288363047, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3288363047, Generator: nil}, + {Name: "vsuxseg7ei8.v", OpcodeMask: 4227887231, Opcode: 3288334375, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3288334375, Generator: nil}, + {Name: "vsuxseg8ei16.v", OpcodeMask: 4227887231, Opcode: 3825225767, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3825225767, Generator: nil}, + {Name: "vsuxseg8ei32.v", OpcodeMask: 4227887231, Opcode: 3825229863, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3825229863, Generator: nil}, + {Name: "vsuxseg8ei64.v", OpcodeMask: 4227887231, Opcode: 3825233959, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3825233959, Generator: nil}, + {Name: "vsuxseg8ei8.v", OpcodeMask: 4227887231, Opcode: 3825205287, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vs3", 11, 5}, + }, AsUInt32: 3825205287, Generator: nil}, + {Name: "vwadd.vv", OpcodeMask: 4227887231, Opcode: 3288342615, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3288342615, Generator: nil}, + {Name: "vwadd.vx", OpcodeMask: 4227887231, Opcode: 3288358999, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3288358999, Generator: nil}, + {Name: "vwadd.wv", OpcodeMask: 4227887231, Opcode: 3556778071, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3556778071, Generator: nil}, + {Name: "vwadd.wx", OpcodeMask: 4227887231, Opcode: 3556794455, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3556794455, Generator: nil}, + {Name: "vwaddu.vv", OpcodeMask: 4227887231, Opcode: 3221233751, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3221233751, Generator: nil}, + {Name: "vwaddu.vx", OpcodeMask: 4227887231, Opcode: 3221250135, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3221250135, Generator: nil}, + {Name: "vwaddu.wv", OpcodeMask: 4227887231, Opcode: 3489669207, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3489669207, Generator: nil}, + {Name: "vwaddu.wx", OpcodeMask: 4227887231, Opcode: 3489685591, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3489685591, Generator: nil}, + {Name: "vwmacc.vv", OpcodeMask: 4227887231, Opcode: 4093648983, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4093648983, Generator: nil}, + {Name: "vwmacc.vx", OpcodeMask: 4227887231, Opcode: 4093665367, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4093665367, Generator: nil}, + {Name: "vwmaccsu.vv", OpcodeMask: 4227887231, Opcode: 4227866711, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4227866711, Generator: nil}, + {Name: "vwmaccsu.vx", OpcodeMask: 4227887231, Opcode: 4227883095, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4227883095, Generator: nil}, + {Name: "vwmaccu.vv", OpcodeMask: 4227887231, Opcode: 4026540119, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4026540119, Generator: nil}, + {Name: "vwmaccu.vx", OpcodeMask: 4227887231, Opcode: 4026556503, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4026556503, Generator: nil}, + {Name: "vwmaccus.vx", OpcodeMask: 4227887231, Opcode: 4160774231, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 4160774231, Generator: nil}, + {Name: "vwmul.vv", OpcodeMask: 4227887231, Opcode: 3959431255, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3959431255, Generator: nil}, + {Name: "vwmul.vx", OpcodeMask: 4227887231, Opcode: 3959447639, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3959447639, Generator: nil}, + {Name: "vwmulsu.vv", OpcodeMask: 4227887231, Opcode: 3892322391, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3892322391, Generator: nil}, + {Name: "vwmulsu.vx", OpcodeMask: 4227887231, Opcode: 3892338775, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3892338775, Generator: nil}, + {Name: "vwmulu.vv", OpcodeMask: 4227887231, Opcode: 3758104663, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3758104663, Generator: nil}, + {Name: "vwmulu.vx", OpcodeMask: 4227887231, Opcode: 3758121047, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3758121047, Generator: nil}, + {Name: "vwredsum.vs", OpcodeMask: 4227887231, Opcode: 3288334423, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3288334423, Generator: nil}, + {Name: "vwredsumu.vs", OpcodeMask: 4227887231, Opcode: 3221225559, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3221225559, Generator: nil}, + {Name: "vwsub.vv", OpcodeMask: 4227887231, Opcode: 3422560343, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3422560343, Generator: nil}, + {Name: "vwsub.vx", OpcodeMask: 4227887231, Opcode: 3422576727, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3422576727, Generator: nil}, + {Name: "vwsub.wv", OpcodeMask: 4227887231, Opcode: 3690995799, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3690995799, Generator: nil}, + {Name: "vwsub.wx", OpcodeMask: 4227887231, Opcode: 3691012183, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3691012183, Generator: nil}, + {Name: "vwsubu.vv", OpcodeMask: 4227887231, Opcode: 3355451479, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3355451479, Generator: nil}, + {Name: "vwsubu.vx", OpcodeMask: 4227887231, Opcode: 3355467863, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3355467863, Generator: nil}, + {Name: "vwsubu.wv", OpcodeMask: 4227887231, Opcode: 3623886935, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3623886935, Generator: nil}, + {Name: "vwsubu.wx", OpcodeMask: 4227887231, Opcode: 3623903319, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3623903319, Generator: nil}, + {Name: "vxor.vi", OpcodeMask: 4227887231, Opcode: 738209879, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 738209879, Generator: nil}, + {Name: "vxor.vv", OpcodeMask: 4227887231, Opcode: 738197591, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 738197591, Generator: nil}, + {Name: "vxor.vx", OpcodeMask: 4227887231, Opcode: 738213975, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 738213975, Generator: nil}, + {Name: "vzext.vf2", OpcodeMask: 4228903039, Opcode: 1208164439, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208164439, Generator: nil}, + {Name: "vzext.vf4", OpcodeMask: 4228903039, Opcode: 1208098903, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208098903, Generator: nil}, + {Name: "vzext.vf8", OpcodeMask: 4228903039, Opcode: 1208033367, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208033367, Generator: nil}, + {Name: "amoadd.d.aq", OpcodeMask: 4261441663, Opcode: 67121199, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 67121199, Generator: nil}, + {Name: "amoadd.d.aqrl", OpcodeMask: 4261441663, Opcode: 100675631, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 100675631, Generator: nil}, + {Name: "amoadd.d.rl", OpcodeMask: 4261441663, Opcode: 33566767, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33566767, Generator: nil}, + {Name: "amoadd.d", OpcodeMask: 4261441663, Opcode: 12335, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 12335, Generator: nil}, + {Name: "amoadd.w.aq", OpcodeMask: 4261441663, Opcode: 67117103, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 67117103, Generator: nil}, + {Name: "amoadd.w.aqrl", OpcodeMask: 4261441663, Opcode: 100671535, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 100671535, Generator: nil}, + {Name: "amoadd.w.rl", OpcodeMask: 4261441663, Opcode: 33562671, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33562671, Generator: nil}, + {Name: "amoadd.w", OpcodeMask: 4261441663, Opcode: 8239, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 8239, Generator: nil}, + {Name: "amoand.d.aq", OpcodeMask: 4261441663, Opcode: 1677733935, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1677733935, Generator: nil}, + {Name: "amoand.d.aqrl", OpcodeMask: 4261441663, Opcode: 1711288367, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1711288367, Generator: nil}, + {Name: "amoand.d.rl", OpcodeMask: 4261441663, Opcode: 1644179503, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1644179503, Generator: nil}, + {Name: "amoand.d", OpcodeMask: 4261441663, Opcode: 1610625071, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1610625071, Generator: nil}, + {Name: "amoand.w.aq", OpcodeMask: 4261441663, Opcode: 1677729839, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1677729839, Generator: nil}, + {Name: "amoand.w.aqrl", OpcodeMask: 4261441663, Opcode: 1711284271, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1711284271, Generator: nil}, + {Name: "amoand.w.rl", OpcodeMask: 4261441663, Opcode: 1644175407, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1644175407, Generator: nil}, + {Name: "amoand.w", OpcodeMask: 4261441663, Opcode: 1610620975, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1610620975, Generator: nil}, + {Name: "amomax.d.aq", OpcodeMask: 4261441663, Opcode: 2751475759, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2751475759, Generator: nil}, + {Name: "amomax.d.aqrl", OpcodeMask: 4261441663, Opcode: 2785030191, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2785030191, Generator: nil}, + {Name: "amomax.d.rl", OpcodeMask: 4261441663, Opcode: 2717921327, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2717921327, Generator: nil}, + {Name: "amomax.d", OpcodeMask: 4261441663, Opcode: 2684366895, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2684366895, Generator: nil}, + {Name: "amomax.w.aq", OpcodeMask: 4261441663, Opcode: 2751471663, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2751471663, Generator: nil}, + {Name: "amomax.w.aqrl", OpcodeMask: 4261441663, Opcode: 2785026095, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2785026095, Generator: nil}, + {Name: "amomax.w.rl", OpcodeMask: 4261441663, Opcode: 2717917231, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2717917231, Generator: nil}, + {Name: "amomax.w", OpcodeMask: 4261441663, Opcode: 2684362799, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2684362799, Generator: nil}, + {Name: "amomaxu.d.aq", OpcodeMask: 4261441663, Opcode: 3825217583, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3825217583, Generator: nil}, + {Name: "amomaxu.d.aqrl", OpcodeMask: 4261441663, Opcode: 3858772015, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3858772015, Generator: nil}, + {Name: "amomaxu.d.rl", OpcodeMask: 4261441663, Opcode: 3791663151, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3791663151, Generator: nil}, + {Name: "amomaxu.d", OpcodeMask: 4261441663, Opcode: 3758108719, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3758108719, Generator: nil}, + {Name: "amomaxu.w.aq", OpcodeMask: 4261441663, Opcode: 3825213487, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3825213487, Generator: nil}, + {Name: "amomaxu.w.aqrl", OpcodeMask: 4261441663, Opcode: 3858767919, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3858767919, Generator: nil}, + {Name: "amomaxu.w.rl", OpcodeMask: 4261441663, Opcode: 3791659055, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3791659055, Generator: nil}, + {Name: "amomaxu.w", OpcodeMask: 4261441663, Opcode: 3758104623, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3758104623, Generator: nil}, + {Name: "amomin.d.aq", OpcodeMask: 4261441663, Opcode: 2214604847, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2214604847, Generator: nil}, + {Name: "amomin.d.aqrl", OpcodeMask: 4261441663, Opcode: 2248159279, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2248159279, Generator: nil}, + {Name: "amomin.d.rl", OpcodeMask: 4261441663, Opcode: 2181050415, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2181050415, Generator: nil}, + {Name: "amomin.d", OpcodeMask: 4261441663, Opcode: 2147495983, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2147495983, Generator: nil}, + {Name: "amomin.w.aq", OpcodeMask: 4261441663, Opcode: 2214600751, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2214600751, Generator: nil}, + {Name: "amomin.w.aqrl", OpcodeMask: 4261441663, Opcode: 2248155183, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2248155183, Generator: nil}, + {Name: "amomin.w.rl", OpcodeMask: 4261441663, Opcode: 2181046319, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2181046319, Generator: nil}, + {Name: "amomin.w", OpcodeMask: 4261441663, Opcode: 2147491887, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2147491887, Generator: nil}, + {Name: "amominu.d.aq", OpcodeMask: 4261441663, Opcode: 3288346671, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3288346671, Generator: nil}, + {Name: "amominu.d.aqrl", OpcodeMask: 4261441663, Opcode: 3321901103, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3321901103, Generator: nil}, + {Name: "amominu.d.rl", OpcodeMask: 4261441663, Opcode: 3254792239, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3254792239, Generator: nil}, + {Name: "amominu.d", OpcodeMask: 4261441663, Opcode: 3221237807, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3221237807, Generator: nil}, + {Name: "amominu.w.aq", OpcodeMask: 4261441663, Opcode: 3288342575, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3288342575, Generator: nil}, + {Name: "amominu.w.aqrl", OpcodeMask: 4261441663, Opcode: 3321897007, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3321897007, Generator: nil}, + {Name: "amominu.w.rl", OpcodeMask: 4261441663, Opcode: 3254788143, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3254788143, Generator: nil}, + {Name: "amominu.w", OpcodeMask: 4261441663, Opcode: 3221233711, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3221233711, Generator: nil}, + {Name: "amoor.d.aq", OpcodeMask: 4261441663, Opcode: 1140863023, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1140863023, Generator: nil}, + {Name: "amoor.d.aqrl", OpcodeMask: 4261441663, Opcode: 1174417455, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1174417455, Generator: nil}, + {Name: "amoor.d.rl", OpcodeMask: 4261441663, Opcode: 1107308591, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1107308591, Generator: nil}, + {Name: "amoor.d", OpcodeMask: 4261441663, Opcode: 1073754159, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1073754159, Generator: nil}, + {Name: "amoor.w.aq", OpcodeMask: 4261441663, Opcode: 1140858927, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1140858927, Generator: nil}, + {Name: "amoor.w.aqrl", OpcodeMask: 4261441663, Opcode: 1174413359, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1174413359, Generator: nil}, + {Name: "amoor.w.rl", OpcodeMask: 4261441663, Opcode: 1107304495, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1107304495, Generator: nil}, + {Name: "amoor.w", OpcodeMask: 4261441663, Opcode: 1073750063, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1073750063, Generator: nil}, + {Name: "amoswap.d.aq", OpcodeMask: 4261441663, Opcode: 201338927, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 201338927, Generator: nil}, + {Name: "amoswap.d.aqrl", OpcodeMask: 4261441663, Opcode: 234893359, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 234893359, Generator: nil}, + {Name: "amoswap.d.rl", OpcodeMask: 4261441663, Opcode: 167784495, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 167784495, Generator: nil}, + {Name: "amoswap.d", OpcodeMask: 4261441663, Opcode: 134230063, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 134230063, Generator: nil}, + {Name: "amoswap.w.aq", OpcodeMask: 4261441663, Opcode: 201334831, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 201334831, Generator: nil}, + {Name: "amoswap.w.aqrl", OpcodeMask: 4261441663, Opcode: 234889263, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 234889263, Generator: nil}, + {Name: "amoswap.w.rl", OpcodeMask: 4261441663, Opcode: 167780399, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 167780399, Generator: nil}, + {Name: "amoswap.w", OpcodeMask: 4261441663, Opcode: 134225967, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 134225967, Generator: nil}, + {Name: "amoxor.d.aq", OpcodeMask: 4261441663, Opcode: 603992111, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 603992111, Generator: nil}, + {Name: "amoxor.d.aqrl", OpcodeMask: 4261441663, Opcode: 637546543, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 637546543, Generator: nil}, + {Name: "amoxor.d.rl", OpcodeMask: 4261441663, Opcode: 570437679, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 570437679, Generator: nil}, + {Name: "amoxor.d", OpcodeMask: 4261441663, Opcode: 536883247, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 536883247, Generator: nil}, + {Name: "amoxor.w.aq", OpcodeMask: 4261441663, Opcode: 603988015, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 603988015, Generator: nil}, + {Name: "amoxor.w.aqrl", OpcodeMask: 4261441663, Opcode: 637542447, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 637542447, Generator: nil}, + {Name: "amoxor.w.rl", OpcodeMask: 4261441663, Opcode: 570433583, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 570433583, Generator: nil}, + {Name: "amoxor.w", OpcodeMask: 4261441663, Opcode: 536879151, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 536879151, Generator: nil}, + {Name: "amoadd.b.aq", OpcodeMask: 4261441663, Opcode: 67108911, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 67108911, Generator: nil}, + {Name: "amoadd.b.aqrl", OpcodeMask: 4261441663, Opcode: 100663343, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 100663343, Generator: nil}, + {Name: "amoadd.b.rl", OpcodeMask: 4261441663, Opcode: 33554479, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33554479, Generator: nil}, + {Name: "amoadd.b", OpcodeMask: 4261441663, Opcode: 47, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 47, Generator: nil}, + {Name: "amoadd.h.aq", OpcodeMask: 4261441663, Opcode: 67113007, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 67113007, Generator: nil}, + {Name: "amoadd.h.aqrl", OpcodeMask: 4261441663, Opcode: 100667439, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 100667439, Generator: nil}, + {Name: "amoadd.h.rl", OpcodeMask: 4261441663, Opcode: 33558575, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 33558575, Generator: nil}, + {Name: "amoadd.h", OpcodeMask: 4261441663, Opcode: 4143, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 4143, Generator: nil}, + {Name: "amoand.b.aq", OpcodeMask: 4261441663, Opcode: 1677721647, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1677721647, Generator: nil}, + {Name: "amoand.b.aqrl", OpcodeMask: 4261441663, Opcode: 1711276079, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1711276079, Generator: nil}, + {Name: "amoand.b.rl", OpcodeMask: 4261441663, Opcode: 1644167215, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1644167215, Generator: nil}, + {Name: "amoand.b", OpcodeMask: 4261441663, Opcode: 1610612783, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1610612783, Generator: nil}, + {Name: "amoand.h.aq", OpcodeMask: 4261441663, Opcode: 1677725743, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1677725743, Generator: nil}, + {Name: "amoand.h.aqrl", OpcodeMask: 4261441663, Opcode: 1711280175, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1711280175, Generator: nil}, + {Name: "amoand.h.rl", OpcodeMask: 4261441663, Opcode: 1644171311, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1644171311, Generator: nil}, + {Name: "amoand.h", OpcodeMask: 4261441663, Opcode: 1610616879, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1610616879, Generator: nil}, + {Name: "amocas.b.aq", OpcodeMask: 4261441663, Opcode: 738197551, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 738197551, Generator: nil}, + {Name: "amocas.b.aqrl", OpcodeMask: 4261441663, Opcode: 771751983, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 771751983, Generator: nil}, + {Name: "amocas.b.rl", OpcodeMask: 4261441663, Opcode: 704643119, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 704643119, Generator: nil}, + {Name: "amocas.b", OpcodeMask: 4261441663, Opcode: 671088687, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 671088687, Generator: nil}, + {Name: "amocas.h.aq", OpcodeMask: 4261441663, Opcode: 738201647, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 738201647, Generator: nil}, + {Name: "amocas.h.aqrl", OpcodeMask: 4261441663, Opcode: 771756079, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 771756079, Generator: nil}, + {Name: "amocas.h.rl", OpcodeMask: 4261441663, Opcode: 704647215, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 704647215, Generator: nil}, + {Name: "amocas.h", OpcodeMask: 4261441663, Opcode: 671092783, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 671092783, Generator: nil}, + {Name: "amomax.b.aq", OpcodeMask: 4261441663, Opcode: 2751463471, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2751463471, Generator: nil}, + {Name: "amomax.b.aqrl", OpcodeMask: 4261441663, Opcode: 2785017903, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2785017903, Generator: nil}, + {Name: "amomax.b.rl", OpcodeMask: 4261441663, Opcode: 2717909039, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2717909039, Generator: nil}, + {Name: "amomax.b", OpcodeMask: 4261441663, Opcode: 2684354607, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2684354607, Generator: nil}, + {Name: "amomax.h.aq", OpcodeMask: 4261441663, Opcode: 2751467567, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2751467567, Generator: nil}, + {Name: "amomax.h.aqrl", OpcodeMask: 4261441663, Opcode: 2785021999, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2785021999, Generator: nil}, + {Name: "amomax.h.rl", OpcodeMask: 4261441663, Opcode: 2717913135, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2717913135, Generator: nil}, + {Name: "amomax.h", OpcodeMask: 4261441663, Opcode: 2684358703, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2684358703, Generator: nil}, + {Name: "amomaxu.b.aq", OpcodeMask: 4261441663, Opcode: 3825205295, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3825205295, Generator: nil}, + {Name: "amomaxu.b.aqrl", OpcodeMask: 4261441663, Opcode: 3858759727, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3858759727, Generator: nil}, + {Name: "amomaxu.b.rl", OpcodeMask: 4261441663, Opcode: 3791650863, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3791650863, Generator: nil}, + {Name: "amomaxu.b", OpcodeMask: 4261441663, Opcode: 3758096431, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3758096431, Generator: nil}, + {Name: "amomaxu.h.aq", OpcodeMask: 4261441663, Opcode: 3825209391, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3825209391, Generator: nil}, + {Name: "amomaxu.h.aqrl", OpcodeMask: 4261441663, Opcode: 3858763823, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3858763823, Generator: nil}, + {Name: "amomaxu.h.rl", OpcodeMask: 4261441663, Opcode: 3791654959, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3791654959, Generator: nil}, + {Name: "amomaxu.h", OpcodeMask: 4261441663, Opcode: 3758100527, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3758100527, Generator: nil}, + {Name: "amomin.b.aq", OpcodeMask: 4261441663, Opcode: 2214592559, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2214592559, Generator: nil}, + {Name: "amomin.b.aqrl", OpcodeMask: 4261441663, Opcode: 2248146991, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2248146991, Generator: nil}, + {Name: "amomin.b.rl", OpcodeMask: 4261441663, Opcode: 2181038127, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2181038127, Generator: nil}, + {Name: "amomin.b", OpcodeMask: 4261441663, Opcode: 2147483695, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2147483695, Generator: nil}, + {Name: "amomin.h.aq", OpcodeMask: 4261441663, Opcode: 2214596655, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2214596655, Generator: nil}, + {Name: "amomin.h.aqrl", OpcodeMask: 4261441663, Opcode: 2248151087, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2248151087, Generator: nil}, + {Name: "amomin.h.rl", OpcodeMask: 4261441663, Opcode: 2181042223, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2181042223, Generator: nil}, + {Name: "amomin.h", OpcodeMask: 4261441663, Opcode: 2147487791, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2147487791, Generator: nil}, + {Name: "amominu.b.aq", OpcodeMask: 4261441663, Opcode: 3288334383, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3288334383, Generator: nil}, + {Name: "amominu.b.aqrl", OpcodeMask: 4261441663, Opcode: 3321888815, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3321888815, Generator: nil}, + {Name: "amominu.b.rl", OpcodeMask: 4261441663, Opcode: 3254779951, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3254779951, Generator: nil}, + {Name: "amominu.b", OpcodeMask: 4261441663, Opcode: 3221225519, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3221225519, Generator: nil}, + {Name: "amominu.h.aq", OpcodeMask: 4261441663, Opcode: 3288338479, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3288338479, Generator: nil}, + {Name: "amominu.h.aqrl", OpcodeMask: 4261441663, Opcode: 3321892911, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3321892911, Generator: nil}, + {Name: "amominu.h.rl", OpcodeMask: 4261441663, Opcode: 3254784047, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3254784047, Generator: nil}, + {Name: "amominu.h", OpcodeMask: 4261441663, Opcode: 3221229615, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3221229615, Generator: nil}, + {Name: "amoor.b.aq", OpcodeMask: 4261441663, Opcode: 1140850735, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1140850735, Generator: nil}, + {Name: "amoor.b.aqrl", OpcodeMask: 4261441663, Opcode: 1174405167, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1174405167, Generator: nil}, + {Name: "amoor.b.rl", OpcodeMask: 4261441663, Opcode: 1107296303, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1107296303, Generator: nil}, + {Name: "amoor.b", OpcodeMask: 4261441663, Opcode: 1073741871, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1073741871, Generator: nil}, + {Name: "amoor.h.aq", OpcodeMask: 4261441663, Opcode: 1140854831, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1140854831, Generator: nil}, + {Name: "amoor.h.aqrl", OpcodeMask: 4261441663, Opcode: 1174409263, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1174409263, Generator: nil}, + {Name: "amoor.h.rl", OpcodeMask: 4261441663, Opcode: 1107300399, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1107300399, Generator: nil}, + {Name: "amoor.h", OpcodeMask: 4261441663, Opcode: 1073745967, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1073745967, Generator: nil}, + {Name: "amoswap.b.aq", OpcodeMask: 4261441663, Opcode: 201326639, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 201326639, Generator: nil}, + {Name: "amoswap.b.aqrl", OpcodeMask: 4261441663, Opcode: 234881071, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 234881071, Generator: nil}, + {Name: "amoswap.b.rl", OpcodeMask: 4261441663, Opcode: 167772207, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 167772207, Generator: nil}, + {Name: "amoswap.b", OpcodeMask: 4261441663, Opcode: 134217775, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 134217775, Generator: nil}, + {Name: "amoswap.h.aq", OpcodeMask: 4261441663, Opcode: 201330735, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 201330735, Generator: nil}, + {Name: "amoswap.h.aqrl", OpcodeMask: 4261441663, Opcode: 234885167, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 234885167, Generator: nil}, + {Name: "amoswap.h.rl", OpcodeMask: 4261441663, Opcode: 167776303, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 167776303, Generator: nil}, + {Name: "amoswap.h", OpcodeMask: 4261441663, Opcode: 134221871, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 134221871, Generator: nil}, + {Name: "amoxor.b.aq", OpcodeMask: 4261441663, Opcode: 603979823, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 603979823, Generator: nil}, + {Name: "amoxor.b.aqrl", OpcodeMask: 4261441663, Opcode: 637534255, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 637534255, Generator: nil}, + {Name: "amoxor.b.rl", OpcodeMask: 4261441663, Opcode: 570425391, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 570425391, Generator: nil}, + {Name: "amoxor.b", OpcodeMask: 4261441663, Opcode: 536870959, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 536870959, Generator: nil}, + {Name: "amoxor.h.aq", OpcodeMask: 4261441663, Opcode: 603983919, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 603983919, Generator: nil}, + {Name: "amoxor.h.aqrl", OpcodeMask: 4261441663, Opcode: 637538351, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 637538351, Generator: nil}, + {Name: "amoxor.h.rl", OpcodeMask: 4261441663, Opcode: 570429487, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 570429487, Generator: nil}, + {Name: "amoxor.h", OpcodeMask: 4261441663, Opcode: 536875055, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 536875055, Generator: nil}, + {Name: "amocas.d.aq", OpcodeMask: 4261441663, Opcode: 738209839, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 738209839, Generator: nil}, + {Name: "amocas.d.aqrl", OpcodeMask: 4261441663, Opcode: 771764271, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 771764271, Generator: nil}, + {Name: "amocas.d.rl", OpcodeMask: 4261441663, Opcode: 704655407, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 704655407, Generator: nil}, + {Name: "amocas.d", OpcodeMask: 4261441663, Opcode: 671100975, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 671100975, Generator: nil}, + {Name: "amocas.q.aq", OpcodeMask: 4261441663, Opcode: 738213935, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 738213935, Generator: nil}, + {Name: "amocas.q.aqrl", OpcodeMask: 4261441663, Opcode: 771768367, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 771768367, Generator: nil}, + {Name: "amocas.q.rl", OpcodeMask: 4261441663, Opcode: 704659503, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 704659503, Generator: nil}, + {Name: "amocas.q", OpcodeMask: 4261441663, Opcode: 671105071, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 671105071, Generator: nil}, + {Name: "amocas.w.aq", OpcodeMask: 4261441663, Opcode: 738205743, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 738205743, Generator: nil}, + {Name: "amocas.w.aqrl", OpcodeMask: 4261441663, Opcode: 771760175, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 771760175, Generator: nil}, + {Name: "amocas.w.rl", OpcodeMask: 4261441663, Opcode: 704651311, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 704651311, Generator: nil}, + {Name: "amocas.w", OpcodeMask: 4261441663, Opcode: 671096879, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 671096879, Generator: nil}, + {Name: "lb.aq", OpcodeMask: 4293947519, Opcode: 872415279, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 872415279, Generator: nil}, + {Name: "ld.aq", OpcodeMask: 4293947519, Opcode: 872427567, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 872427567, Generator: nil}, + {Name: "lh.aq", OpcodeMask: 4293947519, Opcode: 872419375, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 872419375, Generator: nil}, + {Name: "lw.aq", OpcodeMask: 4293947519, Opcode: 872423471, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 872423471, Generator: nil}, + {Name: "sb.rl", OpcodeMask: 4261445631, Opcode: 973078575, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 973078575, Generator: nil}, + {Name: "sd.rl", OpcodeMask: 4261445631, Opcode: 973090863, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 973090863, Generator: nil}, + {Name: "sh.rl", OpcodeMask: 4261445631, Opcode: 973082671, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 973082671, Generator: nil}, + {Name: "sw.rl", OpcodeMask: 4261445631, Opcode: 973086767, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + }, AsUInt32: 973086767, Generator: nil}, + {Name: "wrs.nto", OpcodeMask: 4294967295, Opcode: 13631603, AsUInt32: 13631603, Generator: nil}, + {Name: "wrs.sto", OpcodeMask: 4294967295, Opcode: 30408819, AsUInt32: 30408819, Generator: nil}, + {Name: "sh1add.uw", OpcodeMask: 4261441663, Opcode: 536879163, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 536879163, Generator: nil}, + {Name: "sh1add", OpcodeMask: 4261441663, Opcode: 536879155, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 536879155, Generator: nil}, + {Name: "sh2add.uw", OpcodeMask: 4261441663, Opcode: 536887355, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 536887355, Generator: nil}, + {Name: "sh2add", OpcodeMask: 4261441663, Opcode: 536887347, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 536887347, Generator: nil}, + {Name: "sh3add.uw", OpcodeMask: 4261441663, Opcode: 536895547, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 536895547, Generator: nil}, + {Name: "sh3add", OpcodeMask: 4261441663, Opcode: 536895539, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 536895539, Generator: nil}, + {Name: "slli.uw", OpcodeMask: 4227887231, Opcode: 134221851, Fields: []InsnField{ + {"shamt", 25, 6}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 134221851, Generator: nil}, + {Name: "clz", OpcodeMask: 4293947519, Opcode: 1610616851, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1610616851, Generator: nil}, + {Name: "clzw", OpcodeMask: 4293947519, Opcode: 1610616859, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1610616859, Generator: nil}, + {Name: "cpop", OpcodeMask: 4293947519, Opcode: 1612714003, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1612714003, Generator: nil}, + {Name: "cpopw", OpcodeMask: 4293947519, Opcode: 1612714011, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1612714011, Generator: nil}, + {Name: "ctz", OpcodeMask: 4293947519, Opcode: 1611665427, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1611665427, Generator: nil}, + {Name: "ctzw", OpcodeMask: 4293947519, Opcode: 1611665435, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1611665435, Generator: nil}, + {Name: "max", OpcodeMask: 4261441663, Opcode: 167796787, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 167796787, Generator: nil}, + {Name: "maxu", OpcodeMask: 4261441663, Opcode: 167800883, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 167800883, Generator: nil}, + {Name: "min", OpcodeMask: 4261441663, Opcode: 167788595, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 167788595, Generator: nil}, + {Name: "minu", OpcodeMask: 4261441663, Opcode: 167792691, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 167792691, Generator: nil}, + {Name: "orc.b", OpcodeMask: 4293947519, Opcode: 678449171, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 678449171, Generator: nil}, + {Name: "sext.b", OpcodeMask: 4293947519, Opcode: 1614811155, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1614811155, Generator: nil}, + {Name: "sext.h", OpcodeMask: 4293947519, Opcode: 1615859731, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1615859731, Generator: nil}, + {Name: "clmulr", OpcodeMask: 4261441663, Opcode: 167780403, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 167780403, Generator: nil}, + {Name: "brev8", OpcodeMask: 4293947519, Opcode: 1752190995, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1752190995, Generator: nil}, + {Name: "pack", OpcodeMask: 4261441663, Opcode: 134234163, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 134234163, Generator: nil}, + {Name: "packh", OpcodeMask: 4261441663, Opcode: 134246451, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 134246451, Generator: nil}, + {Name: "packw", OpcodeMask: 4261441663, Opcode: 134234171, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 134234171, Generator: nil}, + {Name: "unzip", OpcodeMask: 4293947519, Opcode: 149966867, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 149966867, Generator: nil}, + {Name: "zip", OpcodeMask: 4293947519, Opcode: 149950483, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 149950483, Generator: nil}, + {Name: "xperm4", OpcodeMask: 4261441663, Opcode: 671096883, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 671096883, Generator: nil}, + {Name: "xperm8", OpcodeMask: 4261441663, Opcode: 671105075, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 671105075, Generator: nil}, + {Name: "bclr", OpcodeMask: 4261441663, Opcode: 1207963699, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1207963699, Generator: nil}, + {Name: "bext", OpcodeMask: 4261441663, Opcode: 1207980083, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1207980083, Generator: nil}, + {Name: "binv", OpcodeMask: 4261441663, Opcode: 1744834611, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1744834611, Generator: nil}, + {Name: "bset", OpcodeMask: 4261441663, Opcode: 671092787, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 671092787, Generator: nil}, + {Name: "fli.s", OpcodeMask: 4293947519, Opcode: 4027580499, Fields: []InsnField{ + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 4027580499, Generator: nil}, + {Name: "fmaxm.s", OpcodeMask: 4261441663, Opcode: 671101011, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 671101011, Generator: nil}, + {Name: "fminm.s", OpcodeMask: 4261441663, Opcode: 671096915, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 671096915, Generator: nil}, + {Name: "fround.s", OpcodeMask: 4293918847, Opcode: 1077936211, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1077936211, Generator: nil}, + {Name: "froundnx.s", OpcodeMask: 4293918847, Opcode: 1078984787, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1078984787, Generator: nil}, + {Name: "fcvt.bf16.s", OpcodeMask: 4293918847, Opcode: 1149239379, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1149239379, Generator: nil}, + {Name: "fcvt.s.bf16", OpcodeMask: 4293918847, Opcode: 1080033363, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1080033363, Generator: nil}, + {Name: "fadd.h", OpcodeMask: 4261412991, Opcode: 67108947, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 67108947, Generator: nil}, + {Name: "fclass.h", OpcodeMask: 4293947519, Opcode: 3825209427, Fields: []InsnField{ + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3825209427, Generator: nil}, + {Name: "fcvt.d.h", OpcodeMask: 4293918847, Opcode: 1109393491, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1109393491, Generator: nil}, + {Name: "fcvt.h.d", OpcodeMask: 4293918847, Opcode: 1141899347, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1141899347, Generator: nil}, + {Name: "fcvt.h.l", OpcodeMask: 4293918847, Opcode: 3558867027, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3558867027, Generator: nil}, + {Name: "fcvt.h.lu", OpcodeMask: 4293918847, Opcode: 3559915603, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3559915603, Generator: nil}, + {Name: "fcvt.h.s", OpcodeMask: 4293918847, Opcode: 1140850771, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1140850771, Generator: nil}, + {Name: "fcvt.h.w", OpcodeMask: 4293918847, Opcode: 3556769875, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3556769875, Generator: nil}, + {Name: "fcvt.h.wu", OpcodeMask: 4293918847, Opcode: 3557818451, Fields: []InsnField{ + {"xs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 3557818451, Generator: nil}, + {Name: "fcvt.l.h", OpcodeMask: 4293918847, Opcode: 3290431571, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3290431571, Generator: nil}, + {Name: "fcvt.lu.h", OpcodeMask: 4293918847, Opcode: 3291480147, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3291480147, Generator: nil}, + {Name: "fcvt.s.h", OpcodeMask: 4293918847, Opcode: 1075839059, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1075839059, Generator: nil}, + {Name: "fcvt.w.h", OpcodeMask: 4293918847, Opcode: 3288334419, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3288334419, Generator: nil}, + {Name: "fcvt.wu.h", OpcodeMask: 4293918847, Opcode: 3289382995, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"xd", 11, 5}, + }, AsUInt32: 3289382995, Generator: nil}, + {Name: "fdiv.h", OpcodeMask: 4261412991, Opcode: 469762131, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 469762131, Generator: nil}, + {Name: "feq.h", OpcodeMask: 4261441663, Opcode: 2751471699, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2751471699, Generator: nil}, + {Name: "fle.h", OpcodeMask: 4261441663, Opcode: 2751463507, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2751463507, Generator: nil}, + {Name: "fleq.h", OpcodeMask: 4261441663, Opcode: 2751479891, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2751479891, Generator: nil}, + {Name: "flh", OpcodeMask: 28799, Opcode: 4103, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 4103, Generator: nil}, + {Name: "fli.h", OpcodeMask: 4293947519, Opcode: 4094689363, Fields: []InsnField{ + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 4094689363, Generator: nil}, + {Name: "flt.h", OpcodeMask: 4261441663, Opcode: 2751467603, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2751467603, Generator: nil}, + {Name: "fltq.h", OpcodeMask: 4261441663, Opcode: 2751483987, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2751483987, Generator: nil}, + {Name: "fmadd.h", OpcodeMask: 100663423, Opcode: 67108931, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 67108931, Generator: nil}, + {Name: "fmax.h", OpcodeMask: 4261441663, Opcode: 738201683, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 738201683, Generator: nil}, + {Name: "fmaxm.h", OpcodeMask: 4261441663, Opcode: 738209875, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 738209875, Generator: nil}, + {Name: "fmin.h", OpcodeMask: 4261441663, Opcode: 738197587, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 738197587, Generator: nil}, + {Name: "fminm.h", OpcodeMask: 4261441663, Opcode: 738205779, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 738205779, Generator: nil}, + {Name: "fmsub.h", OpcodeMask: 100663423, Opcode: 67108935, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 67108935, Generator: nil}, + {Name: "fmul.h", OpcodeMask: 4261412991, Opcode: 335544403, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 335544403, Generator: nil}, + {Name: "fmv.h.x", OpcodeMask: 4293947519, Opcode: 4093640787, Fields: []InsnField{ + {"xs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 4093640787, Generator: nil}, + {Name: "fmv.x.h", OpcodeMask: 4293947519, Opcode: 3825205331, Fields: []InsnField{ + {"fs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 3825205331, Generator: nil}, + {Name: "fnmadd.h", OpcodeMask: 100663423, Opcode: 67108943, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 67108943, Generator: nil}, + {Name: "fnmsub.h", OpcodeMask: 100663423, Opcode: 67108939, Fields: []InsnField{ + {"fs3", 31, 5}, + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 67108939, Generator: nil}, + {Name: "fround.h", OpcodeMask: 4293918847, Opcode: 1145045075, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1145045075, Generator: nil}, + {Name: "froundnx.h", OpcodeMask: 4293918847, Opcode: 1146093651, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1146093651, Generator: nil}, + {Name: "fsgnj.h", OpcodeMask: 4261441663, Opcode: 603979859, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 603979859, Generator: nil}, + {Name: "fsgnjn.h", OpcodeMask: 4261441663, Opcode: 603983955, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 603983955, Generator: nil}, + {Name: "fsgnjx.h", OpcodeMask: 4261441663, Opcode: 603988051, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"fd", 11, 5}, + }, AsUInt32: 603988051, Generator: nil}, + {Name: "fsh", OpcodeMask: 28799, Opcode: 4135, Fields: []InsnField{ + {"imm_31_25", 31, 7}, + {"imm_11_7", 11, 5}, + {"xs1", 19, 5}, + {"fs2", 24, 5}, + }, AsUInt32: 4135, Generator: nil}, + {Name: "fsqrt.h", OpcodeMask: 4293918847, Opcode: 1543503955, Fields: []InsnField{ + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 1543503955, Generator: nil}, + {Name: "fsub.h", OpcodeMask: 4261412991, Opcode: 201326675, Fields: []InsnField{ + {"fs2", 24, 5}, + {"fs1", 19, 5}, + {"rm", 14, 3}, + {"fd", 11, 5}, + }, AsUInt32: 201326675, Generator: nil}, + {Name: "cbo.clean", OpcodeMask: 4293951487, Opcode: 1056783, Fields: []InsnField{ + {"xs1", 19, 5}, + }, AsUInt32: 1056783, Generator: nil}, + {Name: "cbo.flush", OpcodeMask: 4293951487, Opcode: 2105359, Fields: []InsnField{ + {"xs1", 19, 5}, + }, AsUInt32: 2105359, Generator: nil}, + {Name: "cbo.inval", OpcodeMask: 4293951487, Opcode: 8207, Fields: []InsnField{ + {"xs1", 19, 5}, + }, AsUInt32: 8207, Generator: nil}, + {Name: "prefetch.i", OpcodeMask: 32538623, Opcode: 24595, Fields: []InsnField{ + {"imm", 31, 7}, + {"xs1", 19, 5}, + }, AsUInt32: 24595, Generator: nil}, + {Name: "prefetch.r", OpcodeMask: 32538623, Opcode: 1073171, Fields: []InsnField{ + {"imm", 31, 7}, + {"xs1", 19, 5}, + }, AsUInt32: 1073171, Generator: nil}, + {Name: "prefetch.w", OpcodeMask: 32538623, Opcode: 3170323, Fields: []InsnField{ + {"imm", 31, 7}, + {"xs1", 19, 5}, + }, AsUInt32: 3170323, Generator: nil}, + {Name: "cbo.zero", OpcodeMask: 4293951487, Opcode: 4202511, Fields: []InsnField{ + {"xs1", 19, 5}, + }, AsUInt32: 4202511, Generator: nil}, + {Name: "lpad", OpcodeMask: 4095, Opcode: 23, Fields: []InsnField{ + {"imm", 31, 20}, + }, AsUInt32: 23, Generator: nil}, + {Name: "ssamoswap.d", OpcodeMask: 4160778367, Opcode: 1207971887, Fields: []InsnField{ + {"aq", 26, 1}, + {"rl", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1207971887, Generator: nil}, + {Name: "ssamoswap.w", OpcodeMask: 4160778367, Opcode: 1207967791, Fields: []InsnField{ + {"aq", 26, 1}, + {"rl", 25, 1}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1207967791, Generator: nil}, + {Name: "sspopchk.x1", OpcodeMask: 4294967295, Opcode: 3451961459, AsUInt32: 3451961459, Generator: nil}, + {Name: "sspopchk.x5", OpcodeMask: 4294967295, Opcode: 3452092531, AsUInt32: 3452092531, Generator: nil}, + {Name: "sspush.x1", OpcodeMask: 4294967295, Opcode: 3457171571, AsUInt32: 3457171571, Generator: nil}, + {Name: "sspush.x5", OpcodeMask: 4294967295, Opcode: 3461365875, AsUInt32: 3461365875, Generator: nil}, + {Name: "ssrdp", OpcodeMask: 4294963327, Opcode: 3451928691, Fields: []InsnField{ + {"xd", 11, 5}, + }, AsUInt32: 3451928691, Generator: nil}, + {Name: "czero.eqz", OpcodeMask: 4261441663, Opcode: 234901555, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 234901555, Generator: nil}, + {Name: "czero.nez", OpcodeMask: 4261441663, Opcode: 234909747, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 234909747, Generator: nil}, + {Name: "csrrc", OpcodeMask: 28799, Opcode: 12403, Fields: []InsnField{ + {"csr", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 12403, Generator: nil}, + {Name: "csrrci", OpcodeMask: 28799, Opcode: 28787, Fields: []InsnField{ + {"csr", 31, 12}, + {"imm", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 28787, Generator: nil}, + {Name: "csrrs", OpcodeMask: 28799, Opcode: 8307, Fields: []InsnField{ + {"csr", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 8307, Generator: nil}, + {Name: "csrrsi", OpcodeMask: 28799, Opcode: 24691, Fields: []InsnField{ + {"csr", 31, 12}, + {"imm", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 24691, Generator: nil}, + {Name: "csrrw", OpcodeMask: 28799, Opcode: 4211, Fields: []InsnField{ + {"csr", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 4211, Generator: nil}, + {Name: "csrrwi", OpcodeMask: 28799, Opcode: 20595, Fields: []InsnField{ + {"csr", 31, 12}, + {"imm", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 20595, Generator: nil}, + {Name: "fence.i", OpcodeMask: 28799, Opcode: 4111, Fields: []InsnField{ + {"imm", 31, 12}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 4111, Generator: nil}, + {Name: "ntl.all", OpcodeMask: 4294967295, Opcode: 5242931, AsUInt32: 5242931, Generator: nil}, + {Name: "ntl.p1", OpcodeMask: 4294967295, Opcode: 2097203, AsUInt32: 2097203, Generator: nil}, + {Name: "ntl.pall", OpcodeMask: 4294967295, Opcode: 3145779, AsUInt32: 3145779, Generator: nil}, + {Name: "ntl.s1", OpcodeMask: 4294967295, Opcode: 4194355, AsUInt32: 4194355, Generator: nil}, + {Name: "aes64ks1i", OpcodeMask: 4278218879, Opcode: 822087699, Fields: []InsnField{ + {"rnum", 23, 4}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 822087699, Generator: nil}, + {Name: "aes64ks2", OpcodeMask: 4261441663, Opcode: 2113929267, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 2113929267, Generator: nil}, + {Name: "aes32dsi", OpcodeMask: 1040216191, Opcode: 704643123, Fields: []InsnField{ + {"bs", 31, 2}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 704643123, Generator: nil}, + {Name: "aes32dsmi", OpcodeMask: 1040216191, Opcode: 771751987, Fields: []InsnField{ + {"bs", 31, 2}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 771751987, Generator: nil}, + {Name: "aes64ds", OpcodeMask: 4261441663, Opcode: 973078579, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 973078579, Generator: nil}, + {Name: "aes64dsm", OpcodeMask: 4261441663, Opcode: 1040187443, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1040187443, Generator: nil}, + {Name: "aes64im", OpcodeMask: 4293947519, Opcode: 805310483, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 805310483, Generator: nil}, + {Name: "aes32esi", OpcodeMask: 1040216191, Opcode: 570425395, Fields: []InsnField{ + {"bs", 31, 2}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 570425395, Generator: nil}, + {Name: "aes32esmi", OpcodeMask: 1040216191, Opcode: 637534259, Fields: []InsnField{ + {"bs", 31, 2}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 637534259, Generator: nil}, + {Name: "aes64es", OpcodeMask: 4261441663, Opcode: 838860851, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 838860851, Generator: nil}, + {Name: "aes64esm", OpcodeMask: 4261441663, Opcode: 905969715, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 905969715, Generator: nil}, + {Name: "sha256sig0", OpcodeMask: 4293947519, Opcode: 270536723, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 270536723, Generator: nil}, + {Name: "sha256sig1", OpcodeMask: 4293947519, Opcode: 271585299, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 271585299, Generator: nil}, + {Name: "sha256sum0", OpcodeMask: 4293947519, Opcode: 268439571, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 268439571, Generator: nil}, + {Name: "sha256sum1", OpcodeMask: 4293947519, Opcode: 269488147, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 269488147, Generator: nil}, + {Name: "sha512sig0", OpcodeMask: 4293947519, Opcode: 274731027, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 274731027, Generator: nil}, + {Name: "sha512sig0h", OpcodeMask: 4261441663, Opcode: 1543503923, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1543503923, Generator: nil}, + {Name: "sha512sig0l", OpcodeMask: 4261441663, Opcode: 1409286195, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1409286195, Generator: nil}, + {Name: "sha512sig1", OpcodeMask: 4293947519, Opcode: 275779603, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 275779603, Generator: nil}, + {Name: "sha512sig1h", OpcodeMask: 4261441663, Opcode: 1577058355, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1577058355, Generator: nil}, + {Name: "sha512sig1l", OpcodeMask: 4261441663, Opcode: 1442840627, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1442840627, Generator: nil}, + {Name: "sha512sum0", OpcodeMask: 4293947519, Opcode: 272633875, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 272633875, Generator: nil}, + {Name: "sha512sum0r", OpcodeMask: 4261441663, Opcode: 1342177331, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1342177331, Generator: nil}, + {Name: "sha512sum1", OpcodeMask: 4293947519, Opcode: 273682451, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 273682451, Generator: nil}, + {Name: "sha512sum1r", OpcodeMask: 4261441663, Opcode: 1375731763, Fields: []InsnField{ + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 1375731763, Generator: nil}, + {Name: "sm3p0", OpcodeMask: 4293947519, Opcode: 276828179, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 276828179, Generator: nil}, + {Name: "sm3p1", OpcodeMask: 4293947519, Opcode: 277876755, Fields: []InsnField{ + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 277876755, Generator: nil}, + {Name: "sm4ed", OpcodeMask: 1040216191, Opcode: 805306419, Fields: []InsnField{ + {"bs", 31, 2}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 805306419, Generator: nil}, + {Name: "sm4ks", OpcodeMask: 1040216191, Opcode: 872415283, Fields: []InsnField{ + {"bs", 31, 2}, + {"xs2", 24, 5}, + {"xs1", 19, 5}, + {"xd", 11, 5}, + }, AsUInt32: 872415283, Generator: nil}, + {Name: "vandn.vv", OpcodeMask: 4227887231, Opcode: 67108951, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 67108951, Generator: nil}, + {Name: "vandn.vx", OpcodeMask: 4227887231, Opcode: 67125335, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 67125335, Generator: nil}, + {Name: "vbrev.v", OpcodeMask: 4228903039, Opcode: 1208295511, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208295511, Generator: nil}, + {Name: "vbrev8.v", OpcodeMask: 4228903039, Opcode: 1208229975, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208229975, Generator: nil}, + {Name: "vclz.v", OpcodeMask: 4228903039, Opcode: 1208361047, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208361047, Generator: nil}, + {Name: "vcpop.v", OpcodeMask: 4228903039, Opcode: 1208426583, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208426583, Generator: nil}, + {Name: "vctz.v", OpcodeMask: 4228903039, Opcode: 1208393815, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208393815, Generator: nil}, + {Name: "vrev8.v", OpcodeMask: 4228903039, Opcode: 1208262743, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208262743, Generator: nil}, + {Name: "vrol.vv", OpcodeMask: 4227887231, Opcode: 1409286231, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1409286231, Generator: nil}, + {Name: "vrol.vx", OpcodeMask: 4227887231, Opcode: 1409302615, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1409302615, Generator: nil}, + {Name: "vror.vv", OpcodeMask: 4227887231, Opcode: 1342177367, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1342177367, Generator: nil}, + {Name: "vror.vx", OpcodeMask: 4227887231, Opcode: 1342193751, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1342193751, Generator: nil}, + {Name: "vwsll.vi", OpcodeMask: 4227887231, Opcode: 3556782167, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3556782167, Generator: nil}, + {Name: "vwsll.vv", OpcodeMask: 4227887231, Opcode: 3556769879, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3556769879, Generator: nil}, + {Name: "vwsll.vx", OpcodeMask: 4227887231, Opcode: 3556786263, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3556786263, Generator: nil}, + {Name: "vclmul.vv", OpcodeMask: 4227887231, Opcode: 805314647, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 805314647, Generator: nil}, + {Name: "vclmul.vx", OpcodeMask: 4227887231, Opcode: 805331031, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 805331031, Generator: nil}, + {Name: "vclmulh.vv", OpcodeMask: 4227887231, Opcode: 872423511, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 872423511, Generator: nil}, + {Name: "vclmulh.vx", OpcodeMask: 4227887231, Opcode: 872439895, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"xs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 872439895, Generator: nil}, + {Name: "vfncvtbf16.f.f.w", OpcodeMask: 4228903039, Opcode: 1208914007, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208914007, Generator: nil}, + {Name: "vfwcvtbf16.f.f.v", OpcodeMask: 4228903039, Opcode: 1208389719, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 1208389719, Generator: nil}, + {Name: "vfwmaccbf16.vf", OpcodeMask: 4227887231, Opcode: 3959443543, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"fs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3959443543, Generator: nil}, + {Name: "vfwmaccbf16.vv", OpcodeMask: 4227887231, Opcode: 3959427159, Fields: []InsnField{ + {"vm", 25, 1}, + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3959427159, Generator: nil}, + {Name: "vghsh.vv", OpcodeMask: 4261441663, Opcode: 2986352759, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2986352759, Generator: nil}, + {Name: "vgmul.vv", OpcodeMask: 4262457471, Opcode: 2718474359, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2718474359, Generator: nil}, + {Name: "vaesdf.vs", OpcodeMask: 4262457471, Opcode: 2785058935, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2785058935, Generator: nil}, + {Name: "vaesdf.vv", OpcodeMask: 4262457471, Opcode: 2717950071, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2717950071, Generator: nil}, + {Name: "vaesdm.vs", OpcodeMask: 4262457471, Opcode: 2785026167, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2785026167, Generator: nil}, + {Name: "vaesdm.vv", OpcodeMask: 4262457471, Opcode: 2717917303, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2717917303, Generator: nil}, + {Name: "vaesef.vs", OpcodeMask: 4262457471, Opcode: 2785124471, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2785124471, Generator: nil}, + {Name: "vaesef.vv", OpcodeMask: 4262457471, Opcode: 2718015607, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2718015607, Generator: nil}, + {Name: "vaesem.vs", OpcodeMask: 4262457471, Opcode: 2785091703, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2785091703, Generator: nil}, + {Name: "vaesem.vv", OpcodeMask: 4262457471, Opcode: 2717982839, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2717982839, Generator: nil}, + {Name: "vaeskf1.vi", OpcodeMask: 4261441663, Opcode: 2315264119, Fields: []InsnField{ + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2315264119, Generator: nil}, + {Name: "vaeskf2.vi", OpcodeMask: 4261441663, Opcode: 2852135031, Fields: []InsnField{ + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2852135031, Generator: nil}, + {Name: "vaesz.vs", OpcodeMask: 4262457471, Opcode: 2785255543, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2785255543, Generator: nil}, + {Name: "vsha2ch.vv", OpcodeMask: 4261441663, Opcode: 3120570487, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3120570487, Generator: nil}, + {Name: "vsha2cl.vv", OpcodeMask: 4261441663, Opcode: 3187679351, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3187679351, Generator: nil}, + {Name: "vsha2ms.vv", OpcodeMask: 4261441663, Opcode: 3053461623, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 3053461623, Generator: nil}, + {Name: "vsm3c.vi", OpcodeMask: 4261441663, Opcode: 2919243895, Fields: []InsnField{ + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2919243895, Generator: nil}, + {Name: "vsm3me.vv", OpcodeMask: 4261441663, Opcode: 2181046391, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vs1", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2181046391, Generator: nil}, + {Name: "vsm4k.vi", OpcodeMask: 4261441663, Opcode: 2248155255, Fields: []InsnField{ + {"vs2", 24, 5}, + {"imm", 19, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2248155255, Generator: nil}, + {Name: "vsm4r.vs", OpcodeMask: 4262457471, Opcode: 2785550455, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2785550455, Generator: nil}, + {Name: "vsm4r.vv", OpcodeMask: 4262457471, Opcode: 2718441591, Fields: []InsnField{ + {"vs2", 24, 5}, + {"vd", 11, 5}, + }, AsUInt32: 2718441591, Generator: nil}, +} diff --git a/pkg/ifuzz/riscv64/pseudo.go b/pkg/ifuzz/riscv64/pseudo.go new file mode 100644 index 000000000000..c87c02dd0600 --- /dev/null +++ b/pkg/ifuzz/riscv64/pseudo.go @@ -0,0 +1,8 @@ +// Copyright 2026 syzkaller project authors. All rights reserved. +// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file. + +// Pseudo instructions for riscv64 architecture. + +package riscv64 + +var pseudo = []*Insn{} diff --git a/pkg/ifuzz/riscv64/riscv64.go b/pkg/ifuzz/riscv64/riscv64.go new file mode 100644 index 000000000000..bed0380ed948 --- /dev/null +++ b/pkg/ifuzz/riscv64/riscv64.go @@ -0,0 +1,116 @@ +// Copyright 2026 syzkaller project authors. All rights reserved. +// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file. + +//go:generate go run gen/gen.go gen/inst generated/insns.go + +// Package riscv64 allows to generate and mutate riscv64 machine code. +package riscv64 + +import ( + "encoding/binary" + "fmt" + "math/rand" + + "github.com/google/syzkaller/pkg/ifuzz/iset" +) + +type InsnField struct { + Name string + Start uint // Little endian bit order. + Length uint +} + +type Insn struct { + Name string + OpcodeMask uint32 + Opcode uint32 + Fields []InsnField + AsUInt32 uint32 + Operands []uint32 + Pseudo bool + Priv bool + Generator func(cfg *iset.Config, r *rand.Rand) []byte // for pseudo instructions +} + +type InsnSet struct { + modeInsns iset.ModeInsns + Insns []*Insn +} + +func Register(insns []*Insn) { + if len(insns) == 0 { + panic("no instructions") + } + insnset := &InsnSet{ + Insns: append(insns, pseudo...), + } + for _, insn := range insnset.Insns { + insnset.modeInsns.Add(insn) + } + iset.Arches[iset.ArchRiscv64] = insnset + templates = insns +} + +func (insnset *InsnSet) GetInsns(mode iset.Mode, typ iset.Type) []iset.Insn { + return insnset.modeInsns[mode][typ] +} + +func (insn *Insn) Info() (string, iset.Mode, bool, bool) { + return insn.Name, 1 << iset.ModeLong64, insn.Pseudo, insn.Priv +} + +func (insn *Insn) Encode(cfg *iset.Config, r *rand.Rand) []byte { + if insn.Pseudo { + return insn.Generator(cfg, r) + } + ret := make([]byte, 4) + binary.LittleEndian.PutUint32(ret, insn.AsUInt32) + return ret +} + +func (insnset *InsnSet) Decode(mode iset.Mode, text []byte) (int, error) { + if len(text) < 4 { + return 0, fmt.Errorf("must be at least 4 bytes") + } + opcode := binary.LittleEndian.Uint32(text[:4]) + _, err := ParseInsn(opcode) + if err != nil { + return 0, fmt.Errorf("failed to decode %x", opcode) + } + return 4, nil +} + +func (insnset *InsnSet) DecodeExt(mode iset.Mode, text []byte) (int, error) { + return 0, fmt.Errorf("no external decoder") +} + +var templates []*Insn + +func (insn *Insn) initFromValue(val uint32) { + operands := []uint32{} + for _, field := range insn.Fields { + extracted := extractBits(val, field.Start, field.Length) + operands = append(operands, extracted) + } + insn.Operands = operands + insn.AsUInt32 = val +} + +func (insn *Insn) matchesValue(val uint32) bool { + opcode := val & insn.OpcodeMask + return opcode == insn.Opcode +} + +func ParseInsn(val uint32) (Insn, error) { + for _, tmpl := range templates { + if tmpl.matchesValue(val) { + newInsn := *tmpl + newInsn.initFromValue(val) + return newInsn, nil + } + } + unknown := Insn{ + Name: "unknown", + } + return unknown, fmt.Errorf("unrecognized instruction: %08x", val) +} diff --git a/pkg/ifuzz/riscv64/util.go b/pkg/ifuzz/riscv64/util.go new file mode 100644 index 000000000000..efa395ffa578 --- /dev/null +++ b/pkg/ifuzz/riscv64/util.go @@ -0,0 +1,9 @@ +// Copyright 2026 syzkaller project authors. All rights reserved. +// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file. + +package riscv64 + +func extractBits(from uint32, start, size uint) uint32 { + mask := uint32((1 << size) - 1) + return (from >> (start - size + 1)) & mask +} diff --git a/pkg/ifuzz/riscv64/util_test.go b/pkg/ifuzz/riscv64/util_test.go new file mode 100644 index 000000000000..554ffca126b4 --- /dev/null +++ b/pkg/ifuzz/riscv64/util_test.go @@ -0,0 +1,35 @@ +// Copyright 2026 syzkaller project authors. All rights reserved. +// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file. + +package riscv64 + +import "testing" + +func extractBitsOne(t *testing.T, from uint32, start, size uint, expect uint32) { + ret := extractBits(from, start, size) + if ret != expect { + t.Fatalf("extractBits(%08x, %d, %d) = %x, want %x", + from, start, size, ret, expect) + } +} + +func TestExtractBits(t *testing.T) { + extractBitsOne(t, 0, 0, 0, 0) + extractBitsOne(t, 0xffffffff, 0, 0, 0) + + for i := uint(0); i <= 31; i++ { + extractBitsOne(t, 0xffffffff, i, 1, 1) + } + + extractBitsOne(t, 0xf0f0f0f0, 31, 5, 0b11110) + + extractBitsOne(t, 0xf0f0f0f0, 25, 4, 0b0011) + + extractBitsOne(t, 0xf0f0f0f0, 21, 4, 0b1100) + + val := uint32(0b0000000_00011_00010_000_00001_0110011) + + extractBitsOne(t, val, 24, 5, 3) + extractBitsOne(t, val, 19, 5, 2) + extractBitsOne(t, val, 11, 5, 1) +} diff --git a/pkg/ifuzz/riscv64_test.go b/pkg/ifuzz/riscv64_test.go new file mode 100644 index 000000000000..9c8ebc443cb1 --- /dev/null +++ b/pkg/ifuzz/riscv64_test.go @@ -0,0 +1,95 @@ +// Copyright 2026 syzkaller project authors. All rights reserved. +// Use of this source code is governed by Apache 2 LICENSE that can be found in the LICENSE file. + +package ifuzz + +import ( + "encoding/binary" + "encoding/hex" + "fmt" + "strconv" + "testing" + + "github.com/google/syzkaller/pkg/ifuzz/iset" + "github.com/google/syzkaller/pkg/ifuzz/riscv64" +) + +func PrintInsnRv(insn riscv64.Insn) { + operands := "" + for i, op := range insn.Operands { + field := insn.Fields[i] + operands += fmt.Sprintf("%s:%d=%x ", field.Name, field.Length, op) + } + fmt.Printf("{ \"%s\" [0x%x] %s }\n", insn.Name, insn.AsUInt32, operands) +} + +func parseAndPrintRv(from uint32) { + insn, _ := riscv64.ParseInsn(from) + PrintInsnRv(insn) +} + +func TestSomethingRv(t *testing.T) { + // add a0,a0,a1 + parseAndPrintRv(0x00b50533) + // li t0,0 + parseAndPrintRv(0x00000293) + // mul a0,a0,a1 + parseAndPrintRv(0x02b50533) + // csrr a0,sstatus + parseAndPrintRv(0x10002573) + // ecall + parseAndPrintRv(0x00000073) +} + +func TestSumRv(t *testing.T) { + data := [][2]string{ + {"00100073", "ebreak"}, + {"18029073", "csrw satp,t0"}, + {"c01025f3", "rdtime a1"}, + {"c0002573", "rdcycle a0"}, + {"02b56533", "rem a0,a0,a1"}, + {"02b54533", "div a0,a0,a1"}, + {"00030513", "mv a0,t1"}, + {"00c5a023", "sw a2,0(a1)"}, + } + for _, pair := range data { + opcode, err := strconv.ParseUint(pair[0], 16, 32) + if err != nil { + t.Fatalf("failed to parse opcode") + } + fmt.Printf("%s\n", pair[1]) + parseAndPrintRv(uint32(opcode)) + } +} + +func decodeRvText(t *testing.T, insnset iset.InsnSet, text []byte) { + for len(text) > 0 { + size, err := insnset.Decode(iset.ModeLong64, text) + if size == 0 || err != nil { + t.Errorf("failed to decode text: %v", text) + return + } + parseAndPrintRv(binary.LittleEndian.Uint32(text[:4])) + text = text[size:] + } +} + +func TestDecodeSamplesRv(t *testing.T) { + testData := []string{ + "7300100073900918", + "f32510c0732500c0", + "3365b5023345b502", + "1305030023a0c500", + // 007302b3 -> add t0, t1, t2 -> "add" [0x7302b3] xs2:5=7 xs1:5=6 xd:5=5 + "b3027300", + } + insnset := iset.Arches["riscv64"] + for _, str := range testData { + text, err := hex.DecodeString(str) + if err != nil { + t.Fatalf("invalid hex string") + } + fmt.Printf("Decoding % x\n", text) + decodeRvText(t, insnset, text) + } +} diff --git a/prog/rand.go b/prog/rand.go index 834003914fe0..f476c474bd73 100644 --- a/prog/rand.go +++ b/prog/rand.go @@ -578,6 +578,13 @@ func createIfuzzConfig(kind TextKind) *ifuzz.Config { case TextArm64: cfg.Mode = ifuzz.ModeLong64 cfg.Arch = ifuzz.ArchArm64 + case TextRiscv64: + cfg.Mode = ifuzz.ModeLong64 + cfg.Arch = ifuzz.ArchRiscv64 + // For riscv64, ifuzz currently has no pseudo-instructions + // and does not handle privileged instructions. + cfg.Priv = false + cfg.Exec = false default: panic(fmt.Sprintf("unknown text kind: %v", kind)) } diff --git a/prog/types.go b/prog/types.go index 1d636fbda68f..ee984965fa4f 100644 --- a/prog/types.go +++ b/prog/types.go @@ -652,6 +652,7 @@ const ( TextX86bit64 TextArm64 TextPpc64 + TextRiscv64 ) type BufferType struct {