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DSLX DMA: Draft implementation
Signed-off-by: Michal Czyz <[email protected]>
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‎xls/modules/dma/BUILD

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# Copyright 2023 The XLS Authors
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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load(
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"//xls/build_rules:xls_build_defs.bzl",
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"xls_dslx_ir",
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"xls_dslx_library",
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"xls_dslx_test",
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"xls_ir_opt_ir",
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"xls_ir_verilog",
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)
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package(
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default_applicable_licenses = ["//:license"],
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default_visibility = ["//xls:xls_users"],
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licenses = ["notice"],
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)
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# Common
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xls_dslx_library(
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name = "dma_common",
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srcs = [
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"bus/axi_pkg.x",
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"bus/axi_st_pkg.x",
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"common.x",
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"config.x",
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"gpf.x",
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],
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)
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xls_dslx_test(
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name = "test_common",
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library = "dma_common",
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)
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# CSR
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xls_dslx_library(
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name = "csr",
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srcs = [
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"csr.x",
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],
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deps = [
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":dma_common",
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],
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)
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xls_dslx_test(
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name = "test_csr",
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library = "csr",
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)
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xls_dslx_ir(
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name = "ir_csr_8_32_14",
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dslx_top = "csr_8_32_14",
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ir_file = "csr_8_32_14.ir",
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library = "csr",
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)
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xls_ir_opt_ir(
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name = "opt_ir_csr_8_32_14",
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src = "csr_8_32_14.ir",
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top = "__csr__csr_8_32_14__CSR_0__8_32_14_next",
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)
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xls_ir_verilog(
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name = "verilog_csr",
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src = ":opt_ir_csr_8_32_14.opt.ir",
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codegen_args = {
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"module_name": "csr",
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"delay_model": "unit",
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"pipeline_stages": "2",
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"reset": "rst",
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"use_system_verilog": "false",
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},
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verilog_file = "csr.v",
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)
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# AXI CSR
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xls_dslx_library(
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name = "axi_csr",
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srcs = [
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"axi_csr.x",
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],
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deps = [
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":csr",
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":dma_common",
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],
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)
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xls_dslx_test(
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name = "test_axi_csr",
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library = "axi_csr",
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)
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xls_dslx_ir(
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name = "axi_csr_8_32_14_ir",
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dslx_top = "axi_csr_8_32_14",
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ir_file = "axi_csr_8_32_14.ir",
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library = "axi_csr",
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)
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xls_ir_opt_ir(
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name = "axi_csr_8_32_14_opt_ir",
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src = "axi_csr_8_32_14.ir",
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top = "__axi_csr__axi_csr_8_32_14__axi_csr_0__8_32_4_14_4_next",
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)
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xls_ir_verilog(
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name = "verilog_axi_csr",
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src = ":axi_csr_8_32_14_opt_ir.opt.ir",
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codegen_args = {
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"module_name": "axi_csr",
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"delay_model": "unit",
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"pipeline_stages": "4",
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"reset": "rst",
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"use_system_verilog": "false",
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},
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verilog_file = "axi_csr.v",
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)
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# FIFO
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xls_dslx_library(
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name = "fifo",
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srcs = [
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"fifo.x",
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],
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deps = [
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":dma_common",
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"//xls/examples:ram_dslx",
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],
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)
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xls_dslx_test(
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name = "test_fifo",
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library = "fifo",
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)
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# xls_dslx_ir(
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# name = "fifo_ir",
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# dslx_top = "fifo_synth",
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# ir_file = "fifo_ir.ir",
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# library = "fifo",
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# )
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# xls_ir_opt_ir(
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# name = "fifo_ir_opt",
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# src = "fifo_ir.ir",
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# # FIXME: Top level is not correctly generated in verilog
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# top = "__fifo__fifo_synth__FIFO__Writer_0__4_8_1_1_16_1_next"
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# )
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# xls_ir_verilog(
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# name = "verilog_fifo",
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# src = ":fifo_ir_opt.opt.ir",
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# codegen_args = {
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# "module_name": "fifo",
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# "delay_model": "unit",
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# "pipeline_stages": "3",
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# "worst_case_throughput": "2",
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# "reset": "rst",
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# "use_system_verilog": "false",
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# # TODO: setup configuration for RAM macro generation
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# # https://google.github.io/xls/codegen_options/#rams-experimental
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# # https://github.com/google/xls/blob/609a7ab89d96d2a7396d2418d00d30e4cb57b119/xls/codegen/ram_configuration.h#L99
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# # https://github.com/google/xls/blob/609a7ab89d96d2a7396d2418d00d30e4cb57b119/docs_src/tutorials/xlscc_memory.md?plain=1#L140
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# },
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# verilog_file = "fifo.v",
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# )
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# Address Generator
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xls_dslx_library(
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name = "address_generator_lib",
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srcs = [
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"address_generator.x",
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],
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deps = [
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":dma_common",
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],
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)
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xls_dslx_test(
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name = "test_address_generator",
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library = "address_generator_lib",
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)
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# Frontend Reader
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xls_dslx_library(
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name = "frontend_reader_lib",
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srcs = [
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"frontend_reader.x",
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],
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deps = [
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":dma_common",
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],
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)
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xls_dslx_test(
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name = "test_frontend_reader",
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library = "frontend_reader_lib",
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)
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# Frontend writer
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xls_dslx_library(
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name = "frontend_writer_lib",
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srcs = [
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"frontend_writer.x",
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],
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deps = [
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":dma_common",
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],
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)
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xls_dslx_test(
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name = "test_frontend_writer",
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library = "frontend_writer_lib",
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)
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# TODO: Uncomment recipce once ready for testing
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# Main controller
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# xls_dslx_library(
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# name = 'main_controller_lib',
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# srcs = [
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# 'main_controller.x',
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# ],
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# )
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# xls_dslx_test(
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# name = "test_main_controller",
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# library = "main_controller_lib",
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# )

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