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meheffernan
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Add test with channel declared in a proc.
The channel results in a FIFO instantiation connected two instantiated procs. No functional change to codegen required. Also, create a test-only RTL FIFO library out of existing test FIFOs in block_generator_test. PiperOrigin-RevId: 740921106
1 parent ce7366d commit ed2b774

6 files changed

+561
-212
lines changed

‎xls/codegen/BUILD

+10
Original file line numberDiff line numberDiff line change
@@ -1000,6 +1000,7 @@ cc_test(
10001000
":module_signature",
10011001
":module_signature_cc_proto",
10021002
":pipeline_generator",
1003+
":test_fifos",
10031004
"//xls/common:golden_files",
10041005
"//xls/common:xls_gunit_main",
10051006
"//xls/common/status:matchers",
@@ -1019,6 +1020,7 @@ cc_test(
10191020
"//xls/simulation:module_simulator",
10201021
"//xls/simulation:module_testbench",
10211022
"//xls/simulation:module_testbench_thread",
1023+
"//xls/simulation:verilog_include",
10221024
"//xls/simulation:verilog_test_base",
10231025
"@com_google_absl//absl/container:flat_hash_map",
10241026
"@com_google_absl//absl/status",
@@ -1266,6 +1268,7 @@ cc_test(
12661268
":module_signature",
12671269
":op_override_impls",
12681270
":signature_generator",
1271+
":test_fifos",
12691272
"//xls/common:xls_gunit_main",
12701273
"//xls/common/logging:log_lines",
12711274
"//xls/common/status:matchers",
@@ -2017,6 +2020,13 @@ cc_test(
20172020
],
20182021
)
20192022

2023+
cc_library(
2024+
name = "test_fifos",
2025+
testonly = True,
2026+
hdrs = ["test_fifos.h"],
2027+
deps = ["//xls/ir:channel"],
2028+
)
2029+
20202030
# Test that codegen args work correctly in our rules.
20212031
xls_ir_verilog(
20222032
name = "assertions_multiple_ifdef_guards",

‎xls/codegen/block_generator_test.cc

+24-212
Original file line numberDiff line numberDiff line change
@@ -43,6 +43,7 @@
4343
#include "xls/codegen/module_signature.h"
4444
#include "xls/codegen/op_override_impls.h"
4545
#include "xls/codegen/signature_generator.h"
46+
#include "xls/codegen/test_fifos.h"
4647
#include "xls/common/logging/log_lines.h"
4748
#include "xls/common/status/matchers.h"
4849
#include "xls/common/status/ret_check.h"
@@ -91,178 +92,6 @@ using ::testing::HasSubstr;
9192
constexpr char kTestName[] = "block_generator_test";
9293
constexpr char kTestdataPath[] = "xls/codegen/testdata";
9394

94-
inline constexpr std::string_view kDepth1FifoRTLText =
95-
R"(// simple fifo depth-1 implementation
96-
module xls_fifo_wrapper (
97-
clk, rst,
98-
push_ready, push_data, push_valid,
99-
pop_ready, pop_data, pop_valid);
100-
parameter Width = 32,
101-
Depth = 32,
102-
EnableBypass = 0,
103-
RegisterPushOutputs = 1,
104-
RegisterPopOutputs = 1;
105-
localparam AddrWidth = $clog2(Depth) + 1;
106-
input wire clk;
107-
input wire rst;
108-
output wire push_ready;
109-
input wire [Width-1:0] push_data;
110-
input wire push_valid;
111-
input wire pop_ready;
112-
output wire [Width-1:0] pop_data;
113-
output wire pop_valid;
114-
115-
// Require depth be 1 and bypass disabled.
116-
initial begin
117-
if (EnableBypass || Depth != 1 || !RegisterPushOutputs || RegisterPopOutputs) begin
118-
// FIFO configuration not supported.
119-
$fatal(1);
120-
end
121-
end
122-
123-
124-
reg [Width-1:0] mem;
125-
reg full;
126-
127-
assign push_ready = !full;
128-
assign pop_valid = full;
129-
assign pop_data = mem;
130-
131-
always @(posedge clk) begin
132-
if (rst == 1'b1) begin
133-
full <= 1'b0;
134-
end else begin
135-
if (push_valid && push_ready) begin
136-
mem <= push_data;
137-
full <= 1'b1;
138-
end else if (pop_valid && pop_ready) begin
139-
mem <= mem;
140-
full <= 1'b0;
141-
end else begin
142-
mem <= mem;
143-
full <= full;
144-
end
145-
end
146-
end
147-
endmodule
148-
)";
149-
150-
inline constexpr std::string_view kDepth1NoDataFifoRTLText =
151-
R"(// simple nodata fifo depth-1 implementation
152-
module xls_nodata_fifo_wrapper (
153-
clk, rst,
154-
push_ready, push_valid,
155-
pop_ready, pop_valid);
156-
parameter Depth = 32,
157-
EnableBypass = 0,
158-
RegisterPushOutputs = 1,
159-
RegisterPopOutputs = 1;
160-
localparam AddrWidth = $clog2(Depth) + 1;
161-
input wire clk;
162-
input wire rst;
163-
output wire push_ready;
164-
input wire push_valid;
165-
input wire pop_ready;
166-
output wire pop_valid;
167-
168-
// Require depth be 1 and bypass disabled.
169-
initial begin
170-
if (EnableBypass || Depth != 1 || !RegisterPushOutputs || RegisterPopOutputs) begin
171-
// FIFO configuration not supported.
172-
$fatal(1);
173-
end
174-
end
175-
176-
reg full;
177-
178-
assign push_ready = !full;
179-
assign pop_valid = full;
180-
181-
always @(posedge clk) begin
182-
if (rst == 1'b1) begin
183-
full <= 1'b0;
184-
end else begin
185-
if (push_valid && push_ready) begin
186-
full <= 1'b1;
187-
end else if (pop_valid && pop_ready) begin
188-
full <= 1'b0;
189-
end else begin
190-
full <= full;
191-
end
192-
end
193-
end
194-
endmodule
195-
)";
196-
197-
inline constexpr std::string_view kDepth0FifoRTLText =
198-
R"(// simple fifo depth-1 implementation
199-
module xls_fifo_wrapper (
200-
clk, rst,
201-
push_ready, push_data, push_valid,
202-
pop_ready, pop_data, pop_valid);
203-
parameter Width = 32,
204-
Depth = 32,
205-
EnableBypass = 0,
206-
RegisterPushOutputs = 1,
207-
RegisterPopOutputs = 1;
208-
localparam AddrWidth = $clog2(Depth) + 1;
209-
input wire clk;
210-
input wire rst;
211-
output wire push_ready;
212-
input wire [Width-1:0] push_data;
213-
input wire push_valid;
214-
input wire pop_ready;
215-
output wire [Width-1:0] pop_data;
216-
output wire pop_valid;
217-
218-
// Require depth be 1 and bypass disabled.
219-
initial begin
220-
if (EnableBypass != 1 || Depth != 0 || RegisterPushOutputs || RegisterPopOutputs) begin
221-
// FIFO configuration not supported.
222-
$fatal(1);
223-
end
224-
end
225-
226-
227-
assign push_ready = pop_ready;
228-
assign pop_valid = push_valid;
229-
assign pop_data = push_data;
230-
231-
endmodule
232-
)";
233-
234-
inline constexpr std::string_view kDepth0NoDataFifoRTLText =
235-
R"(// simple nodata fifo depth-1 implementation
236-
module xls_nodata_fifo_wrapper (
237-
clk, rst,
238-
push_ready, push_valid,
239-
pop_ready, pop_valid);
240-
parameter Depth = 32,
241-
EnableBypass = 0,
242-
RegisterPushOutputs = 1,
243-
RegisterPopOutputs = 1;
244-
localparam AddrWidth = $clog2(Depth) + 1;
245-
input wire clk;
246-
input wire rst;
247-
output wire push_ready;
248-
input wire push_valid;
249-
input wire pop_ready;
250-
output wire pop_valid;
251-
252-
// Require depth be 1 and bypass disabled.
253-
initial begin
254-
if (EnableBypass != 1 || Depth != 0 || RegisterPushOutputs || RegisterPopOutputs) begin
255-
// FIFO configuration not supported.
256-
$fatal(1);
257-
end
258-
end
259-
260-
assign push_ready = pop_ready;
261-
assign pop_valid = push_valid;
262-
263-
endmodule
264-
)";
265-
26695
class BlockGeneratorTest : public VerilogTestBase {
26796
protected:
26897
CodegenOptions codegen_options(
@@ -1701,9 +1530,8 @@ proc running_sum(first_cycle: bits[1], init={1}) {
17011530

17021531
verilog = absl::StrCat("`include \"fifo.v\"\n\n", verilog);
17031532

1704-
VerilogInclude fifo_definition{
1705-
.relative_path = "fifo.v",
1706-
.verilog_text = std::string{kDepth1FifoRTLText}};
1533+
VerilogInclude fifo_definition{.relative_path = "fifo.v",
1534+
.verilog_text = kDepth1Fifo.rtl};
17071535

17081536
ExpectVerilogEqualToGoldenFile(GoldenFilePath(kTestName, kTestdataPath),
17091537
verilog, /*macro_definitions=*/{},
@@ -2009,15 +1837,11 @@ proc lookup_proc(x: bits[1], z: bits[1], init={0, 0}) {
20091837
}
20101838

20111839
TEST_P(BlockGeneratorTest, MultiProcWithInternalFifo) {
2012-
XLS_ASSERT_OK_AND_ASSIGN(
2013-
CodegenResult result,
2014-
MakeMultiProc(FifoConfig(/*depth=*/1, /*bypass=*/false,
2015-
/*register_push_outputs=*/true,
2016-
/*register_pop_outputs=*/false),
2017-
/*data_width=*/32));
2018-
VerilogInclude fifo_definition{
2019-
.relative_path = "fifo.v",
2020-
.verilog_text = std::string{kDepth1FifoRTLText}};
1840+
XLS_ASSERT_OK_AND_ASSIGN(CodegenResult result,
1841+
MakeMultiProc(kDepth1Fifo.config,
1842+
/*data_width=*/32));
1843+
VerilogInclude fifo_definition{.relative_path = "fifo.v",
1844+
.verilog_text = kDepth1Fifo.rtl};
20211845
std::initializer_list<VerilogInclude> include_definitions = {fifo_definition};
20221846

20231847
result.module_generator_result.verilog_text = absl::StrCat(
@@ -2048,16 +1872,12 @@ TEST_P(BlockGeneratorTest, MultiProcWithInternalFifo) {
20481872
}
20491873

20501874
TEST_P(BlockGeneratorTest, MultiProcWithInternalNoDataFifo) {
2051-
XLS_ASSERT_OK_AND_ASSIGN(
2052-
CodegenResult result,
2053-
MakeMultiProc(FifoConfig(/*depth=*/1, /*bypass=*/false,
2054-
/*register_push_outputs=*/true,
2055-
/*register_pop_outputs=*/false),
2056-
/*data_width=*/0));
2057-
2058-
VerilogInclude fifo_definition{
2059-
.relative_path = "fifo.v",
2060-
.verilog_text = std::string{kDepth1NoDataFifoRTLText}};
1875+
XLS_ASSERT_OK_AND_ASSIGN(CodegenResult result,
1876+
MakeMultiProc(kDepth1NoDataFifo.config,
1877+
/*data_width=*/0));
1878+
1879+
VerilogInclude fifo_definition{.relative_path = "fifo.v",
1880+
.verilog_text = kDepth1NoDataFifo.rtl};
20611881
std::initializer_list<VerilogInclude> include_definitions = {fifo_definition};
20621882

20631883
result.module_generator_result.verilog_text = absl::StrCat(
@@ -2088,15 +1908,11 @@ TEST_P(BlockGeneratorTest, MultiProcWithInternalNoDataFifo) {
20881908
}
20891909

20901910
TEST_P(BlockGeneratorTest, MultiProcDirectConnect) {
2091-
XLS_ASSERT_OK_AND_ASSIGN(
2092-
CodegenResult result,
2093-
MakeMultiProc(FifoConfig(/*depth=*/0, /*bypass=*/true,
2094-
/*register_push_outputs=*/false,
2095-
/*register_pop_outputs=*/false),
2096-
/*data_width=*/32));
2097-
VerilogInclude fifo_definition{
2098-
.relative_path = "fifo.v",
2099-
.verilog_text = std::string{kDepth0FifoRTLText}};
1911+
XLS_ASSERT_OK_AND_ASSIGN(CodegenResult result,
1912+
MakeMultiProc(kDepth0Fifo.config,
1913+
/*data_width=*/32));
1914+
VerilogInclude fifo_definition{.relative_path = "fifo.v",
1915+
.verilog_text = kDepth0Fifo.rtl};
21001916
std::initializer_list<VerilogInclude> include_definitions = {fifo_definition};
21011917

21021918
result.module_generator_result.verilog_text = absl::StrCat(
@@ -2128,15 +1944,11 @@ TEST_P(BlockGeneratorTest, MultiProcDirectConnect) {
21281944
}
21291945

21301946
TEST_P(BlockGeneratorTest, MultiProcNoDataDirectConnect) {
2131-
XLS_ASSERT_OK_AND_ASSIGN(
2132-
CodegenResult result,
2133-
MakeMultiProc(FifoConfig(/*depth=*/0, /*bypass=*/true,
2134-
/*register_push_outputs=*/false,
2135-
/*register_pop_outputs=*/false),
2136-
/*data_width=*/0));
2137-
VerilogInclude fifo_definition{
2138-
.relative_path = "fifo.v",
2139-
.verilog_text = std::string{kDepth0NoDataFifoRTLText}};
1947+
XLS_ASSERT_OK_AND_ASSIGN(CodegenResult result,
1948+
MakeMultiProc(kDepth0NoDataFifo.config,
1949+
/*data_width=*/0));
1950+
VerilogInclude fifo_definition{.relative_path = "fifo.v",
1951+
.verilog_text = kDepth0NoDataFifo.rtl};
21401952
std::initializer_list<VerilogInclude> include_definitions = {fifo_definition};
21411953

21421954
result.module_generator_result.verilog_text = absl::StrCat(

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