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Stitching multiple codegen'd RTL files can have name collisions #3705

@grebe

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@grebe

Consider the case where you want to use a parameterized RTL wrapper that conditionally instantiates different XLS-generated RTL. This is OK if every module has different names, say you generate A and B. However, if both A and B spawn proc C, you can get multiple module definitions with the same name (it won't be C, it will be some mangled name, but they can still be the same).

Some possible ways to deal with this:

  • Directly support generating parameterized RTL so you have one compilation unit (this seems like a big divergence from current behavior)
  • Add "multiple-tops" to opt + scheduling + codegen (slightly more limited version of the above)
  • Add an option that mangles extra stuff into spawned proc names
  • Have a mechanism to support marking some modules as extern/already taken when generating RTL, so you'd generate RTL serially by adding all the previously taken names to a list consumed by the next compilation unit.

Any other ideas?

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    codegenRelated to emitting (System)Verilog.stitchingIssues related to stitching, multi-proc codegen, and integration with external verilog modules

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