[zerocopy] Re-enable big endian aarch64 types

When initially released the LLVM semantics did not agree with the
intrinsics in the order of lanes and hence they got removed from stable
on big endian targets. The fix of these semantics was shipped with Rust
1.87 in March 2025 (<rust-lang/rust#136831>).

To keep the library working in these previous compiler versions the
intrinsics are enabled by their prior condition, a little endian target
is detected, or the feature detection cfg of the more recent rust
release is present.

Author: 197g

Cargo.toml

@@ -79,6 +79,11 @@ no-zerocopy-target-has-atomics-1-60-0 = "1.60.0"
 # versions, these types require the "simd-nightly" feature.
 no-zerocopy-aarch64-simd-1-59-0 = "1.59.0"
 
+# Include SIMD types from `core::arch::aarch64` on big endian targets. Prior to
+# 1.87.0 (#136831) the types were only correct on little endian and backed off
+# from stable in a breaking change.
+no-zerocopy-aarch64-simd-be-1-87-0 = "1.87.0"
+
 # Permit panicking in `const fn`s and calling `Vec::try_reserve`.
 no-zerocopy-panic-in-const-and-vec-try-reserve-1-57-0 = "1.57.0"
 

src/impls.rs

@@ -1352,10 +1352,18 @@ mod simd {
         );
         #[cfg(not(no_zerocopy_aarch64_simd_1_59_0))]
         simd_arch_mod!(
-            // NOTE(https://github.com/rust-lang/stdarch/issues/1484): NEON intrinsics are currently
-            // broken on big-endian platforms.
-            #[cfg(all(target_arch = "aarch64", target_endian = "little"))]
-            #[cfg_attr(doc_cfg, doc(cfg(rust = "1.59.0")))]
+            #[cfg(any(
+                all(target_arch = "aarch64", target_endian = "little"),
+                all(target_arch = "aarch64", not(no_zerocopy_aarch64_simd_be_1_87_0))
+            ))]
+            #[cfg_attr(
+                all(doc_cfg, target_endian = "little"),
+                doc(cfg(rust = "1.59.0"))
+            )]
+            #[cfg_attr(
+                all(doc_cfg, not(target_endian = "little")),
+                doc(cfg(rust = "1.87.0"))
+            )]
             aarch64, aarch64, float32x2_t, float32x4_t, float64x1_t, float64x2_t, int8x8_t, int8x8x2_t,
             int8x8x3_t, int8x8x4_t, int8x16_t, int8x16x2_t, int8x16x3_t, int8x16x4_t, int16x4_t,
             int16x8_t, int32x2_t, int32x4_t, int64x1_t, int64x2_t, poly8x8_t, poly8x8x2_t, poly8x8x3_t,