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[zerocopy] Re-enable big endian aarch64 types
When initially released the LLVM semantics did not agree with the intrinsics in the order of lanes and hence they got removed from stable on big endian targets. The fix of these semantics was shipped with Rust 1.87 in March 2025 (<rust-lang/rust#136831>). To keep the library working in these previous compiler versions the intrinsics are enabled by their prior condition, a little endian target is detected, or the feature detection cfg of the more recent rust release is present.
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.github/workflows/ci.yml

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@@ -61,6 +61,7 @@ jobs:
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"no-zerocopy-generic-bounds-in-const-fn-1-61-0",
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"no-zerocopy-target-has-atomics-1-60-0",
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"no-zerocopy-aarch64-simd-1-59-0",
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"no-zerocopy-aarch64-simd-be-1-87-0",
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"no-zerocopy-panic-in-const-and-vec-try-reserve-1-57-0"
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]
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target: [
@@ -103,6 +104,8 @@ jobs:
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features: "--all-features"
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- toolchain: "no-zerocopy-aarch64-simd-1-59-0"
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features: "--all-features"
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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features: "--all-features"
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- toolchain: "no-zerocopy-panic-in-const-and-vec-try-reserve-1-57-0"
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features: "--all-features"
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# Exclude any combination for the zerocopy-derive crate which
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toolchain: "no-zerocopy-target-has-atomics-1-60-0"
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- crate: "zerocopy-derive"
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toolchain: "no-zerocopy-aarch64-simd-1-59-0"
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- crate: "zerocopy-derive"
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toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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- crate: "zerocopy-derive"
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toolchain: "no-zerocopy-panic-in-const-and-vec-try-reserve-1-57-0"
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# Exclude stable/wasm since wasm is no longer provided via rustup on
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target: "thumbv6m-none-eabi"
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- toolchain: "no-zerocopy-aarch64-simd-1-59-0"
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target: "wasm32-unknown-unknown"
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# Exclude non-aarch64 targets from the `no-zerocopy-aarch64-simd-be-1-87-0`
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# toolchain.
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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target: "i686-unknown-linux-gnu"
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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target: "x86_64-unknown-linux-gnu"
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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target: "arm-unknown-linux-gnueabi"
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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target: "powerpc-unknown-linux-gnu"
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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target: "powerpc64-unknown-linux-gnu"
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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target: "riscv64gc-unknown-linux-gnu"
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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target: "s390x-unknown-linux-gnu"
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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target: "x86_64-pc-windows-msvc"
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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target: "thumbv6m-none-eabi"
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- toolchain: "no-zerocopy-aarch64-simd-be-1-87-0"
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target: "wasm32-unknown-unknown"
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# Exclude most targets from the `no-zerocopy-core-error-1-81-0`
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# toolchain since the `no-zerocopy-core-error-1-81-0` feature is unrelated to
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# compilation target. This only leaves i686 and x86_64 targets.

Cargo.toml

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@@ -79,6 +79,11 @@ no-zerocopy-target-has-atomics-1-60-0 = "1.60.0"
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# versions, these types require the "simd-nightly" feature.
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no-zerocopy-aarch64-simd-1-59-0 = "1.59.0"
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# Include SIMD types from `core::arch::aarch64` on big endian targets. Prior to
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# 1.87.0 (#136831) the types were only correct on little endian and backed off
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# from stable in a breaking change.
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no-zerocopy-aarch64-simd-be-1-87-0 = "1.87.0"
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# Permit panicking in `const fn`s and calling `Vec::try_reserve`.
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no-zerocopy-panic-in-const-and-vec-try-reserve-1-57-0 = "1.57.0"
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src/impls.rs

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@@ -1352,10 +1352,14 @@ mod simd {
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);
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#[cfg(not(no_zerocopy_aarch64_simd_1_59_0))]
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simd_arch_mod!(
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// NOTE(https://github.com/rust-lang/stdarch/issues/1484): NEON intrinsics are currently
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// broken on big-endian platforms.
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#[cfg(all(target_arch = "aarch64", target_endian = "little"))]
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#[cfg_attr(doc_cfg, doc(cfg(rust = "1.59.0")))]
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#[cfg(any(
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all(target_arch = "aarch64", target_endian = "little"),
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all(target_arch = "aarch64", not(no_zerocopy_aarch64_simd_be_1_87_0))
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))]
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#[cfg_attr(
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all(doc_cfg, target_endian = "little"),
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doc(cfg(rust = "1.59.0"))
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)]
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aarch64, aarch64, float32x2_t, float32x4_t, float64x1_t, float64x2_t, int8x8_t, int8x8x2_t,
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int8x8x3_t, int8x8x4_t, int8x16_t, int8x16x2_t, int8x16x3_t, int8x16x4_t, int16x4_t,
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int16x8_t, int32x2_t, int32x4_t, int64x1_t, int64x2_t, poly8x8_t, poly8x8x2_t, poly8x8x3_t,

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