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Verilog support
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Diff for: ‎README.md

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Original file line numberDiff line numberDiff line change
@@ -61,15 +61,16 @@ Other languages are supported via extensions:
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[Apollo](src/lang-apollo.js);
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[Basic](src/lang-basic.js);
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[Clojure](src/lang-clj.js);
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[CSS](src/lang-css.js);
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[Clojure](src/lang-clj.js);
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[Dart](src/lang-dart.js);
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[Erlang](src/lang-erlang.js);
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[Go](src/lang-go.js);
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[Haskell](src/lang-hs.js);
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[LLVM](src/lang-llvm.js);
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[LaTeX](src/lang-tex.js);
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[Lasso](src/lang-lasso.js);
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[Lisp, Scheme](src/lang-lisp.js);
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[LLVM](src/lang-llvm.js);
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[Logtalk](src/lang-logtalk.js);
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[Lua](src/lang-lua.js);
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[MATLAB](src/lang-matlab.js);
@@ -81,16 +82,16 @@ Other languages are supported via extensions:
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[R, S](src/lang-r.js);
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[RD](src/lang-rd.js);
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[Rust](src/lang-rust.js);
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[Scala](src/lang-scala.js);
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[SQL](src/lang-sql.js);
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[Scala](src/lang-scala.js);
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[Swift](src/lang-swift.js);
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[TCL](src/lang-tcl.js);
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[LaTeX](src/lang-tex.js);
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[Visual Basic](src/lang-vb.js);
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[VHDL](src/lang-vhdl.js);
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[Verilog](src/lang-verilog.js);
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[Visual Basic](src/lang-vb.js);
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[Wiki](src/lang-wiki.js);
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[XQ](src/lang-xq.js);
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[YAML](src/lang-yaml.js)
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[YAML](src/lang-yaml.js);
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If you'd like to add an extension for your favorite language, please look at
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`src/lang-lisp.js` and submit a pull request.

Diff for: ‎src/lang-verilog.js

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@@ -0,0 +1,48 @@
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/**
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* @license
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* Copyright (C) 2020 [email protected]
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
12+
* distributed under the License is distributed on an "AS IS" BASIS,
13+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14+
* See the License for the specific language governing permissions and
15+
* limitations under the License.
16+
*/
17+
18+
/**
19+
* @fileoverview
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* Registers a language handler for Verilog.
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*
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* Based on the lexical grammar and keywords at
23+
* https://www.verilog.com/VerilogBNF.html#REF170
24+
*
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* @author [email protected]
26+
*/
27+
PR['registerLangHandler'](
28+
PR['createSimpleLexer'](
29+
[
30+
[PR['PR_PLAIN'], /^[\t\n\r \xA0]+/, null, '\t\n\r \xA0'],
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[PR['PR_PUNCTUATION'], /^[.!%&()*+,\-;<=>?\[\\\]^{|}:@#]+/, null, '.!%&()*+,-;<=>?[\\]^{|}:@#']
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],
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[
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[PR['PR_KEYWORD'], /^(?:\$hold|\$period|\$recovery|\$setup|\$setuphold\$skew|\$width|always|assign|begin|case|casex|casez|default|defparam|disable|else|end|endcase|endfunction|endmodule|endprimitive|endspecify|endtable|endtask|for|force|forever|fork|function|if|initial|join|macromodule|module|negedge|parameter|posedge|primitive|release|repeat|specify|specparam|table|task|wait|while)(?=[^\w-]|$)/i],
35+
[PR['PR_TYPE'], /^(?:and|buf|bufif0|bufif1|cmos|event|inout|input|integer|nand|nmos|nor|not|notif0|notif1|or|output|pmos|pulldown|pullup|rcmos|real|reg|rnmos|rpmos|rtran|rtranif0|rtranif1|scalared|supply0|supply1|time|tran|tranif0|tranif1|tri|tri0|tri1|triand|trior|trireg|vectored|wand|wire|wor|xnor|xor)(?=[^\w-]|$)/i],
36+
[PR['PR_TAG'], /^(?:highz0|highz1|large|medium|pull0|pull1|small|strong0|strong1|supply0|supply1|weak0|weak1)(?=[^\w-]|$)/i],
37+
// number
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[PR['PR_LITERAL'], /^(?:[0-9][0-9_]*(?:\.[0-9_]+)?(?:e[0-9_]+)?)|(?:(?:[0-9][0-9_]*)?'[bodh][0-9a-fA-FxXzZ?]+)/i],
39+
// edge
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[PR['PR_LITERAL'], /^(?:01|0x|10|1x|x0|x1)(?=[^\w-]|$)/i],
41+
// string
42+
[PR['PR_STRING'], /^"([^"\\]|\\[\s\S])*"/],
43+
// double slash comments
44+
[PR['PR_COMMENT'], /^\/\/.*/],
45+
// slash star comments and documentation
46+
[PR['PR_COMMENT'], /^\/\*[\s\S]*?(?:\*\/|$)/]
47+
]),
48+
['verilog', 'v']);

Diff for: ‎tests/prettify_test_2.html

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@@ -36,6 +36,7 @@
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'lang-r.js',
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'lang-tcl.js',
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'lang-tex.js',
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'lang-verilog.js',
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'lang-xq.js'
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];
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var styles = [
@@ -1201,5 +1202,76 @@ <h1>Kotlin</h1>
12011202

12021203
fun Boolean?.getOrThrow(): Boolean = this ?: throw Exception()
12031204
</pre>
1205+
1206+
<h1>Verilog</h1>
1207+
<pre class="prettyprint lang-verilog" id="verilog">
1208+
/*
1209+
* Multiline
1210+
* comment
1211+
*/
1212+
a = "123"
1213+
nor ( small )
1214+
nor (highz1, strong0)
1215+
//-----------------------------------------------------
1216+
// Design Name : cam
1217+
// File Name : cam.v
1218+
// Function : CAM
1219+
// Coder : Deepak Kumar Tala
1220+
//-----------------------------------------------------
1221+
module cam (
1222+
clk , // Cam clock
1223+
cam_enable , // Cam enable
1224+
cam_data_in , // Cam data to match
1225+
cam_hit_out , // Cam match has happened
1226+
cam_addr_out // Cam output address
1227+
);
1228+
1229+
parameter ADDR_WIDTH = 8;
1230+
parameter DEPTH = 1 &lt;&lt; ADDR_WIDTH;
1231+
//------------Input Ports--------------
1232+
input clk;
1233+
input cam_enable;
1234+
input [DEPTH-1:0] cam_data_in;
1235+
//----------Output Ports--------------
1236+
output cam_hit_out;
1237+
output [ADDR_WIDTH-1:0] cam_addr_out;
1238+
//------------Internal Variables--------
1239+
reg [ADDR_WIDTH-1:0] cam_addr_out;
1240+
reg cam_hit_out;
1241+
reg [ADDR_WIDTH-1:0] cam_addr_combo;
1242+
reg cam_hit_combo;
1243+
reg found_match;
1244+
integer i;
1245+
//-------------Code Starts Here-------
1246+
always @(cam_data_in) begin
1247+
cam_addr_combo = {ADDR_WIDTH{1'b0}};
1248+
found_match = 1'b0;
1249+
cam_hit_combo = 1'b0;
1250+
for (i=0; i&lt;DEPTH; i=i+1) begin
1251+
if (cam_data_in[i] && !found_match) begin
1252+
found_match = 1'b1;
1253+
cam_hit_combo = 1'b1;
1254+
cam_addr_combo = i;
1255+
end else begin
1256+
found_match = found_match;
1257+
cam_hit_combo = cam_hit_combo;
1258+
cam_addr_combo = cam_addr_combo;
1259+
end
1260+
end
1261+
end
1262+
1263+
// Register the outputs
1264+
always @(posedge clk) begin
1265+
if (cam_enable) begin
1266+
cam_hit_out &lt;= cam_hit_combo;
1267+
cam_addr_out &lt;= cam_addr_combo;
1268+
end else begin
1269+
cam_hit_out &lt;= 1'b0;
1270+
cam_addr_out &lt;= {ADDR_WIDTH{1'b0}};
1271+
end
1272+
end
1273+
1274+
endmodule
1275+
</pre>
12041276
</body>
12051277
</html>

Diff for: ‎tests/prettify_test_2.js

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@@ -768,6 +768,75 @@ var goldens = {
768768
'\n' +
769769
'`END`KWDfun`END`PLN `END`TYPBoolean`END`PUN?.`END`PLNgetOrThrow`END`PUN():`END`PLN `END`TYPBoolean`END`PLN `END`PUN=`END`PLN `END`KWDthis`END`PLN `END`PUN?:`END`PLN `END`KWDthrow`END`PLN `END`TYPException`END`PUN()`END'
770770
),
771+
verilog: (
772+
'`COM/*\n' +
773+
' * Multiline\n' +
774+
' * comment\n' +
775+
' */`END`PLN\n' +
776+
'a `END`PUN=`END`PLN `END`STR"123"`END`PLN\n' +
777+
'`END<span class="typ">nor`END`PLN `END`PUN(`END`PLN `END`TAGsmall`END`PLN `END`PUN)`END`PLN\n' +
778+
'`END<span class="typ">nor`END`PLN `END`PUN(`END`TAGhighz1`END`PUN,`END`PLN `END`TAGstrong0`END`PUN)`END`PLN\n' +
779+
'`END`COM//-----------------------------------------------------`END`PLN\n' +
780+
'`END`COM// Design Name : cam`END`PLN\n' +
781+
'`END`COM// File Name : cam.v`END`PLN\n' +
782+
'`END`COM// Function : CAM`END`PLN\n' +
783+
'`END`COM// Coder : Deepak Kumar Tala`END`PLN\n' +
784+
'`END`COM//-----------------------------------------------------`END`PLN\n' +
785+
'`END`KWDmodule`END`PLN cam `END`PUN(`END`PLN\n' +
786+
'clk `END`PUN,`END`PLN `END`COM// Cam clock`END`PLN\n' +
787+
'cam_enable `END`PUN,`END`PLN `END`COM// Cam enable`END`PLN\n' +
788+
'cam_data_in `END`PUN,`END`PLN `END`COM// Cam data to match`END`PLN\n' +
789+
'cam_hit_out `END`PUN,`END`PLN `END`COM// Cam match has happened`END`PLN\n' +
790+
'cam_addr_out `END`COM// Cam output address`END`PLN\n' +
791+
'`END`PUN);`END`PLN\n' +
792+
'\n' +
793+
'`END`KWDparameter`END`PLN ADDR_WIDTH `END`PUN=`END`PLN `END`LIT8`END`PUN;`END`PLN\n' +
794+
'`END`KWDparameter`END`PLN DEPTH `END`PUN=`END`PLN `END`LIT1`END`PLN `END`PUN&lt;&lt;`END`PLN ADDR_WIDTH`END`PUN;`END`PLN\n' +
795+
'`END`COM//------------Input Ports--------------`END`PLN\n' +
796+
'`END`TYPinput`END`PLN clk`END`PUN;`END`PLN\n' +
797+
'`END`TYPinput`END`PLN cam_enable`END`PUN;`END`PLN\n' +
798+
'`END`TYPinput`END`PLN `END`PUN[`END`PLNDEPTH`END`PUN-`END`LIT1`END`PUN:`END`LIT0`END`PUN]`END`PLN cam_data_in`END`PUN;`END`PLN\n' +
799+
'`END`COM//----------Output Ports--------------`END`PLN\n' +
800+
'`END`TYPoutput`END`PLN cam_hit_out`END`PUN;`END`PLN\n' +
801+
'`END`TYPoutput`END`PLN `END`PUN[`END`PLNADDR_WIDTH`END`PUN-`END`LIT1`END`PUN:`END`LIT0`END`PUN]`END`PLN cam_addr_out`END`PUN;`END`PLN\n' +
802+
'`END`COM//------------Internal Variables--------`END`PLN\n' +
803+
'`END`TYPreg`END`PLN `END`PUN[`END`PLNADDR_WIDTH`END`PUN-`END`LIT1`END`PUN:`END`LIT0`END`PUN]`END`PLN cam_addr_out`END`PUN;`END`PLN\n' +
804+
'`END`TYPreg`END`PLN cam_hit_out`END`PUN;`END`PLN\n' +
805+
'`END`TYPreg`END`PLN `END`PUN[`END`PLNADDR_WIDTH`END`PUN-`END`LIT1`END`PUN:`END`LIT0`END`PUN]`END`PLN cam_addr_combo`END`PUN;`END`PLN\n' +
806+
'`END`TYPreg`END`PLN cam_hit_combo`END`PUN;`END`PLN\n' +
807+
'`END`TYPreg`END`PLN found_match`END`PUN;`END`PLN\n' +
808+
'`END`TYPinteger`END`PLN i`END`PUN;`END`PLN\n' +
809+
'`END`COM//-------------Code Starts Here-------`END`PLN\n' +
810+
'`END`KWDalways`END`PLN `END`PUN@(`END`PLNcam_data_in`END`PUN)`END`PLN `END`KWDbegin`END`PLN\n' +
811+
' cam_addr_combo `END`PUN=`END`PLN `END`PUN{`END`PLNADDR_WIDTH`END`PUN{`END`LIT1\'b0`END`PUN}};`END`PLN\n' +
812+
' found_match `END`PUN=`END`PLN `END`LIT1\'b0`END`PUN;`END`PLN\n' +
813+
' cam_hit_combo `END`PUN=`END`PLN `END`LIT1\'b0`END`PUN;`END`PLN\n' +
814+
' `END`KWDfor`END`PLN `END`PUN(`END`PLNi`END`PUN=`END`LIT0`END`PUN;`END`PLN i`END`PUN&lt;`END`PLNDEPTH`END`PUN;`END`PLN i`END`PUN=`END`PLNi`END`PUN+`END`LIT1`END`PUN)`END`PLN `END`KWDbegin`END`PLN\n' +
815+
' `END`KWDif`END`PLN `END`PUN(`END`PLNcam_data_in`END`PUN[`END`PLNi`END`PUN]`END`PLN `END`PUN&amp;&amp;`END`PLN `END`PUN!`END`PLNfound_match`END`PUN)`END`PLN `END`KWDbegin`END`PLN\n' +
816+
' found_match `END`PUN=`END`PLN `END`LIT1\'b1`END`PUN;`END`PLN\n' +
817+
' cam_hit_combo `END`PUN=`END`PLN `END`LIT1\'b1`END`PUN;`END`PLN\n' +
818+
' cam_addr_combo `END`PUN=`END`PLN i`END`PUN;`END`PLN\n' +
819+
' `END`KWDend`END`PLN `END`KWDelse`END`PLN `END`KWDbegin`END`PLN\n' +
820+
' found_match `END`PUN=`END`PLN found_match`END`PUN;`END`PLN\n' +
821+
' cam_hit_combo `END`PUN=`END`PLN cam_hit_combo`END`PUN;`END`PLN\n' +
822+
' cam_addr_combo `END`PUN=`END`PLN cam_addr_combo`END`PUN;`END`PLN\n' +
823+
' `END`KWDend`END`PLN\n' +
824+
' `END`KWDend`END`PLN\n' +
825+
'`END`KWDend`END`PLN\n' +
826+
'\n' +
827+
'`END`COM// Register the outputs`END`PLN\n' +
828+
'`END`KWDalways`END`PLN `END`PUN@(`END`KWDposedge`END`PLN clk`END`PUN)`END`PLN `END`KWDbegin`END`PLN\n' +
829+
' `END`KWDif`END`PLN `END`PUN(`END`PLNcam_enable`END`PUN)`END`PLN `END`KWDbegin`END`PLN\n' +
830+
' cam_hit_out `END`PUN&lt;=`END`PLN cam_hit_combo`END`PUN;`END`PLN\n' +
831+
' cam_addr_out `END`PUN&lt;=`END`PLN cam_addr_combo`END`PUN;`END`PLN\n' +
832+
' `END`KWDend`END`PLN `END`KWDelse`END`PLN `END`KWDbegin`END`PLN\n' +
833+
' cam_hit_out `END`PUN&lt;=`END`PLN `END`LIT1\'b0`END`PUN;`END`PLN\n' +
834+
' cam_addr_out `END`PUN&lt;=`END`PLN `END`PUN{`END`PLNADDR_WIDTH`END`PUN{`END`LIT1\'b0`END`PUN}};`END`PLN\n' +
835+
' `END`KWDend`END`PLN\n' +
836+
'`END`KWDend`END`PLN\n' +
837+
'\n' +
838+
'`END`KWDendmodule`END'
839+
),
771840
llvm: (
772841
'`COM; Declare the string constant as a global constant.`END`PLN\n' +
773842
'@.str `END`PUN=`END`PLN `END`KWDprivate`END`PLN `END`KWDunnamed_addr`END`PLN `END`KWDconstant`END`PLN `END`PUN[`END`LIT13`END`PLN `END`KWDx`END`PLN `END`KWDi8`END`PUN]`END`PLN `END`KWDc`END`STR"hello world\\0A\\00"`END`PLN\n' +

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