ctxreg: handle riscv32 targets

Author: cpunion

internal/build/target_arch.go

@@ -40,8 +40,7 @@ func goarchFromTriple(triple string) string {
 	case "riscv64":
 		return "riscv64"
 	case "riscv32":
-		// ESP32-C3 and other RISC-V 32-bit targets can use the same x27 register as riscv64
-		return "riscv64"
+		return "riscv32"
 	case "wasm32":
 		return "wasm"
 	}

internal/ctxreg/ctxreg.go

@@ -11,6 +11,7 @@ var table = map[string]Info{
 	"arm64":   {Name: "x26", Constraint: "{x26}"},
 	"386":     {Name: "mm0", Constraint: "{mm0}"},
 	"riscv64": {Name: "x27", Constraint: "{x27}"},
+	"riscv32": {Name: "x27", Constraint: "{x27}"},
 }
 
 // Get returns the register info for the given GOARCH.

ssa/ctxreg.go

@@ -35,6 +35,11 @@ var ctxAsmTemplates = map[string]ctxAsmTemplate{
 		read:    "mv $0, %s",
 		dialect: llvm.InlineAsmDialectATT,
 	},
+	"riscv32": {
+		write:   "mv %s, $0",
+		read:    "mv $0, %s",
+		dialect: llvm.InlineAsmDialectATT,
+	},
 }
 
 func ctxAsmStrings(goarch, reg string) (write string, read string, dialect llvm.InlineAsmDialect, ok bool) {

ssa/target.go

@@ -41,7 +41,7 @@ type Target struct {
 //   - amd64: MM0 - MMX register (caller-saved), avoid MMX usage via -msse2
 //   - 386:   MM0 - MMX register (caller-saved), avoid MMX usage via -msse2
 //   - arm64: X26 - callee-saved, reservable via +reserve-x26
-//   - riscv64: X27 (s11) - callee-saved register
+//   - riscv64/riscv32: X27 (s11) - callee-saved register
 //
 // Platforms without a ctx register:
 //   - arm: r8-r15 are "high registers", LLVM can't use {rN} constraint in ARM mode
@@ -66,6 +66,8 @@ func (t *Target) CtxRegister() CtxRegister {
 		return CtxRegister{Name: "mm0", Constraint: "{mm0}"}
 	case "riscv64":
 		return CtxRegister{Name: "x27", Constraint: "{x27}"}
+	case "riscv32":
+		return CtxRegister{Name: "x27", Constraint: "{x27}"}
 	default:
 		return CtxRegister{}
 	}