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fix format, clippy and tests
1 parent 4369e92 commit ebc953c

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4 files changed

+9
-14
lines changed

4 files changed

+9
-14
lines changed

Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44

55
[package]
66
name = "rainbow-rs"
7-
version = "0.6.1"
7+
version = "0.6.2"
88
edition = "2021"
99

1010
[dependencies]

src/lib.rs

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,6 @@ use unicorn_engine::{
2525
RegisterARM, Unicorn,
2626
};
2727

28-
2928
use asmutils::{ElfInfo, Segment, SideChannelOperandsValues};
3029
use communication::{Communication, SimpleSerial};
3130
use error::{CapstoneError, UcError};
@@ -54,7 +53,7 @@ pub struct ScaData<'a> {
5453
pub instruction: &'a OwnedInsn<'static>,
5554
pub registers: &'a Vec<ArmOperand>,
5655
pub regvalues_before: ArrayVec<u64, 16>,
57-
pub regvalues_after: ArrayVec<u64,16>,
56+
pub regvalues_after: ArrayVec<u64, 16>,
5857
pub cache_updates:
5958
ArrayVec<([u8; MAX_BUS_SIZE], [u8; MAX_BUS_SIZE]), MAX_MEMORY_UPDATES_PER_INSTRUCTION>,
6059
pub bus_updates:

src/memory_extension.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -182,7 +182,7 @@ impl MemoryExtension for CacheLruWriteThrough {
182182
memory_before: [u8; MAX_BUS_SIZE],
183183
memory_after: [u8; MAX_BUS_SIZE],
184184
) {
185-
assert!((address as usize % self.bus_size) == 0);
185+
assert!((address as usize).is_multiple_of(self.bus_size));
186186
// Check if address is in cache
187187
if let Some(index) = self.cache.iter().position(|(addr, _)| *addr == address) {
188188
assert!(
@@ -313,7 +313,7 @@ impl MemoryExtension for CacheLruWriteBack {
313313
memory_before: [u8; MAX_BUS_SIZE],
314314
memory_after: [u8; MAX_BUS_SIZE],
315315
) {
316-
assert!((address as usize % self.bus_size) == 0);
316+
assert!((address as usize).is_multiple_of(self.bus_size));
317317
// Check if address is in cache
318318
if let Some(index) = self.cache.iter().position(|line| line.address == address) {
319319
let line = &self.cache[index];

tests/libtests.rs

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ use rainbow_rs::{
1919
ScaData, ThumbTraceEmulator, ThumbTraceEmulatorTrait,
2020
};
2121
use rstest::rstest;
22-
use unicorn_engine::unicorn_const::Permission;
22+
use unicorn_engine::unicorn_const::Prot;
2323

2424
#[ctor::ctor]
2525
fn init() {
@@ -92,12 +92,8 @@ fn generate_leakage(
9292
)
9393
.unwrap();
9494

95-
emu.mem_map(
96-
elfinfo.segments().next().unwrap().start(),
97-
1024,
98-
Permission::all(),
99-
)
100-
.unwrap();
95+
emu.mem_map(elfinfo.segments().next().unwrap().start(), 1024, Prot::ALL)
96+
.unwrap();
10197
emu.load().unwrap();
10298

10399
emu.register_hook_addr(elfinfo.segments().next().unwrap().start(), |emu| {
@@ -372,7 +368,7 @@ fn test_victim_communication() {
372368
)
373369
.unwrap();
374370

375-
emu.mem_map(0x1000_0000, 1024, Permission::all()).unwrap();
371+
emu.mem_map(0x1000_0000, 1024, Prot::ALL).unwrap();
376372
emu.load().unwrap();
377373

378374
emu.register_hook_addr(0x1000_0000, |emu| {
@@ -416,7 +412,7 @@ fn test_terminate() {
416412
)
417413
.unwrap();
418414

419-
emu.mem_map(0x1000_0000, 1024, Permission::all()).unwrap();
415+
emu.mem_map(0x1000_0000, 1024, Prot::ALL).unwrap();
420416
emu.load().unwrap();
421417

422418
emu.register_hook_addr(0x1000_0000, |emu| emu.process_inter_thread_communication());

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