diff --git a/Cargo.toml b/Cargo.toml
index 3f212ce..157c5b0 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -4,7 +4,7 @@
 
 [package]
 name = "rainbow-rs"
-version = "0.6.1"
+version = "0.6.2"
 edition = "2021"
 
 [dependencies]
diff --git a/src/lib.rs b/src/lib.rs
index 7f1f2f9..7a4ce6e 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -25,7 +25,6 @@ use unicorn_engine::{
     RegisterARM, Unicorn,
 };
 
-
 use asmutils::{ElfInfo, Segment, SideChannelOperandsValues};
 use communication::{Communication, SimpleSerial};
 use error::{CapstoneError, UcError};
@@ -54,7 +53,7 @@ pub struct ScaData<'a> {
     pub instruction: &'a OwnedInsn<'static>,
     pub registers: &'a Vec<ArmOperand>,
     pub regvalues_before: ArrayVec<u64, 16>,
-    pub regvalues_after: ArrayVec<u64,16>,
+    pub regvalues_after: ArrayVec<u64, 16>,
     pub cache_updates:
         ArrayVec<([u8; MAX_BUS_SIZE], [u8; MAX_BUS_SIZE]), MAX_MEMORY_UPDATES_PER_INSTRUCTION>,
     pub bus_updates:
diff --git a/src/memory_extension.rs b/src/memory_extension.rs
index 39b6c41..0fee6bf 100644
--- a/src/memory_extension.rs
+++ b/src/memory_extension.rs
@@ -182,7 +182,7 @@ impl MemoryExtension for CacheLruWriteThrough {
         memory_before: [u8; MAX_BUS_SIZE],
         memory_after: [u8; MAX_BUS_SIZE],
     ) {
-        assert!((address as usize % self.bus_size) == 0);
+        assert!((address as usize).is_multiple_of(self.bus_size));
         // Check if address is in cache
         if let Some(index) = self.cache.iter().position(|(addr, _)| *addr == address) {
             assert!(
@@ -313,7 +313,7 @@ impl MemoryExtension for CacheLruWriteBack {
         memory_before: [u8; MAX_BUS_SIZE],
         memory_after: [u8; MAX_BUS_SIZE],
     ) {
-        assert!((address as usize % self.bus_size) == 0);
+        assert!((address as usize).is_multiple_of(self.bus_size));
         // Check if address is in cache
         if let Some(index) = self.cache.iter().position(|line| line.address == address) {
             let line = &self.cache[index];
diff --git a/tests/libtests.rs b/tests/libtests.rs
index 514e5b3..c15b34e 100644
--- a/tests/libtests.rs
+++ b/tests/libtests.rs
@@ -19,7 +19,7 @@ use rainbow_rs::{
     ScaData, ThumbTraceEmulator, ThumbTraceEmulatorTrait,
 };
 use rstest::rstest;
-use unicorn_engine::unicorn_const::Permission;
+use unicorn_engine::unicorn_const::Prot;
 
 #[ctor::ctor]
 fn init() {
@@ -92,12 +92,8 @@ fn generate_leakage(
     )
     .unwrap();
 
-    emu.mem_map(
-        elfinfo.segments().next().unwrap().start(),
-        1024,
-        Permission::all(),
-    )
-    .unwrap();
+    emu.mem_map(elfinfo.segments().next().unwrap().start(), 1024, Prot::ALL)
+        .unwrap();
     emu.load().unwrap();
 
     emu.register_hook_addr(elfinfo.segments().next().unwrap().start(), |emu| {
@@ -372,7 +368,7 @@ fn test_victim_communication() {
     )
     .unwrap();
 
-    emu.mem_map(0x1000_0000, 1024, Permission::all()).unwrap();
+    emu.mem_map(0x1000_0000, 1024, Prot::ALL).unwrap();
     emu.load().unwrap();
 
     emu.register_hook_addr(0x1000_0000, |emu| {
@@ -416,7 +412,7 @@ fn test_terminate() {
     )
     .unwrap();
 
-    emu.mem_map(0x1000_0000, 1024, Permission::all()).unwrap();
+    emu.mem_map(0x1000_0000, 1024, Prot::ALL).unwrap();
     emu.load().unwrap();
 
     emu.register_hook_addr(0x1000_0000, |emu| emu.process_inter_thread_communication());