results.tsv

date	commit	iterations	scope	supported_delta	tests_passed	todo_delta	remaining_gap	runtime_build_s
2026-04-07	8bbb7ac	1	INT8 processing element	PE MAC and testbench	not recorded	not tracked before results.tsv	Tensor array integration
2026-04-07	7921bfc	1	Systolic array	Parameterized systolic array and 2x2 matrix-vector test	not recorded	not tracked before results.tsv	SRAM and controller integration
2026-04-07	439f05c	1	SRAM banks	Parameterized weight and activation SRAM banks	not recorded	not tracked before results.tsv	Controller sequencing
2026-04-07	5536813	1	Controller	Weight-load stream drain FSM	not recorded	not tracked before results.tsv	Top-level accelerator integration
2026-04-07	a8a2d48	1	Tensor accelerator	Top-level accelerator integrates array SRAM and controller	not recorded	not tracked before results.tsv	Full integration testbench
2026-04-07	700f9f2	1	Accelerator integration	Full integration testbench and proviso fix	not recorded	not tracked before results.tsv	Remove generated build artifacts
2026-04-07	1f77f03	1	Repository hygiene	Gitignore and tracked build artifact removal	not recorded	not tracked before results.tsv	4x4 parameterization
2026-04-07	8d29050	1	Accelerator parameterization	4x4 tensor accelerator parameterization test	not recorded	not tracked before results.tsv	Repo source layout cleanup
2026-04-07	258c2e8	1	Repository layout	Reorganized src test doc and build output	not recorded	not tracked before results.tsv	XLU datapath
2026-04-08	e5d337c	1	XLU rotate	XLU module with ROTATE support and testbench	not recorded	not tracked before results.tsv	XLU broadcast
2026-04-08	05361c0	1	XLU broadcast	BROADCAST test in TbXLU	not recorded	not tracked before results.tsv	XLU permute
2026-04-08	c85d7ad	1	XLU permute	PERMUTE identity and reversal tests	not recorded	not tracked before results.tsv	XLU transpose
2026-04-08	732f48e	1	XLU transpose	TRANSPOSE test in TbXLU	not recorded	not tracked before results.tsv	Chip architecture docs
2026-04-08	8aa62b1	1	Design docs	TPU chip XLU and unit plans	not recorded	not tracked before results.tsv	tinygrad integration
2026-04-08	b2b745c	1	tinygrad submodule	tinygrad compiler stack added as submodule	not recorded	not tracked before results.tsv	VMEM scratchpad
2026-04-08	c3e8a42	1	VMEM	Unified scratchpad SRAM and tests plus software spec	not recorded	not tracked before results.tsv	VRegFile
2026-04-08	f56ee99	1	VRegFile	Vector register file with isolation tests	not recorded	not tracked before results.tsv	VPU
2026-04-08	3349c9e	1	VPU initial ops	ADD MUL RELU MAX SUM_REDUCE and 5 tests	not recorded	not tracked before results.tsv	ScalarUnit sequencing
2026-04-08	ad4dcf0	1	ScalarUnit	Microprogram sequencer for VMEM VRegFile VPU XLU	not recorded	not tracked before results.tsv	TensorCore integration
2026-04-08	35ba221	1	TensorCore	SXU MXU VPU XLU VRegFile VMEM integration and MXU dispatch wait	not recorded	not tracked before results.tsv	Chip peripheral blocks
2026-04-08	43977f5	1	SparseCore	Embedding lookup accelerator with sum pooling	not recorded	not tracked before results.tsv	HBM model
2026-04-08	53c0393	1	HBM model	Configurable read latency behavioral model	not recorded	not tracked before results.tsv	NoC
2026-04-08	4060658	1	Chip NoC	On-chip ring NoC with single-hop two-hop loopback tests	not recorded	not tracked before results.tsv	Top-level chip
2026-04-08	c3a5115	1	TinyTPUChip	Top-level chip integrating TC0 SparseCore HBMModel NoC	not recorded	not tracked before results.tsv	README
2026-04-08	70d0b1c	1	README	Top-level README added	not recorded	not tracked before results.tsv	Co-simulation backend
2026-04-08	1ae533f	1	Co-simulation backend	TinyTPU runtime testbench and tinygrad co-sim path	not recorded	not tracked before results.tsv	Submodule backend pointer
2026-04-08	286c799	1	tinygrad backend pointer	Submodule updated to include ops_tinytpu.py	not recorded	not tracked before results.tsv	README update
2026-04-08	f272fe1	1	README co-sim docs	README updated for completed co-simulation backend	not recorded	not tracked before results.tsv	Profiler design
2026-04-09	182dea3	1	Profiler design	TinyTPU profiler design spec	not recorded	not tracked before results.tsv	Tracing clarification
2026-04-09	e2deeff	1	Tracing docs	Clarified tracing approach for VMEM and VPU	not recorded	not tracked before results.tsv	Move profiler spec
2026-04-09	4bf62ce	1	Profiler docs	Profiler design moved to doc	not recorded	not tracked before results.tsv	Profiler implementation
2026-04-09	e350f7f	1	Profiler and ONNX trace	Profiler tooling and ONNX trace flow	not recorded	not tracked before results.tsv	Runtime runner
2026-04-09	76274ae	1	Runtime runner	TinyTPU numeric bundle runtime runner	not recorded	not tracked before results.tsv	Python cache hygiene
2026-04-09	ffed9a9	1	Gitignore	Python bytecode caches ignored	not recorded	not tracked before results.tsv	Agent loop docs
2026-04-09	b3a4249	1	Agent workflow	Expanded AGENT implementation loop	not recorded	not tracked before results.tsv	GEMM coverage expansion
2026-04-09	38e383b	1	GEMM coverage	Batched TinyTPU GEMM tests	not recorded	not tracked before results.tsv	Wide GEMM
2026-04-09	f82d0e6	1	GEMM coverage	Wide TinyTPU GEMM tests	not recorded	not tracked before results.tsv	Int8 range checks
2026-04-09	9eea0dc	1	GEMM diagnostics	Int8 range checks	not recorded	not tracked before results.tsv	Lowering errors
2026-04-09	175bf33	1	Lowering diagnostics	TinyTPU lowering error tests	not recorded	not tracked before results.tsv	Deep GEMM
2026-04-09	3c8a4bb	1	GEMM coverage	Deep TinyTPU GEMM tests	not recorded	not tracked before results.tsv	Batched deep GEMM
2026-04-09	4668472	1	GEMM coverage	Batched deep TinyTPU GEMM tests	not recorded	not tracked before results.tsv	Random signed GEMM
2026-04-09	bd64e71	1	GEMM coverage	Random signed TinyTPU GEMM tests	not recorded	not tracked before results.tsv	Tiling inference
2026-04-09	c500a30	1	Tiling tests	TinyTPU tiling inference locked	not recorded	not tracked before results.tsv	Width diagnostics
2026-04-09	f635c6e	1	Tiling diagnostics	Width diagnostics for unsupported TinyTPU GEMM	not recorded	not tracked before results.tsv	Empty GEMM shapes
2026-04-09	3be5495	1	GEMM edge cases	Empty TinyTPU GEMM shape tests	not recorded	not tracked before results.tsv	Zero-sized GEMM diagnostics
2026-04-09	e99a9fd	1	GEMM diagnostics	Zero-sized TinyTPU GEMM error tests	not recorded	not tracked before results.tsv	Batched random GEMM
2026-04-09	4d2ecdd	1	GEMM coverage	Batched random TinyTPU GEMM tests	not recorded	not tracked before results.tsv	Tiling notes
2026-04-09	5a1e696	1	Tiling diagnostics	TinyTPU tiling notes locked	not recorded	not tracked before results.tsv	UOp diagnostics
2026-04-09	0c86375	1	UOp diagnostics	TinyTPU UOp diagnostics tests	not recorded	not tracked before results.tsv	Profiler validation
2026-04-09	f71b3c0	1	Profiler validation	Invalid bundle integer diagnostics	not recorded	not tracked before results.tsv	Output flag validation
2026-04-09	0f71f54	1	Profiler validation	Bundle output flag validation	not recorded	not tracked before results.tsv	Simulator output parsing
2026-04-09	e6b5adb	1	Simulator parsing	Indented TinyTPU sim output	not recorded	not tracked before results.tsv	Malformed sim output
2026-04-09	79c228c	1	Simulator parsing	Malformed TinyTPU sim output diagnostics	not recorded	not tracked before results.tsv	MXU result width
2026-04-09	201dd65	1	Simulator parsing	TinyTPU MXU result width validation	not recorded	not tracked before results.tsv	Simulator failure lines
2026-04-09	3163c27	1	Simulator status	Simulator failure line rejection	not recorded	not tracked before results.tsv	Simulator ok status
2026-04-09	5adfdd1	1	Simulator status	Simulator status ok requirement	not recorded	not tracked before results.tsv	Trace parser validation
2026-04-09	fdda68b	1	Trace parser validation	Malformed trace line rejection	not recorded	not tracked before results.tsv	Trace field validation
2026-04-09	06dfb26	1	Trace parser validation	Malformed trace field rejection	not recorded	not tracked before results.tsv	Empty trace field validation
2026-04-09	7a8e0c8	1	Trace parser validation	Empty trace field rejection	not recorded	not tracked before results.tsv	VPU add lowering
2026-04-09	4311142	1	VPU add lowering	tinygrad int add runs on TinyTPU VPU	not recorded	not tracked before results.tsv	VPU binary coverage
2026-04-09	246163c	1	VPU binary coverage	TinyTPU VPU binary op tests	not recorded	not tracked before results.tsv	ReLU lowering
2026-04-09	302b005	1	ReLU lowering	TinyTPU ReLU lowering tests	not recorded	not tracked before results.tsv	Sum lowering
2026-04-09	24a4d34	1	Sum lowering	TinyTPU four-element sum lowering tests	not recorded	not tracked before results.tsv	Full-tile add
2026-04-09	906f337	1	Full-tile ADD	TinyTPU full-tile ADD tests	not recorded	not tracked before results.tsv	Full-tile mul
2026-04-09	1ce885f	1	Full-tile MUL	TinyTPU full-tile MUL tests	not recorded	not tracked before results.tsv	Full-tile max
2026-04-09	2ab8a37	1	Full-tile MAX	TinyTPU full-tile MAX tests	not recorded	not tracked before results.tsv	Full-tile relu
2026-04-09	335e38c	1	Full-tile RELU	TinyTPU full-tile RELU tests	not recorded	not tracked before results.tsv	Signed VPU ops
2026-04-09	10ead63	1	Signed VPU ops	Signed TinyTPU VPU op coverage	not recorded	not tracked before results.tsv	VMEM result parsing
2026-04-09	d41253c	1	VMEM parsing	TinyTPU VMEM result parsing	not recorded	not tracked before results.tsv	VMEM width validation
2026-04-09	3e7354d	1	VMEM parsing	TinyTPU VMEM result width validation	not recorded	not tracked before results.tsv	Malformed VMEM output
2026-04-09	04ee5ed	1	VMEM parsing	Malformed VMEM output diagnostics	not recorded	not tracked before results.tsv	Tinyspec tracking
2026-04-09	961a02d	1	Tinyspec tracking	TODO and tinyspec source saved	not recorded	TODO introduced with tinyspec estimate	VPU-only runtime completion
2026-04-10	b70bf44	1	VPU-only runtime	VPU-only bundles complete without dummy MXU dispatch	not recorded	TODO marked VPU-only runtime progress	Scalar constants
2026-04-10	697817e	1	Scalar ADD constant	TinyTPU scalar add constants covered	not recorded	TODO marked x + scalar	Scalar MUL constant
2026-04-10	0e24b7f	1	Scalar MUL constant	TinyTPU scalar mul constants covered	not recorded	TODO marked x * scalar	Scalar MAX constant
2026-04-10	f5b7622	1	Scalar MAX constant	TinyTPU scalar max constants covered	not recorded	TODO marked maximum x scalar	Less-than compare
2026-04-10	aaecd9a	1	VPU CMPLT	VPU less-than compare hardware backend and tests	not recorded	TODO marked CMPLT	Not-equal compare
2026-04-10	fd72f7d	1	VPU CMPNE	VPU not-equal compare hardware backend and tests	not recorded	TODO marked CMPNE	Subtract
2026-04-10	139ea5e	1	VPU SUB	VPU subtract hardware backend and tests	not recorded	TODO marked SUB	NEG coverage
2026-04-10	1c69ee3	1	NEG coverage	TinyTPU neg lowering through multiply by -1	not recorded	TODO marked NEG	Scalar comparisons
2026-04-10	91bfd49	1	Scalar comparisons	TinyTPU scalar comparison constants covered	not recorded	TODO marked scalar comparison constants	VMEM bundle records
2026-04-10	5969391	1	VMEM bundle records	Profiler roundtrip for VMEM input output records	not recorded	TODO marked bundle record roundtrip	Fork submodule URL
2026-04-10	65ba605	1	Submodule URL	tinygrad submodule points to fork	not recorded	not tracked before results.tsv	Next 50 batch
2026-04-10	3289dc8	50	TinyTPU tinyspec expansion	VPU CMPEQ; reverse scalar sub; grouped scalar constants; lowering dumps; VMEM protocol tests; profiler bundle tooling	make test-vpu: 9 passed, 0 failed; pytest TinyTPU/profiler/run tests: 84 passed	Next 50 iteration plan completed; recommended next work refreshed	Multi-tile elementwise ADD and multiple VMEM output tiles
2026-04-10	2d75e93	1	Multi-tile VPU elementwise	numel>16 VPU binary/unary via chunked tile loop	pytest tiling/parsing: 13 passed; profiler: 17 passed	Marked multi-tile elementwise loops done	Multi-tile test coverage for MUL/SUB/MAX/compare
2026-04-10	8beeabc	1	Multi-tile binary coverage	Multi-tile MUL SUB MAX CMPLT CMPNE CMPEQ tests	pytest backend: 58 passed (sim-backed)	none	Multi-tile scalar const and ReLU coverage
2026-04-10	8daa17e	1	Multi-tile scalar const coverage	Scalar ADD/SUB 17-elem; scalar CMPLT/CMPEQ 32-elem	pytest backend: 62 passed (sim-backed)	none	Multi-tile ReLU coverage
2026-04-10	fbaf5a6	1	Multi-tile ReLU coverage	32-elem and 33-elem (tail) multi-tile ReLU	pytest backend: 64 passed (sim-backed)	none	Multi-tile reverse sub const
2026-04-10	717dba9	1	Multi-tile reverse sub const	Reverse sub const at 17-elem and 32-elem	pytest backend: 66 passed (sim-backed)	none	WHERE op
2026-04-10	016ae86	1	WHERE op	WHERE via multi-instruction VPU bundle (MUL+SUB+MUL+ADD)	pytest backend: 66 passed (sim-backed)	Marked WHERE done	WHERE full-tile and multi-tile coverage
2026-04-10	fd79399	1	WHERE coverage	WHERE full-tile 16-elem and multi-tile 32-elem	pytest backend: 68 passed (sim-backed)	none	AND and OR ops
2026-04-10	6e2fd5e	1	AND and OR ops	AND via MUL, OR via MAX with bool_out flag	pytest backend: 70 passed (sim-backed)	Marked AND OR done	XOR op
2026-04-10	80b1a2f	1	XOR op	XOR via CMPNE with bool_out flag	pytest backend: 71 passed (sim-backed)	Marked XOR done	Multi-tile sum reduction
2026-04-10	ac5451d	1	Multi-tile sum reduction	N-element sum via chunked VPU_SUM_REDUCE + host accumulate	pytest backend: 73 passed (sim-backed)	Marked full-tile and multi-tile sum done	Update recommended next iterations
2026-04-10	2a3c17f	1	Multi-tile AND	Fix grouped binary analyzer for bool logic ops; 32-elem AND	pytest backend: 74 passed (sim-backed)	none	Multi-tile OR/XOR
2026-04-10	34e6f21	1	Multi-tile OR	32-elem OR via multi-tile VPU MAX	pytest backend: 75 passed (sim-backed)	none	Multi-tile XOR
2026-04-10	d7c86e2	1	Multi-tile XOR	32-elem XOR via multi-tile VPU CMPNE	pytest backend: 76 passed (sim-backed)	none	NOT lowering
2026-04-10	9201c54	1	NOT lowering	NOT via CMPNE with bool input detection	pytest backend: 77 passed (sim-backed)	none	Multi-tile NOT
2026-04-10	5c5a0f3	1	Multi-tile NOT	32-elem NOT via multi-tile CMPNE	pytest backend: 78 passed (sim-backed)	none	VPU MAX_REDUCE hardware
2026-04-10	9b87aa1	1	VPU MAX_REDUCE hardware	lane_max reducer and VPU_MAX_REDUCE opcode	make test-vpu: 10 passed; pytest backend: 78 passed	none	MAX reduction lowering
2026-04-10	b449fa9	1	MAX reduction 4-elem	MAX reduction through VPU_MAX_REDUCE	pytest backend: 79 passed (sim-backed)	Marked MAX reduction done	Full-tile MAX reduction
2026-04-10	7ee2bef	1	MAX reduction full-tile	16-elem MAX reduction	pytest backend: 80 passed (sim-backed)	none	Multi-tile MAX reduction
2026-04-10	26d8c06	1	MAX reduction multi-tile	32-elem MAX reduction via chunked VPU_MAX_REDUCE + host max	pytest backend: 81 passed (sim-backed)	Marked multi-tile MAX reduction done	MUL reduction or movement ops
2026-04-10	8f156fb	1	Analyzer fix: complex ops	Reject IDIV/ABS/MOD from RELU and scalar const paths	pytest backend: 81 passed (sim-backed)	none	MINIMUM misdetection
2026-04-10	776a68d	1	Analyzer fix: MINIMUM	Require bool inputs for AND/XOR/OR detection	pytest backend: 81 passed (sim-backed)	none	SHL/SHR hardware
2026-04-10	f8b1142	1	VPU SHL/SHR hardware	VPU_SHL and VPU_SHR opcodes with BSV tests	make test-vpu: 12 passed; pytest backend: 81 passed	none	SHL/SHR lowering
2026-04-10	3bc8fb3	1	SHL lowering	Scalar const SHL through VPU_SHL	pytest backend: 82 passed (sim-backed)	Marked SHL done	SHR lowering
2026-04-10	cfd333c	1	SHR lowering	Scalar const SHR through VPU_SHR	pytest backend: 83 passed (sim-backed)	Marked SHR done	Multi-tile SHL
2026-04-10	ea7a01a	1	Multi-tile SHL	32-elem SHL with scalar const disambiguation	pytest backend: 84 passed (sim-backed)	none	Multi-tile SHR
2026-04-10	fd0e668	1	Multi-tile SHR	32-elem SHR	pytest backend: 85 passed (sim-backed)	none	Full-tile SHL/SHR
2026-04-10	3ce7bc8	1	Full-tile SHL/SHR	16-elem SHL and SHR coverage	pytest backend: 87 passed (sim-backed)	none	Negative reduction coverage
2026-04-10	2b8b5ce	1	Negative reductions	Sum and max with negative int32 values	pytest backend: 89 passed (sim-backed)	none	Loop-based reductions or IDIV
2026-04-10	d7a6851	1	Analyzer fix: clip	Reject clip from RELU by checking WHERE <= STORE	pytest backend: 89 passed (sim-backed)	none	VPU_MIN hardware
2026-04-10	d2c170a	1	VPU_MIN hardware	VPU_MIN opcode with BSV test	make test-vpu: 13 passed; pytest backend: 89 passed	none	minimum lowering
2026-04-10	56e1f2d	1	minimum lowering	minimum(a,b) through VPU_MIN detecting XOR+MAX pattern	pytest backend: 90 passed (sim-backed)	none	Multi-tile minimum
2026-04-10	a1039d6	1	Multi-tile minimum	16-elem and 32-elem minimum coverage	pytest backend: 92 passed (sim-backed)	none	VPU_MIN_REDUCE
2026-04-10	46cd837	1	VPU_MIN_REDUCE hardware	lane_min reducer and VPU_MIN_REDUCE opcode	make test-vpu: 14 passed; pytest backend: 92 passed	none	MIN reduction lowering
2026-04-10	f27b9a5	1	MIN reduction	4/16/32-elem min through VPU_MIN_REDUCE; exclude XOR from MAX_REDUCE	pytest backend: 95 passed (sim-backed)	Marked MIN reduction done	File rename
2026-04-10	9ad63e8	1	Test file rename	test_tinytpu_backend_gemm -> test_tinytpu_backend	pytest backend: 95 passed (sim-backed)	none	Negative MIN
2026-04-10	941b248	1	Negative MIN reduction	min with all-negative int32 values	pytest backend: 96 passed (sim-backed)	none	Scalar MIN const
2026-04-10	d03f172	1	Scalar minimum const	minimum(x, c) via XOR+MAX decomposition detection	pytest backend: 97 passed (sim-backed)	none	Clip support
2026-04-10	a031e37	1	Clip diagnostic	clip correctly reports unsupported (was silently wrong)	pytest backend: 98 passed (sim-backed)	none	Fused clamp lowering or more reductions
2026-04-10	b7e5071	1	Analyzer fix: add+relu	Block grouped binary with CMPLT+WHERE (fused epilogue)	pytest backend: 98 passed (sim-backed)	none	Add+relu diagnostic test
2026-04-10	4cab815	1	Add+relu diagnostic	Fused add+relu correctly reports unsupported	pytest backend: 99 passed (sim-backed)	none	Multi-tile scalar const coverage
2026-04-10	b750920	1	Multi-tile min scalar const	32-elem minimum(x, 10)	pytest backend: 100 passed (sim-backed)	none	More multi-tile coverage
2026-04-10	bb9f4b9	1	Multi-tile max scalar const	32-elem maximum(x, 10)	pytest backend: 101 passed (sim-backed)	none	More multi-tile coverage
2026-04-10	f97cb31	1	Multi-tile CMPNE scalar const	32-elem x != 10	pytest backend: 102 passed (sim-backed)	none	WHERE tail coverage
2026-04-10	804c46b	1	WHERE tail coverage	17-elem WHERE with tail handling	pytest backend: 103 passed (sim-backed)	none	Signed minimum
2026-04-10	0c56fc3	1	Signed minimum	Minimum with negative values on both sides	pytest backend: 104 passed (sim-backed)	none	Negative min const
2026-04-10	f3b0c0b	1	Negative min const	minimum(x, -2)	pytest backend: 105 passed (sim-backed)	none	Diagnostic tests
2026-04-10	bb86956	1	Diagnostic tests	IDIV/MOD/ABS unsupported + minimum regression	pytest backend: 109 passed (sim-backed)	none	Fused clamp or CAST lowering
2026-04-11	e1796ef	1	tests: fix stale WAIT_MXU opcode	VPU-only bundles end with HALT not WAIT_MXU	pytest: 193 passed	none	IDIV/MOD/abs multi-tile coverage
2026-04-11	68f8ccb	1	full-tile and multi-tile abs tests	abs works for all numel via VPU_PROGRAM tile loop	pytest: 197 passed	none	IDIV/MOD multi-tile coverage
2026-04-11	8ecc187	1	full-tile and multi-tile IDIV/MOD tests	truncation semantics documented	pytest: 203 passed	none	scalar broadcast coverage
2026-04-11	a8ff56b	1	scalar broadcast and cast coverage	MUL/SUB/MAX size-1 broadcast; int32<->bool cast	pytest: 211 passed	none	clip/fused coverage
2026-04-11	7f4aeb1	1	clip and fused add+relu multi-tile	16-elem and 32-elem coverage	pytest: 215 passed	none	row-wise sum
2026-04-11	bf4ef32	1	row-wise sum via VPU_SUM_REDUCE	VPU_ROWSUM: nrows x 4 -> nrows sums	pytest: 219 passed	marked row-wise sum done	row-wise max/min
2026-04-11	27da240	1	row-wise max and min reductions	discriminate sum/max/min by UOp body; VPU_MAX/MIN_REDUCE	pytest: 223 passed	none	tensor-tensor IDIV/MOD; keepdim
2026-04-11	91b9178	1	tensor-tensor IDIV/MOD; rowsum keepdim; rowmax/min 3x4	all shape counts for row reductions	pytest: 229 passed	none	vpu_rowsum multi-tile rows
2026-04-11	40d41db	1	vpu_rowsum arbitrary nrows via 4-row tile chunking	5x4 and 8x4 sum/max/min	pytest: 233 passed	TODO updated	column-wise sum or movement ops
2026-04-11	f5652aa	50	TinyTPU 50-iteration batch	Grouped scalar-const 2D lowering; HOST_ROWREDUCE/COLREDUCE; row/col reductions for arbitrary shapes; _tasm helpers; TASM bundle roundtrips; 2D coverage for all ops	pytest: 399 passed (+166 from 233 baseline)	TODO updated; row/col reductions marked done; 2D ops marked done	GEMM epilogues; XLU-backed col reductions; fused kernel detection
2026-04-10	336dfb1	10	multi-WMMA + hardware epilogue	Multi-WMMA GEMM lowering; SXU_LOAD_MXU_RESULT BSV instruction; hardware-fused bias+ReLU epilogue via MXU→VPU pipeline	pytest: 340 passed	GEMM epilogues marked done; multi-WMMA marked done; SXU_LOAD_MXU_RESULT added	hardware epilogue for multi-K-tile; movement ops; col-wise VPU reductions
2026-04-11	96c1d95	1	VPU_NOT BSV opcode	VPU_NOT hardware instruction (opcode 26) with testbench	make test-vpu: 20/20; pytest: 340 passed	none	migrate scalar-const ops to SXU_PROGRAM
2026-04-11	1f341a7	1	scalar-const + bool SXU_PROGRAM migration	scalar-const binary ops and bool AND/OR/XOR/NOT via SXU_PROGRAM	pytest: 340 passed	scalar-const and bool marked done	migrate WHERE to SXU_PROGRAM
2026-04-11	f026837	1	WHERE SXU_PROGRAM migration	WHERE ternary select via 4-instruction MUL/SUB/MUL/ADD SXU_PROGRAM	pytest: 340 passed	WHERE marked done	migrate multi-step VPU_PROGRAM patterns
2026-04-11	faeb937	1	abs/clip/MOD/CMPEQ SXU_PROGRAM	abs clip MOD CMPEQ patterns via multi-step SXU_PROGRAM	pytest: 340 passed	multi-step patterns marked done	migrate reductions to SXU_PROGRAM
2026-04-11	96abba7	2	multi-step + data-path ALU fix	abs/clip/MOD/CMPEQ via SXU_PROGRAM; fix RANGE/GROUP ALU filtering	pytest: 340 passed; SXU_PROGRAM 97/263	multi-step marked done; reduction deferred	scalar broadcast in BSV
2026-04-11	09a5978	1	data-path ALU + SUB/CMPEQ/clip fixes	SUB tensor-tensor, CMPEQ RANGE, clip const detection via SXU_PROGRAM	pytest: 340 passed; SXU_PROGRAM 143/263 (54%)	none	MIN decomposition, scalar broadcast
2026-04-11	4195857	1	reverse SUB + ALU refactor	scalar-const reverse SUB, data-path ALU in multistep renderer	pytest: 340 passed; SXU_PROGRAM 146/263 (55%)	none	MIN decomposition, fused add+relu, scalar broadcast
2026-04-11	2ce9812	1	tensor-tensor MIN via SXU_PROGRAM	MIN XOR+MAX decomposition detected and emitted as VPU_MIN	pytest: 340 passed	none	scalar-const MIN, fused add+relu, scalar broadcast
2026-04-11	4c7b394	1	fused add+relu SXU_PROGRAM	fused add+relu via ADD+RELU SXU_PROGRAM	pytest: 340 passed; SXU_PROGRAM 157/263 (59%)	none	scalar broadcast, scalar-const MIN/MOD, reductions
2026-04-11	10faf9d	1	scalar broadcast + reductions SXU_PROGRAM	scalar broadcast, SUM/MAX/MIN scalar reduce via SXU_PROGRAM with cross-sublane accum	pytest: 340 passed; SXU_PROGRAM 180/263 (68%)	scalar broadcast + reductions marked done	row/col reduce axis detection, scalar-const DIV/MOD
2026-04-11	4d03968	2	VPU_SELECT/COPY + RELU/SUB fix	VPU_SELECT hardware opcode; WHERE 2-instr; RELU/SUB RANGE fix	VPU: 22/22; pytest: 340 passed; SXU_PROGRAM 191/263 (72%)	SELECT marked done in plan	host fallback renderers, dead code deletion
2026-04-11	057b143	3	legacy renderer + dead code deletion	_render_legacy_descriptor; delete _exec_vpu_where/unary, _build_vpu_where, dead analyze blocks	pytest: 340 passed; 2810 lines (-267)	legacy renderer decouples from analyze	delete more dead analyze code
2026-04-11	e7fd99d	4	dead code deletion batch	delete _render_wmma_descriptor, dead analyze blocks, _exec_vpu_where/unary, slim diag	pytest: 340 passed; 2670 lines	analyze slimmed 905→556; _render_wmma deleted	analyze still 556 lines for scalar-const DIV/MIN/MOD
2026-04-11	TBD	2	SXU_PROGRAM migration	row-broadcast binary and scalar-const minimum now lower through SXU_PROGRAM	pytest rowbc: 3 passed; pytest lowering_dump: 14 passed; pytest minimum const: 4 passed	marked row-broadcast migration done; analyze narrowed to scalar-const DIV/MOD	scalar-const DIV and MOD still use legacy renderer
2026-04-11	TBD	4	first-class select primitive	SXU_DISPATCH_SELECT end-to-end: BSV opcode, runtime/TASM support, tinygrad WHERE lowering	pytest where: 4 passed; test-sxu: 3 passed; test_tasm select: 2 passed	WHERE cleanup note now points at first-class SXU_DISPATCH_SELECT	next primitive slice is scalar/row/col broadcast ISA cleanup
2026-04-11	TBD	4	explicit broadcast primitives	SXU/XLU scalar,row,col broadcast opcodes plus row-bias lowering through BROADCAST_ROW	test-sxu: 6 passed; pytest rowbc: 3 passed; pytest rowbc lowering: 1 passed; test_tasm broadcast: 6 passed	marked explicit broadcasts and XLU-backed broadcast primitives done	next slice is col/tile reductions or scalar-broadcast lowering through new primitive
2026-04-11	TBD	2	scalar broadcast primitive lowering	scalar-broadcast SXU_PROGRAM now emits BROADCAST_SCALAR in tinygrad backend	pytest scalar broadcast: 7 passed	constants and scalar broadcasting marked done	next slice is col/tile reductions
2026-04-11	3fae151	1	col/tile reduce VPU primitives	VPU_{SUM,MAX,MIN}_REDUCE_{COL,TILE} opcodes 29-34 with BSV tests; Python opcode table; uses_scalar_broadcast drive-by init fix	make test-vpu: 28/28; pytest backend: 343 passed	marked col/tile reduce primitives done in plan	wire col/tile reduce through SXU dispatch and migrate HOST_COLREDUCE + scalar reductions to use new primitives
2026-04-11	6fbea28	1	col/tile reduce end-to-end wiring	TASM mnemonics for new opcodes; 6 TASM roundtrip tests; 2 runtime-sim bundle tests proving VPU_SUM_REDUCE_TILE/COL reachable end-to-end; fix stale test_vpu_ops_cover_full_range count	pytest tests/: 467 passed (2 pre-existing import failures unrelated)	none	migrate tinygrad HOST_COLREDUCE and scalar reductions to emit new primitives
2026-04-11	2091734	1	scalar SUM via VPU_SUM_REDUCE_TILE	scalar SUM reductions now emit opcode 32 and rely on zero-padding identity; output parser reads scalar from [0] via reduce_layout	pytest backend: 343 passed	none	migrate MAX/MIN scalar reductions with identity padding
2026-04-11	7f4920a	1	scalar MAX via VPU_MAX_REDUCE_TILE	VMEM pad_value for identity padding; scalar MAX emits opcode 33 with INT32_MIN pad	pytest backend: 343 passed	none	scalar MIN + col-reduce renderer
2026-04-11	f6920ec	1	scalar MIN via VPU_MIN_REDUCE_TILE	scalar MIN emits opcode 34 with INT32_MAX pad	pytest backend: 343 passed	none	col-reduce SUM via SXU_PROGRAM
2026-04-11	5699262	1	col-reduce SUM single-tile	N<=4 M=4 SUM lowers to VPU_SUM_REDUCE_COL; added 4x4 and 3x4 tests	pytest backend: 345 passed	none	col-reduce MAX/MIN with pad
2026-04-11	00d0b57	1	col-reduce MAX/MIN single-tile	MAX/MIN use INT32 identity pad; single-tile N<=4 M=4	pytest backend: 349 passed	none	narrow width M<4
2026-04-11	e56c194	1	col-reduce narrow M<4	MATRIX_TILE VMEM mode packs NxM slice into 4x4 with identity pad	pytest backend: 352 passed	none	multi row-tile
2026-04-11	5e5a8de	1	col-reduce multi row-tile (N>4)	split into ceil(N/4) row-tiles, combine via VPU_ADD/MAX/MIN	pytest backend: 352 passed	none	wide M>4
2026-04-11	1bda80d	1	col-reduce wide M>4	col-tile iteration emits multi-output tiles with offset=col_base	pytest backend: 352 passed	none	full N>4 M>4 test coverage
2026-04-11	0055ee6	1	col-reduce multi row x col tests	6x6 SUM, 5x7 MAX, 7x5 MIN exercising ceil(N/4) x ceil(M/4) path	pytest backend: 355 passed	marked column-wise and full-tile reductions done	dead code cleanup
2026-04-11	1c90bff	1	drop dead reduce_layout plumbing	row-layout branch and reduce_src_size fields removed; scalar reduction path always extracts [0]	pytest backend: 355 passed	none	migrate row reductions to SXU_PROGRAM
2026-04-11	cd460ac	1	row-reduce SUM single-tile	_render_rowreduce_sxu_program for N<=4 M<=4 SUM; output parser extract=row_heads	pytest backend: 355 passed	none	extend to MAX/MIN
2026-04-11	879df4f	1	row-reduce MAX/MIN single-tile	INT32 identity padding on partial cols	pytest backend: 355 passed	none	multi row-tile
2026-04-11	5def932	1	row-reduce multi row-tile	ceil(N/4) row-tiles each emit own row_heads output	pytest backend: 355 passed	none	wide M>4
2026-04-11	689c76f	1	row-reduce wide M>4	combine col-tile partial row-reductions with VPU_ADD/MAX/MIN	pytest backend: 355 passed	none	delete legacy host paths
2026-04-11	f952f1d	1	delete legacy row/col-reduce host paths	remove VPU_ROWSUM, HOST_ROWREDUCE, HOST_COLREDUCE exec methods and dispatch; -113 lines	pytest backend: 355 passed	marked row/col reductions fully hardware-backed	none
2026-04-12	5564628	1	float32 VPU dispatch	Remap ADD/MUL/SUB/MAX/CMPLT to FADD/FMUL/FSUB/FMAX/FCMPLT for float tensors	pytest backend: 379 passed	none	FP tensor-tensor divide requires RECIPROCAL detection
2026-04-12	604e3a0	1	Float32 binary coverage	FADD/FMUL/FSUB/FMAX tests	pytest backend: 383 passed	none	FCMPLT
2026-04-12	2ed7c53	1	Float32 FCMPLT	Less-than on float tensors	pytest backend: 384 passed	none	scalar float const
2026-04-12	b1ddb6a	1	Float32 scalar const	x + 2.5, x * 3.0 with bitcast const	pytest backend: 386 passed	none	multi-tile float
2026-04-12	2255026	1	Multi-tile float32	32-elem FADD and scalar FMUL	pytest backend: 388 passed	none	Reciprocal + float div
2026-04-12	e54347d	1	Float32 reciprocal/div	FRECIP hardware works; scalar float div	pytest backend: 390 passed	none	Signed float
2026-04-12	2e47fff	1	Signed float	Negative value FADD/FMUL	pytest backend: 392 passed	none	Tensor-tensor fdiv
2026-04-12	58402fc	1	fdiv regression fence	xfail test documents broken tensor-tensor fdiv	pytest backend: 393 passed	none	RECIPROCAL UOp detection
2026-04-12	a6ba2dc	1	TODO update	marked float32 policy complete	pytest backend: 393 passed	float32 policy checked	RECIPROCAL UOp detection
2026-04-12	0190499	1	float tensor-tensor divide	FRECIP+FMUL SXU program; flipped xfail to passing	pytest backend: 393 passed	none	Complex float math rejection
2026-04-12	096b6a5	1	Reject sqrt/log2/sin/exp2	Guard analyze_tinytpu_uops on BITCAST; tighten HOST_UNARY	pytest backend: 393 passed	none	Diagnostic tests
2026-04-12	904f568	1	Math diagnostic tests	sqrt/log2/sin/exp2 correctly unsupported	pytest backend: 397 passed	none	Multi-tile fdiv
2026-04-12	f820c67	1	Multi-tile fdiv + frecip	32-elem coverage	pytest backend: 399 passed	none	Float minimum
2026-04-12	227bef3	1	Float minimum	FCMPLT+SELECT multistep SXU program	pytest backend: 400 passed	none	Multi-tile fmin
2026-04-12	e0352d9	1	Multi-tile fmin/fmax	32-elem coverage	pytest backend: 402 passed	none	Float RELU
2026-04-12	3adc7a6	1	Float RELU	VPU_RELU works on float sign bit; VECTORIZE pattern match	pytest backend: 403 passed	none	Multi-tile frelu
2026-04-12	97531b7	1	Multi-tile frelu	full-tile and 32-elem coverage	pytest backend: 405 passed	none	Float WHERE
2026-04-12	8cf7f02	1	Float WHERE	ternary select on float tensors	pytest backend: 406 passed	none	Cast lowering or movement ops
2026-04-12	c8a3baf	1	Float minimum scalar const	FCMPLT+SELECT with broadcast const	pytest backend: 407 passed	none	Float reductions
2026-04-12	6e60838	1	Reject float reductions	Integer VPU_*_REDUCE on float bits would corrupt; diagnostic tests	pytest backend: 410 passed	none	Casts
2026-04-12	170d3dc	1	int32↔float32 casts	VPU_I2F / VPU_F2I renderer; supports single and multi-tile	pytest backend: 413 passed	float32 cast coverage	Negative scalar float const
2026-04-12	951c381	1	Negative scalar float min/max	coverage for -2.0 constant	pytest backend: 415 passed	none	Float cmp
2026-04-12	b4b6daf	1	Float CMPNE/CMPEQ/CMPGT	comparison coverage	pytest backend: 418 passed	none	Float neg
2026-04-12	ef21a91	1	Float neg	single and multi-tile	pytest backend: 420 passed	none	Float scalar sub
2026-04-12	65daed8	1	Float scalar sub	x-c and c-x coverage	pytest backend: 422 passed	none	Cast round-trip
2026-04-12	b6965d2	1	Cast round-trip	Fused same-dtype chain lowered to COPY	pytest backend: 423 passed	cast round-trip	Float reductions via host or FADD tree
2026-04-12	8778ea1	1	Float multi-tile tensor-tensor sub	FSUB works on 32-elem tensor-tensor	pytest backend: 411 passed	none	Float ABS
2026-04-12	9a24751	1	Float signed multi-tile FMUL	32-elem signed FMUL	pytest backend: 412 passed	none	Float ABS
2026-04-12	a31f0f0	1	Float multi-tile WHERE	32-elem float select	pytest backend: 413 passed	none	Float ABS
2026-04-12	85459c7	1	Float multi-tile F2I cast	32-elem F2I	pytest backend: 414 passed	none	Float ABS
2026-04-12	77ee2d2	1	Float multi-tile scalar fdiv	32-elem scalar fdiv	pytest backend: 415 passed	none	Float ABS
2026-04-12	ef5df76	1	Float multi-tile scalar maximum	32-elem x.maximum(0.0)	pytest backend: 416 passed	none	Float ABS
2026-04-12	30fae5a	1	Float multi-tile scalar minimum	32-elem x.minimum(0.0)	pytest backend: 417 passed	none	Float ABS
2026-04-12	cd0caea	1	Float scalar-const FCMPLT	x<c single and multi-tile	pytest backend: 419 passed	none	Float ABS
2026-04-12	8ea1f9b	1	Float scalar-const FCMPGT/FCMPNE	x>c and x!=c	pytest backend: 421 passed	none	fcmpeq scalar broken
2026-04-12	ae761f7	1	Float signed multi-tile FADD	32-elem signed FADD	pytest backend: 422 passed	none	fcmpeq scalar broken
2026-04-12	44d6ab3	1	Float full-tile fneg	16-elem fneg	pytest backend: 423 passed	none	fcmpeq scalar broken
2026-04-12	a8698a4	1	Float three-tile fneg	48-elem fneg	pytest backend: 424 passed	none	fcmpeq scalar broken
2026-04-12	5ee86c0	1	Float multi-tile rev scalar fmul	3.0*x over 32 elems	pytest backend: 425 passed	none	fcmpeq scalar broken
2026-04-12	d20956d	1	Float multi-tile rev scalar fsub	c-x over 32 elems	pytest backend: 426 passed	none	fcmpeq scalar broken
2026-04-12	0270e88	1	Float multi-tile FCMPGT	32-elem a>b	pytest backend: 427 passed	none	fcmpeq scalar broken
2026-04-12	a316731	1	Float multi-tile FCMPLT	32-elem a<b	pytest backend: 428 passed	none	fcmpeq scalar broken
2026-04-12	0dc1da4	1	Float multi-tile FCMPNE	32-elem a!=b	pytest backend: 429 passed	none	fcmpeq scalar broken
2026-04-12	490f8b7	1	Float multi-tile FCMPEQ	32-elem a==b	pytest backend: 430 passed	none	fcmpeq scalar broken
2026-04-12	19448bf	1	Float three-tile frelu	48-elem frelu	pytest backend: 431 passed	none	fcmpeq scalar broken
2026-04-12	a844524	1	Float three-tile WHERE	48-elem signed WHERE	pytest backend: 432 passed	none	fcmpeq scalar broken
2026-04-12	afffbe9	1	Float three-tile scalar fadd	48-elem x+c	pytest backend: 433 passed	none	fcmpeq scalar broken
2026-04-12	edf521c	1	Float three-tile scalar fsub	48-elem x-c	pytest backend: 434 passed	none	fcmpeq scalar broken
2026-04-12	b53270b	1	Float three-tile fadd tt	48-elem a+b	pytest backend: 435 passed	none	fcmpeq scalar broken
2026-04-12	200b59f	1	Float three-tile fsub tt	48-elem a-b	pytest backend: 436 passed	none	fcmpeq scalar broken
2026-04-12	eb876fe	1	Float three-tile fmul tt	48-elem a*b	pytest backend: 437 passed	none	fcmpeq scalar broken
2026-04-12	aa53b89	1	Float three-tile fmin tt	48-elem min(a,b)	pytest backend: 438 passed	none	fcmpeq scalar broken
2026-04-12	bb30a16	1	Float three-tile fmax tt	48-elem max(a,b)	pytest backend: 439 passed	none	fcmpeq scalar broken
2026-04-12	2622240	1	Float neg multi-tile frecip	12-elem 1/neg	pytest backend: 440 passed	none	fcmpeq scalar broken
2026-04-12	8010b18	1	Float all-negative F2I	F2I preserves trunc toward 0 for negatives	pytest backend: 441 passed	none	fcmpeq scalar broken
2026-04-12	196a018	1	Signed full-tile I2F	16-elem signed I2F	pytest backend: 442 passed	none	fcmpeq scalar broken
2026-04-12	33fa4a3	1	Rev scalar fadd	c+x 32-elem	pytest backend: 443 passed	none	fcmpeq scalar broken
2026-04-12	449fcb8	1	Signed multi-tile I2F	32-elem signed I2F	pytest backend: 444 passed	none	fcmpeq scalar broken
2026-04-12	093b6b7	1	Full-tile frecip	16-elem 1/x	pytest backend: 445 passed	none	fcmpeq scalar broken
2026-04-12	51533dc	1	Negative scalar fmul	x*-c	pytest backend: 446 passed	none	fcmpeq scalar broken
2026-04-12	509abc4	1	Negative scalar fadd	x+-c	pytest backend: 447 passed	none	fcmpeq scalar broken
2026-04-12	7a6ec21	1	Signed fdiv tt	signed a/b	pytest backend: 448 passed	none	fcmpeq scalar broken
2026-04-12	ca75687	1	Float WHERE derived cond	boolean cond from >	pytest backend: 449 passed	none	fcmpeq scalar broken
2026-04-12	95271bc	1	Positive scalar fmax mt	x.maximum(8.0) 32-elem	pytest backend: 450 passed	none	fcmpeq scalar broken
2026-04-12	f95342e	1	Positive scalar fmin mt	x.minimum(5.0) 32-elem	pytest backend: 451 passed	none	fcmpeq scalar broken
2026-04-12	ed6bd02	1	Signed full-tile fsub tt	16-elem signed	pytest backend: 452 passed	none	fcmpeq scalar broken
2026-04-12	4cbd168	1	Signed full-tile fadd tt	16-elem signed	pytest backend: 453 passed	none	fcmpeq scalar broken
2026-04-12	f9ab691	1	Signed full-tile fmul tt	16-elem signed	pytest backend: 454 passed	none	fcmpeq scalar broken
2026-04-12	dc2da35	1	2D fadd	2x2 float add	pytest backend: 455 passed	none	fcmpeq scalar broken
2026-04-12	2b579ec	1	2D fmul	2x2 float mul	pytest backend: 456 passed	none	fcmpeq scalar broken
2026-04-12	b7c2f76	1	Negative const FCMPLT	x<-c	pytest backend: 457 passed	none	fcmpeq scalar broken
2026-04-12	725f6c1	1	Negative const FCMPGT	x>-c	pytest backend: 458 passed	none	fcmpeq scalar broken
2026-04-12	645b520	1	Negative const FCMPNE	x!=-c	pytest backend: 459 passed	none	fcmpeq scalar broken
2026-04-12	690d37c	1	Four-tile frecip	64-elem 1/x	pytest backend: 460 passed	none	fcmpeq scalar broken
2026-04-12	9c0caae	1	Four-tile scalar fadd	64-elem x+c	pytest backend: 461 passed	none	fcmpeq scalar broken
2026-04-12	3d99d7c	1	Four-tile fdiv tt	64-elem a/b	pytest backend: 462 passed	none	fcmpeq scalar broken
2026-04-12	f1abcaa	1	Four-tile scalar fmul	64-elem x*c	pytest backend: 463 passed	none	fcmpeq scalar broken
2026-04-12	c1489fd	1	Four-tile scalar fsub	64-elem x-c	pytest backend: 464 passed	none	fcmpeq scalar broken
2026-04-12	7dbea6a	1	Four-tile fneg	64-elem fneg	pytest backend: 465 passed	none	fcmpeq scalar broken
2026-04-12	b21b5af	1	Four-tile frelu	64-elem frelu	pytest backend: 466 passed	none	fcmpeq scalar broken
2026-04-12	65cf37e	1	Four-tile FCMPLT scalar	64-elem x<c	pytest backend: 467 passed	none	fcmpeq scalar broken
2026-04-12	ffd1ed3	1	Four-tile fadd tt	64-elem a+b	pytest backend: 468 passed	none	fcmpeq scalar broken
2026-04-12	0dd9943	1	2D fmax tt	2x2 signed max	pytest backend: 469 passed	none	fcmpeq scalar broken
2026-04-12	d92e64f	1	2D fmin tt	2x2 signed min	pytest backend: 470 passed	none	fcmpeq scalar broken
2026-04-12	0c8b519	1	2D fsub tt	2x2 float sub	pytest backend: 471 passed	none	fcmpeq scalar broken
2026-04-12	611d9df	1	2D fcmpeq tt	2x2 float eq	pytest backend: 472 passed	none	fcmpeq scalar broken
2026-04-12	ec25b92	1	2D fwhere	2x2 float select	pytest backend: 473 passed	none	fcmpeq scalar broken
2026-04-12	b1a72a1	1	2D fneg	2x2 fneg	pytest backend: 474 passed	none	fcmpeq scalar broken
2026-04-12	0a778d8	1	2D frelu	2x2 frelu	pytest backend: 475 passed	none	fcmpeq scalar broken
2026-04-12	7f68707	1	2D fcmplt tt	2x2 float lt	pytest backend: 476 passed	none	fcmpeq scalar broken
2026-04-12	acf9d08	1	2D frecip	2x2 1/x	pytest backend: 477 passed	none	fcmpeq scalar broken
2026-04-12	548a6bb	1	2D scalar fmul	2x2 x*c	pytest backend: 478 passed	none	fcmpeq scalar broken
2026-04-12	3f239b6	1	2D scalar fadd	2x2 x+c	pytest backend: 479 passed	none	fcmpeq scalar broken
2026-04-12	126bf46	1	Five-tile scalar fadd	80-elem x+c	pytest backend: 480 passed	none	fcmpeq scalar broken
2026-04-12	b49e284	1	Five-tile fadd tt	80-elem a+b	pytest backend: 481 passed	none	fcmpeq scalar broken
2026-04-12	7fd5e21	1	3D scalar fmul	2x2x2 x*c	pytest backend: 482 passed	none	fcmpeq scalar broken
2026-04-12	1063512	1	Float ABS via FSUB/FMAX	Src-dtype-aware op dispatch in ABS renderer	pytest backend: 483 passed	float abs correctness	fcmpeq scalar broken
2026-04-12	f69cfe1	1	Float scalar fcmpeq	Pack float bits for broadcast const	pytest backend: 485 passed	fcmpeq scalar correctness	fclip chain broken
2026-04-12	f50036b	1	Full-tile fabs	16-elem via FSUB/FMAX	pytest backend: 486 passed	none	fclip chain broken
2026-04-12	2963055	1	2D fabs	2x2 via FSUB/FMAX	pytest backend: 487 passed	none	fclip chain broken
2026-04-12	00a1440	1	Three-tile fabs	48-elem via FSUB/FMAX	pytest backend: 488 passed	none	fclip chain broken
2026-04-12	e441742	1	Four-tile fabs	64-elem via FSUB/FMAX	pytest backend: 489 passed	none	fclip chain broken
2026-04-12	773e68b	1	Fractional FCMPEQ scalar	x==2.5 via bit-pattern broadcast	pytest backend: 490 passed	none	fclip chain broken
2026-04-12	a0bcc67	1	Multi-tile scalar FCMPEQ	x==c over 32 elems	pytest backend: 491 passed	none	fclip chain broken
2026-04-12	e3dbb56	1	Five-tile fabs	80-elem via FSUB/FMAX	pytest backend: 492 passed	none	fclip chain broken
2026-04-12	8169db8	1	3D fabs	2x2x2 via FSUB/FMAX	pytest backend: 493 passed	none	fclip chain broken
2026-04-12	241578c	1	Fractional fabs	±1.5..4.5 via FSUB/FMAX	pytest backend: 494 passed	none	fclip chain broken
2026-04-12	fd51dbe	1	Negative-only mt fabs	32-elem all-neg	pytest backend: 495 passed	none	fclip chain broken
2026-04-12	6e5a621	1	Single-elem fabs	1-elem fabs	pytest backend: 496 passed	none	fclip chain broken
2026-04-12	7e56f9b	1	Zero-mix fabs	±0/±1 fabs	pytest backend: 497 passed	none	fclip chain broken
2026-04-12	3979a64	1	Scaled mt fabs	32-elem 0.5x	pytest backend: 498 passed	none	fclip chain broken
2026-04-12	205f781	1	Negative FCMPEQ scalar	x==-2.0	pytest backend: 499 passed	none	fclip chain broken
2026-04-12	f0ab6b4	1	Fractional mt FCMPEQ scalar	32-elem 0.5x==4.0	pytest backend: 500 passed	none	fclip chain broken
2026-04-12	660fc16	1	Fractional FCMPGT scalar	x>1.5	pytest backend: 501 passed	none	fclip chain broken
2026-04-12	fc4db3b	1	Fractional FCMPLT scalar	x<1.5	pytest backend: 502 passed	none	fclip chain broken
2026-04-12	eedb6eb	1	Fractional FCMPNE scalar	x!=2.5	pytest backend: 503 passed	none	fclip chain broken
2026-04-12	46c008b	1	2D FCMPEQ scalar	2x2 x==1.0	pytest backend: 504 passed	none	fclip chain broken
2026-04-12	834acc2	1	5x3 fabs	2D non-square fabs	pytest backend: 505 passed	none	fclip chain broken
2026-04-12	f54706a	1	3x4 fabs	2D non-square fabs	pytest backend: 506 passed	none	fclip chain broken
2026-04-12	364de51	1	4x4 fabs	2D square fabs	pytest backend: 507 passed	none	fclip chain broken
2026-04-12	874944d	1	2D frac fneg	2x2 ±1.5..4.5	pytest backend: 508 passed	none	fclip chain broken
2026-04-12	419b15b	1	3x3 frelu	2D 3x3 signed	pytest backend: 509 passed	none	fclip chain broken
2026-04-12	dd99db8	1	3x3 fneg	3x3 fneg	pytest backend: 510 passed	none	fclip chain broken
2026-04-12	0131fc3	1	3x3 fadd tt	3x3 a+b	pytest backend: 511 passed	none	fclip chain broken
2026-04-12	5547247	1	3x3 fmul tt	3x3 a*b	pytest backend: 512 passed	none	fclip chain broken
2026-04-12	dd468f6	1	3x3 fsub tt	3x3 a-b	pytest backend: 513 passed	none	fclip chain broken
2026-04-12	a978400	1	3x3 scalar fsub	3x3 x-0.5	pytest backend: 514 passed	none	fclip chain broken
2026-04-12	c550647	1	3x3 scalar fmul	3x3 x*0.5	pytest backend: 515 passed	none	fclip chain broken
2026-04-12	02bfecd	1	3x3 scalar fadd	3x3 x+0.5	pytest backend: 516 passed	none	fclip chain broken
2026-04-12	dfa25b7	1	3x3 FCMPLT scalar	3x3 x<4.0	pytest backend: 517 passed	none	fclip chain broken
2026-04-12	7aeb636	1	2x3 fsub tt	2x3 fsub	pytest backend: 518 passed	none	fclip chain broken
2026-04-12	c10fad0	1	3-elem mixed fabs	+/- float abs	pytest backend: 519 passed	none	fclip chain broken
2026-04-12	a9014e8	1	2-elem neg fabs	[-1.5,-2.5]	pytest backend: 520 passed	none	fclip chain broken
2026-04-12	0acadcb	1	5-elem neg fabs	-1..-5	pytest backend: 521 passed	none	fclip chain broken
2026-04-12	4805611	1	5-elem frelu	signed -2..2	pytest backend: 522 passed	none	fclip chain broken
2026-04-12	c930667	1	2D fcmpgt tt	2x2 float gt	pytest backend: 523 passed	none	fclip chain broken
2026-04-12	2026-04-12	67f7133	1	2D fcmpne tt	2x2 float ne	pytest backend: 524 passed	none	fclip chain broken
2026-04-12	914f8a7	1	4x4 scalar fadd	4x4 x+c	pytest backend: 525 passed	none	fclip chain broken
2026-04-12	cf461c5	1	4x4 scalar fmul	4x4 x*c	pytest backend: 526 passed	none	fclip chain broken
2026-04-12	abaf7ab	1	4x4 scalar fsub	4x4 x-c	pytest backend: 527 passed	none	fclip chain broken
2026-04-12	d84ee77	1	4x4 fneg	4x4 -x	pytest backend: 528 passed	none	fclip chain broken
2026-04-12	a08a7c7	1	4x4 frelu	4x4 signed	pytest backend: 529 passed	none	fclip chain broken
2026-04-12	40f9041	1	4x4 FCMPLT scalar	4x4 x<c	pytest backend: 530 passed	none	fclip chain broken
2026-04-12	a7a0b1a	1	Positive scalar fadd mt	x+5.0 32-elem	pytest backend: 532 passed	none	fclip chain broken
2026-04-12	a6f95d2	1	fsub -c mt	x-(-3.0) 32-elem	pytest backend: 533 passed	none	fclip chain broken
2026-04-12	cdfb818	1	Fwhere signed rhs mt	32-elem lhs/-lhs	pytest backend: 534 passed	none	fclip chain broken
2026-04-12	9facf40	1	Signed 3-tile fadd tt	48-elem signed	pytest backend: 535 passed	none	fclip chain broken
2026-04-12	02a2d66	1	Pos-only frelu	identity relu 16-elem	pytest backend: 536 passed	none	fclip chain broken
2026-04-12	3bb9f84	1	2x3 frecip	2D 2x3 recip	pytest backend: 537 passed	none	fclip chain broken
2026-04-12	244f0f5	1	3x3 fdiv tt	3x3 a/b	pytest backend: 538 passed	none	fclip chain broken
2026-04-12	32df07d	1	3-elem I2F	positive ints	pytest backend: 540 passed	none	fclip chain broken
2026-04-12	4deb71b	1	2D F2I	2x2 F2I	pytest backend: 541 passed	none	fclip chain broken
2026-04-12	591b503	1	Three-tile I2F	48-elem I2F	pytest backend: 542 passed	none	fclip chain broken
2026-04-12	376d251	1	Three-tile F2I	48-elem signed F2I	pytest backend: 543 passed	none	fclip chain broken
2026-04-12	b0ad697	1	3x2 fabs	3x2 float abs	pytest backend: 544 passed	none	fclip chain broken
2026-04-12	8619c82	1	Scalar-numerator fdiv (c/x)	FRECIP+FMUL when src_params=1+RECIPROCAL	pytest backend: 546 passed	c/x fixed	fclip chain broken
2026-04-12	fe4ea03	3	Legacy descriptor: IDIV/MOD SXU + HOST_BINARY delete	Scalar-const IDIV/MOD now SXU_PROGRAM, HOST_BINARY dead code removed	pytest backend: 547 passed	Milestone 2 progress + Milestone 4 done	3 pre-existing colbc regressions
2026-04-12	ffe4d01	1	Legacy descriptor: bool cast SXU	bool->int32 cast emits COPY via SXU_PROGRAM	pytest backend: 547 passed	Milestone 2 near-done	3 pre-existing colbc regressions
2026-04-12	a208ba7	2	Legacy: RECIPROCAL + tensor-tensor IDIV/MOD	RECIPROCAL via FRECIP SXU; divmod renderer extended to 2-param tt case	pytest backend: 547 passed	Milestone 2 + 5 progress	3 pre-existing colbc regressions
2026-04-12	967683e	1	Legacy: TRUNC SXU	TRUNC via F2I+I2F SXU_PROGRAM round-trip	pytest backend: 547 passed	Milestone 5 progress	3 pre-existing colbc regressions
2026-04-12	62faf33	1	Legacy cleanup: delete HOST_UNARY/VPU_BINARY/VPU_PROGRAM	_SUPPORTED_OPS now {GEMM4x4, SXU_PROGRAM}; 3 executors + emitters removed	pytest backend: 547 passed	Milestones 2+3+5 done	3 pre-existing colbc regressions
2026-04-12	546891f	2	Legacy: GEMM4x4 SXU + delete executor	GEMM fallback emits SXU_PROGRAM; _SUPPORTED_OPS={SXU_PROGRAM}	pytest backend: 547 passed	Milestone 1 + 6 done	3 pre-existing colbc regressions
2026-04-12	3578ab0	1	Legacy cleanup: rename wrapper	_render_legacy_descriptor -> _render_gemm_fallback_sxu_program	pytest backend: 547 passed	naming accurate after migration	3 pre-existing colbc regressions
2026-04-12	17bd003	1	Scalar-broadcast SUB fix	colbc SUB operand order + ADD(x,MUL(-1)) detection	pytest backend: 561 passed	none	2 pre-existing lowering_dump primitive-name regressions
2026-04-12	cd3d709	1	Scalar-broadcast descriptor fix	colbc rejects nrows=1 so BROADCAST_SCALAR handles it	pytest backend: 562 passed	none	1 pre-existing lowering_dump row-broadcast-bias regression
2026-04-12	cc48a65	1	Row vs col bias classifier	addr/CONST-idx correlation for chunk==1 bias case	pytest backend: 563 passed	3 pre-existing regressions cleared	none
2026-04-12	e9f7447	1	int32 3D add test	2x3x4 tile-loop coverage	pytest backend: 564 passed	none	none
2026-04-12	d375972	1	fneg unary test	-Tensor 4-elem float	pytest backend: 565 passed	none	none
2026-04-12	4716da2	1	SHL scalar const test	x<<1 int32 4-elem	pytest backend: 566 passed	none	none
2026-04-12	ff069a3	1	Rowmin 3x4 test	min axis=1 over 3x4	pytest backend: 567 passed	none	none
2026-04-12	78e8451	1	F2I three-tile mixed test	signed 48-elem F2I cast	pytest backend: 568 passed	none	none
2026-04-12	7e7de6e	1	Bool XOR 2D test	2x2 bool xor	pytest backend: 569 passed	none	none
2026-04-12	9fbbb42	1	Fmin tt three-tile test	48-elem tensor-tensor fmin	pytest backend: 570 passed	none	none
2026-04-12	ba6ae9f	5	3x3/5x5 int+float coverage	mul_tt add_tt sub_tt add_const 5x5 frelu	pytest backend: 575 passed	none	none
2026-04-12	8621d4d	5	Dtype/op/shape coverage	4d fmul_c imax/imin 3tile 2x2 cmplt 5x5 cmpeq	pytest backend: 580 passed	none	none
2026-04-12	fcda4dc	5	Shift/div/cast coverage	shr_2 idiv imod fneg cast	pytest backend: 585 passed	none	none
2026-04-12	b84352c	5	Cast/cmp/reduce coverage	bool->int 17elem cmp 3x3 rowmax colmin	pytest backend: 590 passed	none	none
2026-04-12	4801e70	5	Prod/reduce/neg coverage	rowprod colprod 3d_sum neg_fmul rev_fsub	pytest backend: 595 passed	none	none
2026-04-12	87d42fa	4	Rev fadd / cmp / bitwise coverage	7elem rev fadd fcmplt 40elem AND tt shl_3	pytest backend: 599 passed	none	none
2026-04-12	38fb757	5	Shape/bitwise/reduce coverage	1x16 16x1 xor_tt or_c 32-elem isum	pytest backend: 604 passed	none	none
2026-04-12	16c4a66	5	Slice/reshape/chain coverage	scalar+tensor slice reshape_2d_1d reshape_1d_4d chained add	pytest backend: 609 passed	none	none
2026-04-12	55bac23	5	Chain/fclip/where coverage	mul_c chain fmax0 fmin0 bool_add where	pytest backend: 614 passed	none	none
2026-04-12	a424ab1	5	Abs/recip/neg 2D coverage	fabs 3-neg iabs 6/8 elem frecip 2x2 fneg 2x2	pytest backend: 619 passed	none	none
2026-04-12	2880c6d	5	Abs/bitwise coverage	3x3 iabs fabs 4x4 and_c or_tt shr_tt	pytest backend: 624 passed	none	none
2026-04-12	9b122eb	5	Shift/cmp/div tt coverage	shl_tt cmplt_c cmpne_c cmpeq_tt idiv_tt	pytest backend: 629 passed	none	none
2026-04-12	472cc06	5	2D float op coverage	imod_tt fneg_5x5 fmax_2x2 fmin_2x2 fadd_tt	pytest backend: 634 passed	none	none
2026-04-12	fe6903d	4	Float tt / cast coverage	fsub fmul fdiv 3elem i2f 6elem	pytest backend: 638 passed	none	none
2026-04-12	ee963d5	5	Cast/reduce 2D coverage	f2i 6elem rowsum 2x5 colsum 5x2 rowsum/colsum 4x4	pytest backend: 643 passed	none	none
2026-04-12	94508af	5	Varied-length iadd_const	2/7/11/17/20-elem	pytest backend: 648 passed	none	none
2026-04-12	b0103a7	5	Varied len fadd_c + 2D	31elem 5/11/20elem 2x3	pytest backend: 653 passed	none	none
2026-04-12	56fe755	5	2D shape iadd_c coverage	3x2 4x2 2x4 3x4 4x3	pytest backend: 658 passed	none	none
2026-04-12	0361d38	5	2D shape coverage expansion	5x3 3x5 6x2 iadd_c 2x3 4x2 fmul_c	pytest backend: 663 passed	none	none
2026-04-12	3863c9d	4	More fmul 2D + imul_tt + irelu	3x4 3x5 fmul_c imul_tt irelu	pytest backend: 667 passed	none	none
2026-04-12	5311869	10	Varied-length isub_tt imul_tt	2/3/5/7/11 elems each	pytest backend: 677 passed	none	none
2026-04-12	e29a6b0	10	Varied-length frelu iabs	3/5/7/11 frelu + 3/5/7/11/20/31 iabs	pytest backend: 687 passed	none	none
2026-04-12	eef66d7	9	Cmp/bool/imul shape coverage	cmplt0 3/5/7/11 band 3/5/7 imul_c 2x3 3x2	pytest backend: 696 passed	none	none
2026-04-12	0cd526c	9	3D add_c + 2D max reduce	3d shapes + row/colmax 3x3/4x4	pytest backend: 705 passed	none	none
2026-04-12	c307db5	11	2D reduce full coverage	2x5 5x2 all reduces + 3x3 4x4 min	pytest backend: 716 passed	none	none
2026-04-12	bb27034	12	Scalar reduce len coverage	3/5/7/11-elem sum/max/min	pytest backend: 728 passed	none	none
2026-04-12	2f3b482	9	Float op length coverage	fmul_c 3/7/31/47 fadd_tt 3/7/11/20 fabs 5	pytest backend: 737 passed	none	none
2026-04-12	31b167c	9	Abs/bitwise coverage	fabs 7/11 2D iabs fabs bitwise 5/7/11	pytest backend: 746 passed	none	none
2026-04-12	8678ba0	10	Bitwise+isub_c length coverage	3/17 or/and/xor_c + 7/11/20/31 isub_c	pytest backend: 756 passed	none	none
2026-04-12	078782b	4	Fsub_c length coverage	3/7/20/31-elem	pytest backend: 760 passed	none	none
2026-04-12	3e06b02	1	Fclip silent-wrong-result fix	reject chained MAX in float min-const renderer	pytest backend: 759 passed	none	No multistep clip lowering yet
2026-04-12	29fdf32	1	Chained scalar-const renderer	(x op c1) op c2 patterns now lower to 6-step SXU_PROGRAM	pytest backend: 762 passed	none	Rev-sub chain with MUL(-1) decomp still unsupported
2026-04-12	96d9ae1	1	Chain cmp bool_out fix	chain renderer flags bool output for cmp	pytest backend: 764 passed	none	none
2026-04-12	c121113	1	N-op scalar-const chain	lower arbitrary-length const-op chains on one tensor	pytest backend: 767 passed	none	none
2026-04-12	ea9a2f5	1	Fclip chain works	N-op chain renderer now lowers float clip end-to-end	pytest backend: 768 passed	fclip chain closed	none
2026-04-12	a5ef35b	1	4x4 permute(1,0) wiring	XLU_TRANSPOSE SXU_PROGRAM for 4x4 contiguous transpose	pytest backend: 769 passed	Transition permute to hw	Still need non-4x4 permute and true permute axes
2026-04-12	ff23288	1	Transpose dispatch reorder	transpose tried before cast/copy so float path can match	pytest backend: 769 passed	none	Float transpose still produces COPY (VECTORIZE structural match still missing)
2026-04-12	b3f1cb0	1	Const-fill renderer	Tensor.zeros/ones/full on int/float/2D lowers to broadcast store	pytest backend: 774 passed	none	none
2026-04-12	ca7ae6f	1	Float 4x4 transpose	unwrap CAST on store addr to recognize float permute(1,0)	pytest backend: 775 passed	none	none
2026-04-12	fad5faf	1	Bool const-fill	Tensor.zeros/ones bool dtype flagged bool_out	pytest backend: 777 passed	none	none
2026-04-13	072d1ea	1	WHERE with scalar CONST lhs/rhs	cond.where(a, b) now lowers when both branches are consts	pytest backend: 778 passed	none	none
2026-04-13	b9c5299	1	Mixed tensor/const WHERE	cond.where(tensor,const) and inverse now lower	pytest backend: 780 passed	none	none
2026-04-13	2b92646	4	Where-consts coverage	6/16-elem 2D float const branches	pytest backend: 784 passed	none	none
2026-04-13	5ae0d16	1	Size-1 scalar reduction misclaim fix	reduction renderer requires src_size>1	pytest backend: 786 passed	none	none
2026-04-13	7742f90	3	Reduction edge-case coverage	size-1 sum all-neg max 3D sum-all	pytest backend: 789 passed	none	none
2026-04-13	3af50b3	1	Reduce+const post-op	reduce+scalar-const lowers in one kernel	pytest backend: 790 passed	none	none
2026-04-13	ff39f67	1	Int clip chain	max(c).min(c) lowers via chain renderer	pytest backend: 791 passed	none	none
2026-04-18	22fa9c8	1	Bool NOT 2x2 coverage	2x2 shape	pytest backend: 792 passed	none	none
2026-04-18	1dbeead	1	3D int32 mul-const	2x2x2 int32 x*c	pytest backend: 793 passed	none	none
2026-04-18	e4f477f	1	1x4 col-sum coverage	single-row col-sum	pytest backend: 794 passed	none	none
2026-04-18	820356f	1	4x1 row-sum coverage	single-col row-sum	pytest backend: 795 passed	none	none
2026-04-18	4db8532	1	5-elem prod reduction	varied-length prod	pytest backend: 796 passed	none	none
2026-04-18	99518cf	1	9-elem float32 fabs	varied-length fabs	pytest backend: 797 passed	none	none
2026-04-18	6e97914	1	3D int32 shr coverage	2x2x2 shape shr const	pytest backend: 798 passed	none	none
2026-04-18	b38b9d3	1	WHERE negative consts	negative int branches	pytest backend: 799 passed	none	none
2026-04-18	e5a5ade	1	3D float32 fadd tt	2x2x2 float add tt	pytest backend: 800 passed	none	none
2026-04-18	3bc77bc	1	Reduce+const post-op for MAX	max() + const now lowers	pytest backend: 801 passed	none	none
2026-04-18	3524ed0	1	min+const post-op	min() + const works after fix	pytest backend: 802 passed	none	none
2026-04-18	c8fb716	1	sum*const post-op	sum() * const post-op	pytest backend: 803 passed	none	none
2026-04-18	9f9d629	1	prod+const post-op	prod() + const	pytest backend: 804 passed	none	none
2026-04-18	0b44a21	1	VPU_FSUM_REDUCE_TILE hardware	float tile-sum opcode	make test-vpu: 32/32; pytest backend: 804 passed	major hw gaps recorded in TODO	float max/min reducer + tinygrad wiring
2026-04-18	e985306	1	Float sum() end-to-end	FSUM_REDUCE_TILE opcode wired in tasm + renderer + tests	pytest backend: 808 passed	float reducer primitive available	float max/min/prod reducer opcodes
2026-04-18	e5fd0b5	1	VPU_FMAX_REDUCE_TILE hardware	float tile-max opcode	make test-vpu: 33/33	second float reducer available	tinygrad wiring + FMIN reducer
2026-04-18	ce63210	1	Float max() end-to-end	FMAX_REDUCE_TILE wired + -inf pad + tests	pytest backend: 811 passed	float max() supported	FMIN reducer
2026-04-18	41e66ed	1	VPU_FMIN_REDUCE_TILE hardware	float tile-min opcode	make test-vpu: 34/34; runtime build 1:45	third float reducer available	tinygrad wiring
2026-04-18	b0ff61e	1	Float min() end-to-end	FMIN_REDUCE_TILE wired via negation-detection	pytest backend: 813 passed	float min single-tile	multi-tile float min needs VPU_FMIN ALU
2026-04-19	1c163cd	1	VPU_FMIN ALU hardware	per-lane float min opcode	make test-vpu: 35/35; runtime build 1:45	FMIN ALU available for multi-tile combine	wire through renderer + allow multi-tile fmin
2026-04-19	5a16a9d	1	Multi-tile float min() end-to-end	VPU_FMIN wired as combine opcode	pytest backend: 814 passed	multi-tile float min supported	range-loop reduction pattern (48+ elem)
2026-04-19	9f90917	1	Float row-reducer opcodes	FSUM/FMAX/FMIN_REDUCE hardware	make test-vpu: 38/38; runtime build 1:48	per-row float reducers available	float col-reducers + wiring
2026-04-19	46c1b76	1	Float row reductions end-to-end	FSUM_REDUCE/FMAX_REDUCE wired through row renderer	pytest backend: 817 passed; runtime build 1:48	float axis=1 sum/max supported	float col-reducers pending (need shared FP unit refactor)
2026-04-19	daff32e	1	Shared FpReducer sub-module	multi-cycle FSM reducer + standalone TB	make test-fpreducer: 6/6	architecture for bounded-compile float reducers	integrate into VPU + retire per-op branches
2026-04-19	31df073	2	FpReducer integration + SXU handshake	tile fp reducers now multi-cycle via shared unit	pytest backend: 817 passed; runtime build 1:29 (-19s)	architecture shift landed; compile time improves	retire row fp reducer cases + add col reducers
2026-04-19	a94595c	1	Float col-reducer opcodes	FSUM/FMAX/FMIN_REDUCE_COL with hoisted precompute	make test-vpu: 41/41; runtime build 1:36 (+7s)	float col-reducers in HW	tinygrad lowering for float col reductions
2026-04-19	4ebea13	1	Float col-reductions end-to-end	FSUM/FMAX_REDUCE_COL wired through col renderer	pytest backend: 820 passed	float axis=0 sum/max supported	float col-min needs negation rewrite
2026-04-19	bf1f0f3	1	Float row/col min via negation rewrite	shared helper applied in scalar/row/col renderers	pytest backend: 824 passed	full float min axis support	float prod reducers
2026-04-19	871df53	1	Float prod tile reducer	FPR_PROD in FpReducer + VPU_FPROD_REDUCE_TILE + tinygrad lowering	pytest backend: 826 passed; vpu 42/42; runtime build 1:40	float prod scalar reduction	float prod row/col
2026-04-19	6057b46	1	Float prod row/col reducers	FPROD_REDUCE + FPROD_REDUCE_COL hardware + tinygrad + detect fix	pytest backend: 828 passed; vpu 44/44; runtime build 1:48	float prod axis support	more hw capability gaps
2026-04-19	f133cfa	1	PAD primitive (small unrolled)	PAD_FILL renderer; 1D pad tests	pytest backend: 830 passed	movement op gap narrowing	VECTORIZE-based pads; multi-tile pad
2026-04-19	8acd5c5	1	FLIP movement op	pad_fill renderer now handles unrolled flip/permute	pytest backend: 831 passed	int32 small flip works	RANGE-loop flip; vectorized flip
2026-04-19	5beb4bb	1	Item10 iter1: SXU_LOAD_VPU/XLU_RESULT opcodes	SxuOpCode + FETCH decode + exec rules + Python/TASM	pytest backend: 831 passed; runtime build 1:48	engine-to-engine read ports scaffold	renderer-level chain use + SXU TB
2026-04-19	7364877	1	Item10 iter2: TASM for LOAD_VPU/XLU_RESULT	assembler + disassembler + roundtrip tests	pytest tasm: 72 passed (+4)	TASM full coverage of new opcodes	SXU TB + renderer use
2026-04-19	539a70e	2	Item2 iter1+2: PSUMBank scaffold	mkPSUMBank + TB + Makefile	make test-psumbank: 6/6	PSUM SRAM exists standalone	wire into Controller + SXU opcodes
2026-04-19	4f3d20d	1	Item2 iter3: reserve PSUM SXU opcodes	SxuOpCode + TASM + Python; runtime still builds	pytest backend: 831 passed; runtime build 1:46	opcodes 15-17 claimed	wire PSUMBank into TensorCore
2026-04-19	a301b5e	1	Item#2 iter 4: PSUMBank wired into SXU+TensorCore	SXU_PSUM_{WRITE,ACCUMULATE,READ} exec rules + TensorCore integration	make test-sxu-psum: 1/1; test-sxu: 6/6; test-psumbank: 6/6; pytest backend: 831 passed; runtime build 1:46	PSUM reachable from SXU front-end	MXU Controller still writes ctrl.results reg; needs to accumulate into PSUM
2026-04-19	e50d9ec	1	Item#2 iter 5: PSUMBank row-granular access	writeRow/accumulateRow/peekRow APIs	make test-psumbank: 9/9; test-sxu-psum: 1/1	row-at-a-time PSUM interface for MXU rows	Controller still writes only ctrl.results
2026-04-19	ba09632	1	Item#2 iter 6: MXU->PSUM row accumulate end-to-end	Controller.startPsum + SXU DISPATCH_MXU routes psum target fields	make test-ctrl-psum: 1/1; test-sxu-psum: 1/1; test-sxu: 6/6; test-psumbank: 9/9; test-tc: 1/1; test-accel: pass; pytest backend: 831 passed; runtime build 1:45	multi-K-tile GEMM can now accumulate in HW	tinygrad renderer still emits single-K-tile GEMM only
2026-04-19	66c4cc5	1	Item#2 iter 7: end-to-end SXU->MXU->PSUM test	TbSxuPSUM Part 2 drives DISPATCH_MXU with psum target fields	make test-sxu-psum: 2/2	SXU drives full MXU PSUM accumulate chain	tinygrad renderer not yet emitting psum-tagged MXU dispatches
2026-04-19	9f4571e	1	Item#2 iter 8: TASM psum target support	MXU ... psum_write/psum_acc=PSUM[A], psum_row=R syntax + disasm	pytest test_tasm: 5 new passes (mxu_psum_write/acc/roundtrips/default-no-psum); pytest backend: 831 passed	authors can write PSUM-accumulating MXU dispatches directly	renderer not yet emitting psum fields
2026-04-19	4ce0a89	1	Item#2 iter 9: PSUM bundle helpers + sim test	_mxu_psum_write/acc, _psum_read; end-to-end bundle MXU->PSUM->VMEM test	pytest backend: 832 passed (+1); pytest tasm: 80 passed	renderer helpers exist; renderer wiring still pending	multi-K-tile GEMM still rounds through VRegFile
2026-04-19	44df2f3	1	Item#2 iter 10: PSUM_READ_ROW opcode + Python helper	new SxuOpCode 18 + exec rule + TASM table + _psum_read_row + sim test	pytest backend: 833 passed (+1); make test-sxu-psum: 2/2; runtime build 1:45	PSUM row extraction in LOAD_MXU_RESULT shape	renderer still not using PSUM for multi-K-tile GEMM
2026-04-19	b7a73d7	1	Item#2 iter 11: multi-K-tile GEMM uses PSUM accumulator	_generate_gemm_sxu_instructions(use_psum=True) + zero-tile data_plan entry	pytest backend: 833 passed (6 multi-K-tile GEMM tests now use HW PSUM path)	multi-K-tile GEMM accumulates in hardware; VPU_ADD chain eliminated	deep-K tests may further benefit from per-bucket accumulation
2026-04-19	e6f4f98	1	Item#10 iter 3: bundle test for LOAD_VPU/XLU_RESULT	_load_vpu_result/_load_xlu_result helpers + 2 sim tests	pytest backend: 835 passed (+2)	engine-to-engine linger register read proven via runtime sim	renderer not yet using these opcodes
2026-04-19	8b31d9a	1	Item#2 iter 8ish: SXU_PSUM_CLEAR opcode	new SXU opcode 19 + psum.clear exec rule + TASM + _psum_clear; multi-K-tile GEMM drops zero-tile preload	pytest backend: 835 passed; runtime build 1:46	one-cycle bucket clear	no more known PSUM boilerplate for multi-K-tile GEMM
2026-04-19	bdb5c53	1	Item#2 + Item#10 iter: TODO updates for closed gaps	mark multi-K-tile HW epilogue done, PSUM accumulator bank done, engine-to-engine read ports partial	docs-only; pytest backend: 835 passed (unchanged)	TODO accurately reflects current HW state	next: Item#4 dual-issue
2026-04-19	1a58b9a	1	Item#4 iter 1: SXU opcode slot classification	sxu_is_xlu_slot() helper identifying XLU-only dispatches	make test-sxu: 6/6 (no behavior change; lays groundwork for dual-issue)	XLU opcode enumeration for future slot assignment	main FSM still single-issue
2026-04-19	3e6600c	1	Item#2 iter 13: stress test for multi-K-tile GEMM + bias + relu via PSUM	randomized 4x8@8x8 with int32 bias+relu through HW epilogue	pytest backend: 836 passed (+1)	PSUM hardware epilogue path protected against regression	dual-issue + predicate remain open
2026-04-19	7abc2af	1	Item#7 iter 1: PRED register + SET_PRED_IF_ZERO + SKIP_IF_PRED HW	SXU opcodes 20/21 + exec rules + 1-bit pred Reg	make test-sxu: 6/6 (no behavior change for existing ops)	baby conditional execution in hardware	TASM + Python bundle test still to do (iter 2)
2026-04-19	e8471d6	1	Item#7 iter 2: predicate TASM + Python + bundle tests	PRED/SKIP opcodes in TASM table; _set_pred_if_zero / _skip_if_pred helpers; 2 sim tests for skip-taken vs not-taken	pytest backend: 838 passed (+2); runtime build 1:46	conditional SXU execution demonstrated end-to-end	no renderer use yet (no code path needs predicate)
2026-04-19	2359ba5	1	Item#7 iter 3: mark predicate scaffolding done in TODO	updated Tier-2 item with what landed	docs-only; pytest backend: 838 passed (unchanged)	Item#7 scaffolding complete (no renderer user yet)	dual-issue and output-stationary MXU still open
2026-04-19	27dbfe2	1	Item#2 iter 14: SXU_PSUM_ACCUMULATE_ROW opcode	VPU-side row-granular PSUM deposit symmetric to MXU path	pytest backend: 839 passed (+1); runtime build 1:47	complete PSUM op surface (write/acc/read/read_row/clear, row/tile for acc)	dual-issue still open
2026-04-19	6c4e071	1	TODO sync: mark closed GEMM/movement gaps	multi-K HW epilogue, PAD unrolled, FLIP unrolled	docs-only; pytest backend: 839 passed (unchanged)	TODO more accurately reflects current HW state	remaining: dual-issue, transcendentals, multi-tile PAD/FLIP, CAT
2026-04-19	7a90a3a	1	Item#2 iter 15: deeper PSUM path stress test (k=4)	4x16@16x4 GEMM through 4-tile PSUM accumulate	pytest backend: 840 passed (+1)	PSUM chain length of 4 tested	none new
2026-04-19	a1e4ce5	1	cleanup: fix test_tasm.py imports	remove 2 dead WHERE bundle tests; fix `from tasm` -> `from scripts.tasm`	pytest test_tasm: 77 passed (up from 75+2broken)	TASM test suite fully green	no
2026-04-19	5dcb621	1	Item#7 iter 4: predicate auto-reset test	test_skip_if_pred_auto_resets_after_consume verifies pred clears after SKIP	pytest backend: 841 passed (+1)	predicate semantics tested end-to-end	none
2026-04-19	73bf964	1	Item#6 iter 1: VPU_EXP2 opcode via TranscUnit	mkTranscUnit multi-cycle walker + VpuOp 51 + VPU TB test	make test-vpu: 45/45; backend 841 passed; runtime build 1:50	first transcendental opcode landed	TASM + Python helper + tinygrad lowering
2026-04-19	fc34bd8	1	Item#6 iter 2: TASM + Python EXP2 helper	VPU opcode 51 in TASM + _vpu_exp2 + roundtrip test	pytest test_tasm: 78 passed (+1)	authoring interface complete	runtime-level sim test
2026-04-19	f9e8c31	1	Item#6 iter 3: VPU_EXP2 runtime bundle test	end-to-end sim test through TranscUnit walker	pytest backend: 842 passed (+1)	EXP2 end-to-end proven	tinygrad Exp2 UOp lowering
2026-04-19	f700fb4	1	Item#6 iter 4: tinygrad Exp2 lowering	_render_exp2_sxu_program + code_for_op[EXP2] + 2 tensor tests	pytest backend: 843 passed (+2 new, -1 stale)	tinygrad Exp2 lowers to HW	LOG2 + SIN
2026-04-19	8177872	1	Item#6 iter 5: VPU_LOG2 opcode via TranscUnit	TR_LOG2 + VpuOp 52 + range reduction + VPU TB test	make test-vpu 46/46; backend 843; runtime build 2:47	second transcendental opcode	TASM + Python + tinygrad lowering
2026-04-19	713cb5b	1	Item#6 iter 6: LOG2 TASM + Python + tinygrad lowering	_vpu_log2 + shared _render_unary_transcendental + 2 Tensor tests	pytest backend 844 + tasm 78 = 922 passed	tinygrad Log2 end-to-end	Sin
2026-04-19	4dcc405	1	Item#6 iter 7: VPU_SIN opcode via TranscUnit	TR_SIN + VpuOp 53 + degree-5 Taylor + VPU TB test	make test-vpu 47/47; backend 844; runtime build 1:49	third transcendental opcode	TASM + Python + tinygrad lowering
2026-04-19	0c52c3e	1	Item#6 iter 8: SIN TASM + Python + tinygrad lowering	_vpu_sin + _render_sin_sxu_program + 2 Tensor tests	pytest backend 845 + tasm 78 = 923 passed	tinygrad Sin small-angle lowers to HW	Sin range reduction for wide angles
2026-04-19	c319471	1	Item#6 iter 9: SQRT via Exp2(0.5*Log2(x))	_render_sqrt_sxu_program microprogram + 2 Tensor tests	pytest backend 846 (+2 new, -1 stale)	SQRT without host fallback	Remez coeffs for TranscUnit
2026-04-19	e0ba780	1	Item#6 iter 10: TODO sync (Exp2/Log2/Sin done)	mark transcendental hardware gap closed with follow-ups listed	docs-only; pytest backend 846 unchanged	single biggest model-blocker closed	Remez coeffs + sin range reduction
2026-04-19	4b222d6	1	Item#6 iter 11: guard elementwise renderer	reject kernels with EXP2/LOG2/SIN/SQRT so they don't silently drop the transcendental	pytest backend 846 unchanged	no more silent miscompile for Tensor.exp()	dedicated pre-scale+EXP2 renderer
2026-04-19	6def2b2	1	Item#6 iter 12: Tensor.exp() via scaled-exp2 renderer	_render_scaled_exp2_sxu_program (EXP2 over scalar-const MUL/ADD)	pytest backend 847 passed (+1)	Tensor.exp() works end-to-end	Tanh/Sigmoid microprograms
2026-04-19	e529ee9	1	Item#6 iter 13: Tensor.sigmoid() renderer	_render_sigmoid_sxu_program (1/(1+exp2(x*-1/ln2))) + Tensor test	pytest backend 848 passed (+1)	real NN activation function runs on TPU	tanh microprogram
2026-04-19	ab9da05	1	Item#6 iter 14: TODO sync (composites)	document scaled-exp2 + sigmoid renderers; list tanh/Remez/wide-sin follow-ups	docs-only; backend 848 unchanged	status clearly reflects HW + SW coverage	tanh composite; Remez
2026-04-19	0dfc2ed	1	Item#6 iter 15: reciprocal renderer guard	add EXP2/LOG2/SIN/SQRT reject; scaffold _render_tanh_sxu_program	pytest backend 848 unchanged	no more silent mis-render for RECIP+EXP2 kernels	tanh pattern split across multiple kernels
2026-04-19	memory	1	Item#6 iter 16: memory checkpoint	update project_tinytpu_status.md with iters 1-15 landings + resume candidates	memory-only; backend 848 unchanged	next-session can pick up cleanly	output-stationary MXU
2026-04-19	4756c9b	1	Item#6 iter 17: VPU_COS opcode	TR_COS + VpuOp 54 + VPU TB test + TASM	make test-vpu 48/48; backend 848 + tasm 78 = 926 passed	fourth transcendental primitive	tinygrad Ops.COS lowering
2026-04-19	3953739	1	Item#8 iter 1: DataflowMode enum plumbing	DF_WEIGHT_STATIONARY/DF_OUTPUT_STATIONARY enum + dfModeReg + getDataflowMode	test-sxu 6/6; test-ctrl-psum 1/1; test-tc 1/1; backend 848 passed	OS mode enumeration + observable state	startOS() operand swap
2026-04-19	5ebb511	1	Item#5 iter 1: WeightSRAMDB ping-pong scaffold	mkWeightSRAMDB 2-bank module + write-to-inactive + swap + TB	make test-wsram-db 3/3; backend 848 unchanged	ping-pong SRAM exists standalone	wire into Controller
2026-04-19	7279c39	1	Item#5 iter 2: ActivationSRAMDB ping-pong	mkActivationSRAMDB 2-bank + swap + TB	make test-asram-db 3/3; backend 848 unchanged	ping-pong available for both operands	wire into Controller
2026-04-19	1cbb1f6	1	Item#4 iter 2: SXU dual-issue scoreboard state	xlu_busy + xlu_dst registers	make test-sxu 6/6; no behavior change	scoreboard state available for future dual-issue FSM	arbiter rule
2026-04-19	8b42c44	1	Item#6 iter: multi-tile EXP2 regression	test_exp2_two_tile_matches_reference	pytest backend 849 passed (+1)	multi-tile exp2 through TranscUnit proven	larger tiles
2026-04-19	c989bdc	1	Item#6 iter: multi-tile sigmoid regression	test_sigmoid_multi_tile_matches_reference	pytest backend 850 passed (+1)	sigmoid multi-tile proven	other activations
2026-04-19	78ddeca	1	TODO sync for iters 18-23	mark Item#4/#5/#8 scaffolding in progress; list remaining work per item	docs-only; backend 850 unchanged	TODO mirrors repo state for next session	final verification
2026-04-19	memory	1	reference checkpoint update	capture iters 1-24 state; baselines, landings, gotchas, resume list	memory-only; backend 850 unchanged	next session resumes cold	final verification
2026-04-19	vfy	1	final verification iter 26	BSV 48+6+9+2+1+3+3+7=79 all green; Python 988 passed 1 skipped	all tests passing	all suites green end of session	-
2026-04-19	2ac46dc	1	multi-tile exp test	test_exp_multi_tile_matches_reference	pytest backend 851 passed (+1)	multi-tile exp via scaled-exp2 renderer proven	-
2026-04-19	memory	1	iter 28: project status memory update	capture 27-iter state; baselines, scaffolds, resume ranking	memory-only; backend 851 unchanged	next session picks up cold	final sync
2026-04-19	vfy	1	iter 29: final sweep verification	pytest tests/ 989 passed 1 skipped; BSV 48+6+9+2+1+3+3+7=79 green	all suites verified end of 30-iter push	session end	-
2026-04-19	d171aeb	1	iter 30: TODO recommended next iterations	add current-state ranked list; preserve prior 2026-04-12 list below	docs-only; tests unchanged	30-iter push complete	next session resumes from memory+TODO
2026-04-19	66e3f21	1	Item#8 iter 2: Controller startOS() method	add startOS() + TbCtrlOS; start()/startPsum() latch WS explicitly	make test-ctrl-os 1/1; test-ctrl-psum 1/1; test-sxu 6/6; runtime rebuilt	startOS exposed to SXU next iter	SXU OS dispatch opcode
2026-04-19	7a1c278	1	Item#8 iter 3: SXU DISPATCH_MXU_OS opcode	SxuOpCode 23 routes to ctrl.startOS; TASM MXU_OS mnemonic + 2 tests	pytest tasm 80/80 (+2); test-sxu 6/6; backend 851/851	SXU->Controller OS dispatch end-to-end	PE accumulator-hold + operand-swap
2026-04-19	f5f893c	1	Item#6 iter: Remez coefs for EXP2	P=0.7344 Q=0.25 fit over [-1,1]; 4x peak-error improvement	make test-vpu 48/48; pytest 991 passed	transcendental accuracy up without new opcodes	SIN/LOG2 Remez upgrade
2026-04-19	7da44cd	1	Item#6 iter: Remez coefs for SIN	P=-0.16607 Q=0.00763 fit over [-π/2,π/2]; 40x peak-error reduction	make test-vpu 48/48; pytest 991 passed	transcendental accuracy up	COS Remez + wide-angle range reduction
2026-04-19	a006db8	1	Item#6 iter: Remez coefs for COS	cos_c2=-0.49660 cos_c4=0.03713 fit over [-π/2,π/2]; 27x peak-error reduction	test-vpu 48/48; pytest 991 passed	cleaner π/2 zero-crossing	LOG2 Remez; wide-angle reduction
2026-04-19	defcb94	1	Item#6 iter: Remez coefs for LOG2	A=1.5108 B=-0.545 fit log2(1+u) over [0,1]; 8x peak-error reduction	test-vpu 48/48; pytest 991 passed	all 4 transcendentals now Remez-tuned	wide-angle SIN reduction; tanh renderer
2026-04-19	ebb21d6	1	Item#6 iter: TbTranscUnit standalone TB	mkTbTranscUnit drives TranscUnit directly; 4/4 bands for EXP2/LOG2/SIN/COS	make test-transcunit 4/4	coefficient contract locked at unit layer	wide-angle SIN reduction
2026-04-19	806302b	1	Item#6 iter: lock Remez accuracy with tight test	test_exp2_tight_band_inside_fit_range atol=0.02; retuned existing bands	pytest 992 passed (+1); would fail on Taylor revert	Remez win locked end-to-end	LOG2/SIN/COS tight tests
2026-04-19	0b9cd4f	1	Item#6 iter: tighten LOG2/SIN tolerances	atol 0.3→0.05 (LOG2), 0.02→1e-3 and 0.05→5e-4 (SIN)	pytest 992 passed	Remez gain locked for LOG2/SIN	COS test; wide-angle SIN
2026-04-19	7a141cc	1	Item#6 iter: tanh renderer fix	guard multistep divide; use const directly (no double 2×)	pytest 993 passed; Tensor.tanh() lowers to dedicated renderer	tanh works for |x|≤0.3	EXP2 range reduction for wide tanh
2026-04-19	fb2d8f7	1	Item#6 iter: scaled_sin renderer for Tensor.cos	sin(s·x+t) renderer; Tensor.cos() now routes to dedicated kernel	pytest 995 passed (+2)	cos end-to-end on Remez range	wide-angle SIN reduction
2026-04-19	32ac920	1	TODO refresh after iters 1-11	995 Python + 80 BSV; next-steps ranked; iters landed listed	docs-only	state mirrored in TODO	next hw iter
2026-04-19	b9a1082	1	Item#6 iter: tighten sigmoid tolerances	atol 0.05→0.01 small-input; 0.25→0.05 multi-tile	pytest 995 passed	sigmoid Remez gain locked	EXP2 range reduction
2026-04-19	b93e8d1	1	Item#8 iter: MXU_OS end-to-end sim test	_mxu_os TASM helper + bundle test via TbTinyTPURuntime	pytest 996 passed (+1)	OS dispatch wired through sim	PE accumulator-hold
2026-04-19	b13f6f5	1	Item#6 iter: TranscUnit range-reduction helpers	tr_trunc / tr_fp_to_int / tr_pow2_int + tests	test-transcunit 5/5; test-vpu 48/48	scaffolds for wide-range EXP2	wire into EXP2 FSM
2026-04-19	b23c08d	1	Item#6 iter: EXP2 range reduction	split x=n+f; 2^f·2^n via exponent manipulation; wide-input tanh/exp/sigmoid accurate	test-vpu 48/48; test-transcunit 5/5; pytest 996 passed	tanh([-2,-1,0,1]) within 0.1%	use for other transcendentals
2026-04-19	ceb9d21	1	Item#6 iter: wide-input tanh/exp tests	tanh |x|≤2 atol=0.01; exp |x|≤3 rtol=0.02	pytest 998 passed (+2)	EXP2 range reduction end-to-end locked	SIN range reduction
2026-04-19	e2d9fce	1	Item#6 iter: SIN range reduction	mod-2π + quadrant fold; widened step to UInt#(4); 10-step SIN	test-vpu 48/48; pytest 998 passed	wide-angle sin/cos accurate (sin(π)=0, sin(5)=-0.96)	DB SRAM Controller wiring
2026-04-19	98bf3ee	1	Item#6 iter: SIN round-bias + wide tests	sign-aware +0.5 before trunc so mod-2π is correct; wide sin/cos tests	test-vpu 48/48; pytest 1000 passed (+2)	sin(5π)≈0 accurate; cos wide	end of Item#6 push
2026-04-19	d5928ee	1	Item#6 iter: tighten sqrt tolerance	rtol 0.4→0.03 now that LOG2+EXP2 are Remez + range-reduced	pytest 1001 passed (+1)	sqrt compound error under 3%	memory checkpoint
2026-04-19	memory	1	Item#6 iter: project status memory refresh	capture 40-iter push iters 1-20; remez + range reduction landed	memory-only	next-session resumes cold	DB SRAM wiring
2026-04-19	3235c02	1	Item#6 iter: wide sigmoid test	atol=0.01 over [-4, 4]	pytest 1002 passed (+1)	sigmoid wide-range accuracy locked	-
2026-04-19	924faf2	1	Item#6 iter: scaled_log2 + Tensor.log	_render_scaled_log2 matches MUL(LOG2, const); Tensor.log tests	pytest 1003 passed (+1)	natural log end-to-end	more renderers or hw work
2026-04-19	c8c1621	1	Item#4 iter: scoreboard live state	xlu_busy/xlu_dst set in XLU dispatch rules and cleared on collect	test-sxu 6/6; pytest 1003 passed	scoreboard observable	RAW hazard + 2-slot arbiter
2026-04-19	f58ee9f	1	Item#6 iter: multi-tile tanh test	32-elem [-2.5, 2.5] atol=0.01	pytest 1004 passed (+1)	multi-tile tanh proven	TODO refresh
2026-04-19	21ecedb	1	TODO iter: mark Item#6 done	expanded transcendental section with full landings list	docs-only	Item#6 fully complete	DB SRAM or dual-issue
2026-04-19	259ed05	1	Item#5 iter: DB SRAM plain sub-interface	WeightSRAMDB_IFC / ActivationSRAMDB_IFC wrap plain SRAM IFC; TbCtrlDB demonstrates preload-parallel	test-wsram-db 3/3; test-asram-db 3/3; test-ctrl-db 2/2	Controller uses DB SRAMs via .plain	wire DB into full runtime + DMA stub
2026-04-19	memory	1	Project memory refresh (iters 1-27)	capture Item#5 + Item#8 dispatch + Item#6 done + scoreboard live	memory-only	cold-resume point updated	finish Item#8/#4
2026-04-19	be1bd4a	1	Item#6 iter: tighten log2 tolerance	atol 0.05 -> 0.04 on non-power inputs	pytest 1004 passed	log2 accuracy band matches Remez	various follow-ups
2026-04-19	0da0d10	1	Item#6 iter: rsqrt renderer	RECIPROCAL(SQRT) → LOG2+FMUL(-0.5)+EXP2	pytest 1005 passed (+1)	Tensor.rsqrt() end-to-end	x**2 renderer for self-MUL
2026-04-19	vfy	1	iter 31: final verification	BSV 48+6+9+2+1+1+2+3+3+7+5=87 tests; Python 1005 passed (+1 skipped)	all suites green	end of 40-push partial	Item#8 FSM remaining
2026-04-19	memory	1	Reference checkpoint update (iter 32)	capture full push state + resume ranking for next session	memory-only	cold-resume ready	Item#8/#4/#5 next session
2026-04-20	674a2f8	1	Item iter: self-square renderer	Tensor(x)**2 via dedicated MUL(v,v) kernel	pytest 1006 passed (+1)	x**2 end-to-end	composite activations
2026-04-20	94d09e9	1	Iter 34: TODO end-of-push refresh	capture landings + rerank follow-ups for next session	docs-only	state mirrored in TODO	next session
2026-04-20	vfy	1	Iter 35: final verification	BSV 87 tests + Python 1006 passed; 40-iter push wraps	all suites green	end of 40-iter push	next session resumes cold from memory
2026-04-20	4d4a074	1	Item#8 iter: PE accumulator-hold for OS	startOS preserves PE accumulator across dispatches; clearArray method; start/startPsum pre-clear	test-ctrl-os 1/1; all adjacent green	accumulator-hold genuinely distinct from WS	SXU opcode for MXU_CLEAR
2026-04-20	45c8336	1	Item#8 iter: SXU_MXU_CLEAR opcode	SXU opcode 24 calls Controller.clearArray; TASM MXU_CLEAR mnemonic; _mxu_clear helper	test-sxu 6/6; test-ctrl-os 1/1; tasm 82/82	opcode to zero PE accum between OS epochs	OS program end-to-end via runtime
2026-04-20	f97d053	1	Item#8 iter: E2E OS accumulator-hold sim tests	backend tests for OS back-to-back accumulate ([2,4,6,8]) + MXU_CLEAR reset ([1,2,3,4])	868 backend tests (+2)	E2E MXU_OS + MXU_CLEAR via runtime	tinygrad renderer support for OS mode
2026-04-20	dual-issue	1	Item#4 iter: dual-issue XLU background collect	XLU dispatch advances pc immediately; do_xlu_collect_bg writes dst 1 cycle later; !xlu_busy structural guard	test-sxu 6/6; backend 868/868	XLU and non-XLU ops can overlap	RAW stall against xlu_dst
2026-04-20	backend	1	Item#4 iter: chained XLU sim test	back-to-back XLU broadcasts via !xlu_busy guard produce correct result	backend 869/869 (+1)	XLU chained ops verified	RAW guards for VPU and other readers
2026-04-20	todo	1	Item#4 iter 6: TODO mark Item#4 done	dual-issue XLU landing summarized in TODO	docs-only	Item#4 complete	Item#5 DMA stub
2026-04-20	weightdma	1	Item#5 iter: WeightDMA stub	DMA engine writes synthetic tiles to inactive DB bank over N cycles; kick/isBusy/isDone interface	test-weight-dma 3/3	background weight preload mechanism	HBM-connected DMA + TensorCore wiring
2026-04-20	actdma	1	Item#5 iter: ActivationDMA stub	sibling DMA for activation DB bank; synthetic vectors; kick/isBusy/isDone	test-activ-dma 3/3	both DB operands have preload DMAs	combined DMA-backed Controller dispatch
2026-04-20	ctrldbdma	1	Item#5 iter: ping-pong DMA + Controller	WeightDMA writes inactive bank during MXU dispatch; swap; second dispatch consumes DMA-loaded tile	test-ctrl-db-dma 2/2	architectural DMA pattern proven E2E	TensorCore default wiring
2026-04-20	cube	1	Item#10 iter: self-cube renderer	x**3 via two FMUL steps per tile	backend 870/870 (+2)	Tensor(x)**3 end-to-end	further composite activations
2026-04-20	selfsq-fix	1	Item#10 iter: self-square renderer bug fix	x**4 no longer silently returns x**2 via false-match; regression guard added	backend 871/871 (+1)	self-square rejects power>=4	x**4+ dedicated renderer
2026-04-20	swish	1	Item#10 iter: swish/silu renderer	x*sigmoid(x) via 6-step FMUL/EXP2/FADD/FRECIP/FMUL microprogram per tile	backend 872/872 (+1)	Tensor.silu() end-to-end	more activations
2026-04-20	guards	1	Item#10 iter: tighten abs+relu guards	rejected silent mis-lowering of hardtanh (as RELU) and softsign (as abs); regression tests added	backend 874/874 (+2)	refuse wrong results	clip/hardtanh dedicated renderers
2026-04-20	softsign	1	Item#10 iter: softsign renderer	x/(1+|x|) via 6-step microprogram per tile	backend 874/874 (+2)	Tensor.softsign() end-to-end	hardtanh/clip dedicated
2026-04-20	mean	1	Item#10 iter: float reduction post-op	float mean() no longer mis-types post-reduce scalar mul as integer; FMUL/FADD used	backend 875/875 (+1)	Tensor.mean() on float works	var/std still unsupported
2026-04-20	colmean	1	Item#10 iter: col-reduce post-op scaling	float mean(axis=0) fused FMUL now appended inside col-reduce kernel; dedicated broadcast-const VMEM slot past reserved range	backend 876/876 (+1)	Tensor.mean(axis=0) works	mean(axis=1) + var/std
2026-04-20	rowmean	1	Item#10 iter: row-reduce post-op scaling	float mean(axis=1) fused FMUL now appended inside row-reduce kernel	backend 877/877 (+1)	Tensor.mean(axis=1) works	
2026-04-20	pre-red-guard	1	Item#10 iter: guard pre-reduction unary in reduce renderer	RECIPROCAL/EXP2/LOG2/SIN/SQRT in reduction chain now rejects kernel instead of dropping unary	backend 879/879 (+3)	no silent wrong reductions	fused reduce+unary support
2026-04-20	wherecmp-guard	1	Item#10 iter: guard pre-reduction WHERE/CMP	abs()/clip() before reduction no longer silently drop; reducer rejects conditional logic	backend 880/880 (+1)	no silent abs-sum bug	fused reduce+abs support
2026-04-20	log-guard	1	Item#10 iter: tighten scaled-log2 input	log(x+5) silently rendered as log(x) — now requires plain LOAD input	backend 881/881 (+1)	no silent log shift drop	compound log/exp renderers
2026-04-20	exp2sin-guard	1	Item#10 iter: tighten scaled-exp2/sin inputs	compound-input exp2/sin no longer silently drop inner sub-expressions	backend 881/881 (unchanged; new patterns rejected)	scaled-renderer input validation	per-param type safety
2026-04-20	premul-guard	1	Item#10 iter: pre-reduction MUL guard	sum(x*x)/sum(-x)/max(-x) no longer silently strip pre-reduction MULs	backend 882/882 (+1)	reducer refuses compound int kernels	pre-reduction MUL renderer
2026-04-20	axis-premul	1	Item#10 iter: axis reducer pre-MUL guard	row/col reducers mirror scalar guard; sum(x*x,axis) and max(-x,axis) no longer silently drop pre-reduction MULs	backend 883/883 (+1)	no silent axis-reduce wrong results	fused axis reduce+mul support
2026-04-20	todo-mid	1	iter 24: TODO mid-push refresh	landings 1-23 summarized	docs-only	mid-push snapshot	more renderer fixes
2026-04-20	sweep	1	Iter 25: float correctness sweep	17-op Tensor method sweep vs numpy reference	backend 884/884 (+1)	regression net for future renderer changes	more dtype coverage
2026-04-20	sweep-int	1	Iter 26: int32 correctness sweep	16-op Tensor method sweep vs numpy reference	backend 885/885 (+1)	int regression net	bool correctness fix
2026-04-20	memory-2	1	iter 27: memory refresh mid-push	full checkpoint 2026-04-20; project_status updated; MEMORY index bumped	memory-only	mid-push resume ready	next session picks up cold
2026-04-20	softplus-guard	1	Iter 28: softplus min-const false-match guard	float min-const path no longer silently matches softplus/MAX+MUL+transcendental kernels	backend 886/886 (+1)	no silent softplus-as-min	softplus dedicated renderer
2026-04-20	clip	1	Iter 29: clip/hardtanh renderer	Tensor.clip(lo,hi) and Tensor.hardtanh() lower to FMIN+FMAX per tile	backend 888/888 (+2)	clip/hardtanh end-to-end	softplus still UNSUPPORTED
2026-04-20	leaky	1	Iter 30: leaky_relu renderer	leaky_relu via 3-op FMUL+FMAX microprogram	backend 888/888 (+1)	Tensor.leaky_relu() end-to-end	elu/selu/mish renderers
2026-04-20	clamp1	1	Iter 31: single-bound clamp + relu-zero guard	clamp(min=c)/clamp(max=c) for c!=0 emit FMAX/FMIN; relu pattern now requires CMPLT's CONST to be 0	backend 889/889 (+1)	single-bound clamp works	var/std / softmax
2026-04-20	todo-end-2	1	iter 32: end-of-push-2 TODO refresh	iters 24-31 landings summarized in TODO	docs-only	end-of-push-2 snapshot	var/std + softmax
2026-04-20	vfy-2	1	iter 33: final verification end of push-2	BSV 95 tests green; Python 1031 passed + 1 skipped; 31 iters clean	all green	end of second 40-iter push	cold resume from memory
2026-04-20	colbc-float	1	Iter 34: col-broadcast float remap	ADD/SUB/MUL/etc in col-broadcast renderer now remap to F-variants for float tensors	backend 889/889	float col-broadcast no longer bit-reinterprets	deeper col-broadcast shape bug remains
2026-04-20	rowbc-float	1	Iter 35: row-broadcast float remap	same fix as iter 34 applied to row-broadcast renderer	backend 889/889	float row-broadcast no longer bit-reinterprets	
2026-04-20	memory-3	1	iter 36: memory refresh end-of-push-2	checkpoint 2026-04-20 updated with iters 24-35 landings	memory-only	end of 2nd 40-iter push cold-resume ready	next session picks up cold
2026-04-20	vfy-final	1	iter 37: final verification end-of-push-2	BSV 95 tests + Python 1031 passed + 1 skipped; 36 iters clean second 40-iter push substantially closed	all green	end of second 40-iter push	next session cold-resume
2026-04-20	edd1f7a	1	lean	pipe_refines_abs + multi variant	lake build ok	none (proof add-on)	continue push 3 bool-cast
2026-04-20	f280fd4	1	tinytpu+tests	bool tensor Tensor.sum() correct	sim tests: 2 new + 119 regress pass	none (bugfix)	continue push 3 hardware
2026-04-20	e5fa1fa	1	pe+test	feedPair/passWeight OS primitive	make test-pe pass (+2 OS cycles)	none	iter 41 SystolicArray streaming
2026-04-20	68b902c	1	systolic+test	feedPair streaming + getMatrix drain	make test-array pass (WS + OS 2x2 matmul)	none	iter 42 Controller OS FSM
2026-04-20	b57243c	1	ctrl+test	startOsReal + FSM + full-matrix drain	make test-ctrl-os-real pass (4x4 I@W = W)	none	iter 43 SXU/TASM OS-real opcode
2026-04-21	b92cd7d	1	os cleanup	unified naming: accumulate (23) + OS (25)	ctrl-os+ctrl-accumulate+sxu+tasm pass	none	iter 45 IS dataflow
2026-04-21	13b93cf	1	sramdb	writeActive front-door method	test-wsram-db+asram-db pass	none	iter 46 TensorCore DB wire-in
2026-04-21	b6190c6	1	tc	DB SRAMs as TensorCore default	test-tc+4x4+accel+chip+865 backend tests pass	Item #5 finish	iter 47 preload+swap API E2E test
2026-04-21	7327dfe	1	tc+sxu+test	DB ping-pong dispatch + SXU restart from HALTED	test-tc-db pass + sxu/sxu-psum/tc/4x4/accel clean	none	iter 48 TensorCore DB wiring doc
2026-04-21	8f509b8	1	todo	close Item #5 + #8	none (docs)	Item#5 + #8 done	iter 49 TranscUnit TANH/SIGMOID
2026-04-21	339312e	1	vregfile	Vector-of-Reg unblocks dual-issue writeback	test-vregfile+sxu+865 backend pass; G0010 → G0036	real hw gap closed (dual-issue)	iter 50 more SXU gaps
2026-04-21	2809dd0	1	sxu+tasm	LOAD_MXU_MATRIX_ROW (opcode 26)	test-sxu clean; tasm 86 pass (+2)	none	iter 51 OS end-to-end sim test
2026-04-21	b90ab1d	1	test	OS E2E through runtime sim	892 backend tests pass (+1)	OS fully usable via bundle	iter 52 multi-K OS accumulate
2026-04-21	0df63ed	1	test	OS E2E non-trivial A matmul	2 OS E2E tests pass	staircase non-identity exercise	iter 53 cycle counter
2026-04-21	ed0ed19	1	sxu+perf	READ_CYCLE opcode 27 + counter reg	tasm 88 + 894 backend pass	none	iter 54 cycle-range E2E test
2026-04-21	ab3c958	1	todo	close VRegFile writeback item	none (docs)	Tier 3 item closed	iter 55 SXU_LOOP
2026-04-21	6ac6703	1	sxu+loop	LOOP_BEGIN/END opcodes 28/29 + body-runs test	tasm 90 + 895 backend pass	real hw support for short loops	iter 56 iter-count proof test
2026-04-21	48dcba5	1	test	LOOP iter-count proof via READ_CYCLE delta	896 backend pass	none	iter 57 small cleanup
2026-04-21	042796a	1	sxu	VZERO opcode 30 (single-cycle zero vreg)	tasm 92 + backend clean	none	iter 58 VFILL
2026-04-21	08ba1ff	1	sxu	VFILL (31) + VMOV (32) single-cycle	tasm 96 pass; 3 E2E tests	none	iter 59 combined test
2026-04-21	2f21712	1	test	LOOP accumulator integration test	900 backend pass	none	iter 60 read results panel
2026-04-21	136af66	1	test	dual-issue XLU cycle-span guard	901 backend pass	locks in iter 49 win	iter 61 next
2026-04-21	e7befdd	1	ctrl+sxu	MXU_OS_ACCUMULATE (33) — multi-K-tile OS	tasm 98 + 902 backend pass	real OS scaling past K==rows	iter 62 next
2026-04-21	a85d3ed	1	lean	accumulate_compose theorem	lake build ok	formal OS-accumulate correctness	iter 63 next
2026-04-21	ef029a5	1	sxu	VNEG opcode 34	tasm 100 + backend pass	none	iter 64 next
2026-04-21	82421cf	1	sxu	VABS opcode 35	tasm 102 + backend pass	none	iter 65 run full regression
2026-04-21	59a2574	1	regression	full sweep pass after 35-opcode SXU	BSV 54/54 + Python 1006/1006	none	iter 66 TODO refresh
2026-04-21	87f9ac6	1	todo	push 3 landing summary + deferrals	none (docs)	all Tier 1-2 items closed or deferred	iter 67 next
2026-04-21	554b254	1	test	compose VFILL+LOOP+VNEG+VABS+VMOV	905 backend pass	none	iter 68 docs
2026-04-21	8cd6020	1	doc	architecture.html push-3 opcode refresh	none (docs)	docs in sync	iter 69 next
2026-04-21	b461c3f	1	verify	full verification post-doc refresh	python 1067 + lean lake build ok	none	iter 70 next
2026-04-21	b461c3f	1	memory	checkpoint_2026_04_21 + MEMORY.md bump	none (memory)	resume pointer current	iter 71 next
2026-04-21	6039f71	1	tinytpu	int32 abs renderer uses VABS (5→3 instrs)	905 backend pass	instruction density -40% for int abs	iter 72 next
2026-04-21	52d3ac9	1	tinytpu	softsign: VZERO replaces zero preload	905 backend pass	one less VMEM tile per softsign	iter 73 next
2026-04-21	68cccfd	1	verify	final end-to-end regression	python 1067 + lean build ok	none	iter 74 status memory
2026-04-21	0b57783	1	memory	project_tinytpu_status refresh for push 3	none (memory)	resume pointer current	iter 75 next
2026-04-21	6ce6a0c	1	verify	submodule sync + clean state check	submodule e2439f52 (tinytpu-iterations)	none	iter 76 final TODO
2026-04-21	62051ec	1	todo	note VABS/VZERO renderer adoption	none (docs)	push 3 wrapping	iter 77 final
2026-04-21	0c0cb15	1	push-3-done	final regression: 1007 backend+tasm + 36 SXU opcodes + real OS + DB default + dual-issue unblocked	BSV 54/54 pass	push 3 (iters 38-77) complete	hand off to next session via checkpoint
2026-04-22	3595c3b	1	sxu+loop	nested LOOP via depth-4 stack	907 backend pass (+2 nested)	Item: Nested SXU_LOOP closed	iter 2 VPU dual-issue
2026-04-22	6bd27de	1	vpu	VPU_PACKED_I8_ADD saturating opcode	tasm 103 + backend 908 pass (+1 tasm, +1 backend)	Item: int8 packed ADD	iter 3 PACKED_I8_SUB
2026-04-22	c28bcf3	1	vpu	VPU_PACKED_I8_SUB saturating opcode	tasm 104 + backend 909 pass	Item: int8 packed SUB	iter 4 PACKED_I8_MAX
2026-04-22	7759823	1	vpu	VPU_PACKED_I8_MAX/MIN signed byte-wise	tasm 106 + backend 910 pass	Item: int8 packed MAX/MIN	iter 5 PACKED_I8_NEG/ABS
2026-04-22	db2f203	1	vpu	VPU_PACKED_I8_NEG + RELU	tasm 108 + backend 911 pass	Item: int8 packed NEG/RELU	iter 6 transcunit tanh
2026-04-22	a1ac76e	1	vpu	VPU_PACKED_I8_CMPLT/CMPEQ	tasm 110 + backend 912 pass	Item: int8 CMPLT/CMPEQ	iter 7 PACKED_I8_ABS + MUL_LOW
2026-04-22	9b01dab	1	sxu	LOAD_LOOP_DEPTH opcode	tasm 114 + backend 913 pass	sxu opcodes 37 total	iter 8 XLU rotate
2026-04-22	ff3dc81	1	sxu+xlu	DISPATCH_XLU_ROTATE opcode	tasm 116 + backend 914 pass	sxu opcodes 38 total	iter 9 xlu permute
2026-04-22	0dda23d	1	sxu+psum	PSUM_CLEAR_ALL multi-cycle walker	backend 915 pass	sxu opcodes 39 total	iter 10 pred-not-zero
2026-04-22	d65461b	1	sxu	SET_PRED_NE_ZERO + SKIP_IF_NOT_PRED	backend 916 pass	sxu opcodes 41 total	iter 11 LOOP_BREAK
2026-04-22	16fce52	1	vpu	VPU_PACKED_I8_MUL_LOW	tasm 115 + backend 917 pass	packed_i8 at 7 ops	iter 12 run full regression
2026-04-22	ca19d50	1	vpu	VPU_PACKED_I8_MUL_HIGH (Q-format hi-byte)	tasm 116 + backend 918 pass	packed_i8 at 8 ops	iter 13 vpu sign
2026-04-22	57b75e7	1	vpu	SIGN + PACKED_I8_ABS + PACKED_I8_SIGN unary ops	tasm 119 + backend 920 pass	packed_i8 at 10 ops (ABS/SIGN)	iter 14 lean proof
2026-04-22	539d74b	1	lean	zero_weight_accum_unchanged theorem	lake build ok (4 theorems)	formal inertness of 0-weight	iter 15 next
2026-04-22	15ef22e	1	vpu	VPU_FSIGN float sign opcode	tasm 120 + backend 921 pass	vpu=69 ops	iter 16 xlu permute
2026-04-22	885afb6	1	vpu	ARGMIN + ARGMAX per-row index reductions	tasm 122 + backend 922 pass	vpu=71 ops	iter 17 reductions
2026-04-22	311d4f5	1	vpu	VPU_CLZ + VPU_POPCOUNT	tasm 124 + backend 923 pass	vpu=73 ops	iter 18 byte reverse
2026-04-22	305fa46	1	doc	architecture.html opcode refresh	none (docs)	docs sync to push 4 state	iter 19 tanh
2026-04-22	531dbe2	1	regression	push-4 midpoint full sweep	Python 1107+1skip; BSV sample 15/15	regression baseline clean	iter 20 TODO refresh
2026-04-22	ec381ca	1	todo	push-4 progress summary	none (docs)	Nested LOOP closed; int8 at 10 ops	iter 21 next
2026-04-22	27f5a8b	1	vpu	VPU_CTZ + VPU_BYTE_REVERSE	tasm 126 + backend 924 pass	vpu=75 ops	iter 22 next
2026-04-22	a91d01f	1	vpu	VPU_SAT_ADD_I32 + VPU_SAT_SUB_I32	tasm 128 + backend 925 pass	vpu=77 ops	iter 23 lean sign
2026-04-22	b2ac7a3	1	lean	sign_idempotent + sign_odd	lake build ok (6 theorems)	formal sign semantics	iter 24 more vpu
2026-04-22	dad848f	1	vpu	ABS_DIFF_I32 + PACKED_I8_ABS_DIFF	tasm 130 + backend 927 pass	vpu=79 ops	iter 25 todo refresh
2026-04-22	d4f0fca	1	vpu	VPU_FABS single-cycle float abs	tasm 131 + backend 928 pass	vpu=80 ops	iter 26 softsign renderer adoption
2026-04-22	1ceeda0	1	tinytpu	softsign adopts FABS (drops VZERO+FSUB+FMAX)	softsign test pass	renderer adoption start	iter 27 next
2026-04-22	b98c3e0	1	tinytpu	float-abs adopts FABS (5 instrs -> 3)	58 abs tests pass	renderer adoption 2	iter 28 next
2026-04-22	1f11ec3	1	vpu	VPU_ROTL + VPU_ROTR	tasm 133 + backend 931 pass	vpu=82 ops	iter 29 next
2026-04-22	9d00bb7	1	lean	PE weight invariance theorems	lake build ok (8 theorems)	formal WS weight-stationary invariant	iter 30 next
2026-04-22	11dc825	1	doc	architecture.html VPU=82	none (docs)	docs in sync with push 4	iter 31 todo refresh
2026-04-22	faee5d1	1	todo	push-4 summary update	none (docs)	vpu=82, 5 new lean theorems	iter 32 next
2026-04-22	8bbed4a	1	regression	push-4 end-stage full sweep	Python 1122+1skip (was 1107)	+15 tests since iter 19	iter 33 next
2026-04-22	decba23	1	vpu	VPU_MIN_U32 + VPU_MAX_U32	tasm 135 + backend 933 pass	vpu=84 ops	iter 34 memory refresh
2026-04-22	4ed93cb	1	memory	checkpoint_2026_04_22 + MEMORY.md bump	none (memory)	push-4 checkpoint current	iter 35 project_status
2026-04-22	1b4f03b	1	memory	project_tinytpu_status push-4 refresh	none (memory)	resume pointer current	iter 36 next
2026-04-22	6512019	1	regression	BSV sample sweep (10 targets, 32 passes)	all green	no BSV regressions from push 4 opcode additions	iter 37 next
2026-04-22	f9e906e	1	lean	sign_bounded + sign_times_self_nonneg	lake build ok (10 theorems)	sign ∈ {-1,0,1} bound + |x| lemma	iter 38 next
2026-04-22	a35b881	1	todo	lean theorem count + dual-issue retry plan	none (docs)	final TODO update	iter 39 regression
2026-04-22	b3a9cf7	1	regression	final push-4 regression sweep	Python 1125+1skip	+18 tests since iter 19	iter 40 push-4-done
2026-04-22	0641bd5	1	push-4-done	final: VPU 55→84 (+29), SXU 36→41 (+5), Lean 3→10 (+7), renderer FABS adoption; tasm 135+, Python 1125+1skip	BSV sample 10/10 targets clean	push 4 (iters 1-40) complete	hand off via checkpoint 2026-04-22
2026-04-22	c56ae9e	1	sxu	SXU_DISPATCH_VPU_BG (41) dual-issue path	tasm 135 + sim test_vpu_bg pass	push 5 iter 1 — VPU dual-issue retry w/ dedicated opcode	iter 2 renderer/chain tests
2026-04-23	4884744	1	sxu	VPU_BG refactor to unified dispatch/collect + conservative RAW stall on STORE	sim test_vpu_bg + test_vpu_bg_multi_cycle_log2 + test_dual_issue_xlu pass	push 5 iter 2 — build time regressed 3m->20m+, fixed by unifying rules (single vrf read/write site)	iter 3 renderer adoption of VPU_BG	186.5
2026-04-23	815388b	1	sxu	Extend !vpu_wb_pending RAW stall to all vreg-reader rules + rename to clarify module boundary (vpu_busy -> vpu_wb_pending)	backend 932 pass, sim test_vpu_bg + test_dual_issue_xlu + test_vpu_bg_multi_cycle_log2 pass	push 5 iter 3 — BG is safe under any reader; rename makes SXU pipeline state distinct from VPU busy	iter 4 renderer adoption of VPU_BG	187.0
2026-04-23	622b99e	1	lean	VPU_BG dispatch/collect refinement (3 theorems)	lake build clean (13 theorems); backend 932 pass	push 5 iter 4 — formalize BG dispatch-then-collect == sync; precise-RAW scoreboard deferred (bsc elaboration budget blows on cross-field struct compares)	iter 5 reconsider: renderer adoption vs multi-engine queues	178.4
2026-04-23	42bf6d1	1	docs	TODO.md refresh + checkpoint memory update for push-5 hand-off	no tests (docs/memory only)	push 5 iter 5 — document landings + remaining work + elaboration-budget gotcha for next session	precise RAW scoreboard -> multi-input queue -> renderer adoption	178.4
2026-04-23	bcb0f27	1	docs	architecture.html refresh for push-5 dual-issue: VPU_BG opcode, unified collect, vpu_wb_pending scoreboard	browser render check passes; 14 occurrences of new terms	push 5 iter 6 — docs in sync with push-5 landings	precise RAW scoreboard + multi-queue still deferred	178.4
2026-05-15	f2915e7	1	tests	end-to-end attention block: QKV proj + Q@K^T + relu-attn + host-softmax-attn + 2-head MHA	sim tests/test_e2e_attention.py 7 passed	none (test-only)	bool->int32 MXU activation packing (1<<24 mis-encode); permute view folded by matmul scheduler unless .contiguous()	178.4
2026-05-16	4249682	1	tinytpu	sinh/cosh renderers	backend 934 pass (+2)	none	logsigmoid/softplus/mish/elu still UNSUPPORTED	178.4
2026-05-16	961722a	1	tinytpu	tan renderer	backend 935 pass (+1)	none	elu/softplus/logsigmoid/mish UNSUPPORTED	178.4
2026-05-16	2306446	1	tests	multi-tile sinh/cosh/tan	backend 938 pass (+3)	none	softplus/elu/mish still UNSUPPORTED	178.4
2026-05-16	bea6afe	1	lean	predicate skip/set theorems	lake build clean (17 theorems, was 13)	none	-	178.4
2026-05-16	488894c	1	tinytpu	softplus/logsigmoid renderers	backend 941 pass (+3)	none	elu/mish/hardsigmoid still UNSUPPORTED	178.4
2026-05-16	5b3a865	1	tests	multi-tile logsigmoid	backend 942 pass (+1)	none	-	178.4
2026-05-16	af56f78	1	tinytpu	relu6 renderer	backend 944 pass (+2)	none	hardsigmoid/elu/mish still UNSUPPORTED	178.4
2026-05-16	c05e996	1	tinytpu	hardsigmoid renderer	backend hardsigmoid+adjacent 3 passed	coverage overview adds hardsigmoid	elu/mish still UNSUPPORTED	178.4
2026-05-16	ITER2	1	tinytpu	elu renderer	backend elu+adjacent 3 passed	coverage overview adds elu	mish still UNSUPPORTED	178.4
2026-05-16	ITER3	1	tinytpu	mish renderer	backend mish+adjacent 3 passed	coverage overview adds mish	composite activation multi-tile sweeps remain	178.4
2026-05-16	ITER4	1	tests	multi-tile hardsigmoid coverage	backend hardsigmoid multi-tile pass	none	activation shape sweeps continue	178.4
2026-05-16	ITER5	1	tests	multi-tile elu coverage	backend elu multi-tile pass	none	activation shape sweeps continue	178.4
2026-05-16	ITER6	1	tests	multi-tile mish coverage	backend mish multi-tile pass	none	activation 2D sweeps continue	178.4
2026-05-16	ITER7	1	tests	2D hardsigmoid coverage	backend hardsigmoid 2D pass	none	activation 2D sweeps continue	178.4
2026-05-16	ITER8	1	tests	2D elu coverage	backend elu 2D pass	none	activation 2D sweeps continue	178.4
2026-05-16	ITER9	1	tests	2D mish coverage	backend mish 2D pass	none	activation tail sweeps continue	178.4
2026-05-16	ITER10	1	tests	tail-tile hardsigmoid coverage	backend hardsigmoid tail pass	none	activation tail sweeps continue	178.4
2026-05-16	ITER11	1	tests	tail-tile elu coverage	backend elu tail pass	none	activation tail sweeps continue	178.4
2026-05-16	ITER12	1	tests	tail-tile mish coverage	backend mish tail pass	none	activation lowering dump checks continue	178.4
2026-05-16	ITER13	1	tests	hardsigmoid lowering dump coverage	backend hardsigmoid dump pass	none	activation lowering dump checks continue	178.4
2026-05-16	ITER14	1	tests	elu lowering dump coverage	backend elu dump pass	none	activation lowering dump checks continue	178.4
2026-05-16	ITER15	1	tests	mish lowering dump coverage	backend mish dump pass	none	activation sign-region checks continue	178.4
2026-05-16	ITER16	1	tests	hardsigmoid saturation coverage	backend hardsigmoid saturation pass	none	activation sign-region checks continue	178.4
2026-05-16	ITER17	1	tests	elu negative-branch coverage	backend elu negative branch pass	none	activation sign-region checks continue	178.4
2026-05-16	ITER18	1	tests	elu positive-branch coverage	backend elu positive branch pass	none	activation sign-region checks continue	178.4
2026-05-16	ITER19	1	tests	mish negative-region coverage	backend mish negative region pass	none	final activation sweep remains	178.4
2026-05-16	ITER20	1	tests	mish positive-region coverage	backend mish positive region pass	none	full backend sweep	178.4
2026-05-20	ITER21	1	instsel	int32/bool elementwise via UOp-walking InstSel pass	backend 774 pass / 124 fail (base 749/148): 0 regressions, 24 fixed	added InstSel migration section	walker: float, cast, transcendental coverage	178.4
2026-05-20	ITER22	1	instsel	float elementwise via UOp walker (VECTORIZE/GEP see-through)	backend 784 pass / 114 fail: 0 regressions, 10 fixed	none	delete _render_elementwise after structured broadcast	178.4
2026-05-20	ITER23	1	instsel	float CMPNE/CMPEQ + bool-cast in walker; _render_elementwise deleted (315 lines)	backend 811 pass / 87 fail: 0 regressions, 27 fixed	marked _render_elementwise removal done	transcendental/activation recognizers	178.4
2026-05-20	ITER24	1	instsel	EXP2/LOG2/SIN transcendentals routed through walker	backend 809 pass / 89 fail: 2 hardware-exposure regressions (broken EXP2/LOG2 unmasked)	noted unmasked transcendental hardware bug	delete transcendental+activation recognizers	178.4
2026-05-20	ITER25	1	instsel	RECIPROCAL (FRECIP) + SQRT via InstSel graph-rewrite	backend 810 pass / 88 fail: 0 regressions, 1 fixed	none	delete transcendental+activation recognizers	178.4
2026-05-20	ITER26	1	instsel	deleted 34 transcendental/activation/elementwise recognizers + 3 orphan helpers (3062 lines)	backend 810 pass / 88 fail: 0 regressions	marked recognizer deletion done	divmod/trunc, regalloc spill	178.4
2026-05-20	ITER27	1	instsel	linear-scan VREG allocation with reuse in the walker	backend 810 pass / 88 fail: 0 regressions	none	divmod/trunc, delete last 2 non-structural recognizers	178.4
2026-05-20	ITER28	1	instsel	trunc + divmod via walker; deleted last 2 non-structural recognizers	backend 810 pass / 88 fail: 0 regressions; 4 divmod tests corrected to floor semantics	marked divmod/trunc done; slice complete	structural recognizers (separate slice)	178.4
2026-05-20	ITER29	1	instsel	0 (structural)	backend 810 pass / 88 fail: 0 regressions	InstSel structural slice step 1 (package split)	structural recognizers (classifier, reduction, broadcast, GEMM)	178.4
2026-05-20	ITER30	1	instsel	0 (structural)	backend 810 pass / 88 fail: 0 regressions	InstSel structural slice step 2 (classifier)	structural recognizers (reduction, broadcast, GEMM)	178.4
2026-05-20	ITER31	1	instsel	0 (structural)	backend 810 pass / 88 fail: 0 regressions	InstSel structural slice step 3 (reduction lowerer)	structural recognizers (broadcast, GEMM)	178.4
2026-05-20	ITER32	1	instsel	0 (structural)	backend 810 pass / 88 fail: 0 regressions	InstSel structural slice step 4 (broadcast lowerer)	structural recognizers (GEMM)	178.4
2026-05-20	ITER33	1	instsel	0 (structural)	backend 810 pass / 88 fail: 0 regressions	InstSel structural slice step 5 (trivial kernels: cast/copy/const-fill)	structural recognizers (pad, transpose, rowbc-copy, GEMM)	178.4
2026-05-20	ITER34	1	instsel	0 (structural)	backend 810 pass / 88 fail: 0 regressions	InstSel structural slice step 6 (GEMM relocate + encoder consolidation)	structural recognizers (pad, transpose, rowbc-copy)	178.4
2026-05-20	ITER35	1	instsel	0 (structural)	backend 810 pass / 88 fail: 0 regressions	InstSel structural slice step 7-8 (movement lowerer, Branch B)	none (zero _render_*_sxu_program recognizers remain)	178.4
2026-05-21	ITER36	1	instsel	0 (structural)	backend 810 pass / 88 fail: 0 regressions	InstSel structural slice step 9 (final cleanup, slice complete)	none (zero _render_* recognizers; ops_tinytpu.py 1260 lines from 6984)	178.4
2026-05-24	ccc117d	1	epilogues	+e2e tests for 5 CODA epilogue classes; fix col-vector (M,1) broadcast classifier	19/19 epilogue + 976/976 backend pass	closed "col-vector (M,1) broadcast mis-lowers as MUL"; opened "inline relu->reduce inside add chain mis-lowers"	chained relu+reduce inline-fusion bug	178.4
2026-05-24	1301b45	1	epilogues	tighten GEMM-fallback heuristic (require MUL(LOAD,LOAD)); add inline-reduce regression test	20/20 epilogue + 1036/1036 (epi+e2e+backend) pass	closed "inline reduce-in-add silently produces garbage" (now raises NotImplementedError); fused (M,1)+reduce(axis=1) lowerer still open	fused reduce+add lowering for inline form	178.4