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hathachhathach
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make TUP_DCD_EDPT_ISO_ALLOC i.e dcd_edpt_iso_alloc()/dcd_edpt_iso_activate() as default driver implementation. dcd_edpt_close() is deprecated and will be removed from all driver in the future.
1 parent 6b28a44 commit cbd4aef

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16 files changed

+1850
-482
lines changed

16 files changed

+1850
-482
lines changed

‎examples/device/video_capture/skip.txt‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
mcu:CH32V103
22
mcu:CH32V20X
3-
mcu:MCXA15
43
mcu:MSP430x5xx
54
mcu:NUC121
65
mcu:SAMD11

‎examples/device/video_capture_2ch/skip.txt‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@ mcu:CH32V103
66
mcu:CH32V20X
77
mcu:CH32V307
88
mcu:STM32L0
9-
mcu:MCXA15
109
family:espressif
1110
board:curiosity_nano
1211
board:kuiic

‎hw/bsp/family_support.cmake‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -262,6 +262,7 @@ function(family_configure_common TARGET RTOS)
262262
family_add_board(${BOARD_TARGET})
263263
set_target_properties(${BOARD_TARGET} PROPERTIES
264264
ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib
265+
COMPILE_OPTIONS -w
265266
SKIP_LINTING ON # need cmake 4.2
266267
)
267268
endif ()

‎hw/bsp/mcx/boards/frdm_mcxa153/board.cmake‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,11 @@ function(update_board TARGET)
1414
BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
1515
CFG_EXAMPLE_VIDEO_READONLY
1616
)
17-
target_sources(${TARGET} PUBLIC
18-
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
19-
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
17+
target_sources(${TARGET} PRIVATE
18+
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/clock_config.c
19+
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board/pin_mux.c
20+
)
21+
target_include_directories(${TARGET} PUBLIC
22+
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/board
2023
)
2124
endfunction()

‎hw/bsp/mcx/boards/frdm_mcxa153/clock_config.c‎ renamed to ‎hw/bsp/mcx/boards/frdm_mcxa153/board/clock_config.c‎

Lines changed: 111 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright 2023 NXP
2+
* Copyright 2025 NXP
33
* All rights reserved.
44
*
55
* SPDX-License-Identifier: BSD-3-Clause
@@ -25,11 +25,12 @@
2525
/* clang-format off */
2626
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
2727
!!GlobalInfo
28-
product: Clocks v12.0
28+
product: Clocks v18.0
2929
processor: MCXA153
3030
package_id: MCXA153VLH
3131
mcu_data: ksdk2_0
32-
processor_version: 0.13.0
32+
processor_version: 25.09.10
33+
board: FRDM-MCXA153
3334
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
3435
/* clang-format on */
3536

@@ -45,13 +46,14 @@ processor_version: 0.13.0
4546
* Variables
4647
******************************************************************************/
4748
/* System clock frequency. */
48-
//extern uint32_t SystemCoreClock;
49+
extern uint32_t SystemCoreClock;
4950

5051
/*******************************************************************************
5152
************************ BOARD_InitBootClocks function ************************
5253
******************************************************************************/
5354
void BOARD_InitBootClocks(void)
5455
{
56+
BOARD_BootClockFRO96M();
5557
}
5658

5759
/*******************************************************************************
@@ -68,9 +70,13 @@ name: BOARD_BootClockFRO12M
6870
- {id: MAIN_clock.outFreq, value: 12 MHz}
6971
- {id: Slow_clock.outFreq, value: 3 MHz}
7072
- {id: System_clock.outFreq, value: 12 MHz}
73+
- {id: TRACE_clock.outFreq, value: 12 MHz}
74+
- {id: UTICK_clock.outFreq, value: 1 MHz}
75+
- {id: WWDT0_clock.outFreq, value: 1 MHz}
7176
settings:
7277
- {id: SCGMode, value: SIRC}
73-
- {id: FRO_HF_PERIPHERALS_EN_CFG, value: Disabled}
78+
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
79+
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
7480
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
7581
- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
7682
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
@@ -106,6 +112,9 @@ void BOARD_BootClockFRO12M(void)
106112
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
107113
}
108114

115+
116+
/*!< Set up system dividers */
117+
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
109118
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
110119

111120
CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO12M */
@@ -125,9 +134,11 @@ void BOARD_BootClockFRO12M(void)
125134
}
126135

127136
/*!< Set up clock selectors - Attach clocks to the peripheries */
137+
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
128138

129139
/*!< Set up dividers */
130-
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
140+
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
141+
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
131142

132143
/* Set SystemCoreClock variable */
133144
SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
@@ -149,9 +160,14 @@ name: BOARD_BootClockFRO24M
149160
- {id: MAIN_clock.outFreq, value: 48 MHz}
150161
- {id: Slow_clock.outFreq, value: 6 MHz}
151162
- {id: System_clock.outFreq, value: 24 MHz}
163+
- {id: TRACE_clock.outFreq, value: 24 MHz}
164+
- {id: UTICK_clock.outFreq, value: 1 MHz}
165+
- {id: WWDT0_clock.outFreq, value: 1 MHz}
152166
settings:
167+
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
168+
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
153169
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
154-
- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
170+
- {id: SYSCON.AHBCLKDIV.scale, value: '2'}
155171
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
156172
/* clang-format on */
157173

@@ -184,6 +200,11 @@ void BOARD_BootClockFRO24M(void)
184200
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
185201
}
186202

203+
204+
/*!< Set up system dividers */
205+
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */
206+
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
207+
187208
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
188209

189210
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
@@ -205,10 +226,21 @@ void BOARD_BootClockFRO24M(void)
205226
}
206227

207228
/*!< Set up clock selectors - Attach clocks to the peripheries */
229+
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
230+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
231+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
232+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
233+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
234+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
235+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
236+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
237+
CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
238+
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
239+
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
208240

209241
/*!< Set up dividers */
210-
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 2U); /* !< Set AHBCLKDIV divider to value 2 */
211-
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
242+
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
243+
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
212244

213245
/* Set SystemCoreClock variable */
214246
SystemCoreClock = BOARD_BOOTCLOCKFRO24M_CORE_CLOCK;
@@ -230,7 +262,12 @@ name: BOARD_BootClockFRO48M
230262
- {id: MAIN_clock.outFreq, value: 48 MHz}
231263
- {id: Slow_clock.outFreq, value: 12 MHz}
232264
- {id: System_clock.outFreq, value: 48 MHz}
265+
- {id: TRACE_clock.outFreq, value: 48 MHz}
266+
- {id: UTICK_clock.outFreq, value: 1 MHz}
267+
- {id: WWDT0_clock.outFreq, value: 1 MHz}
233268
settings:
269+
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
270+
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
234271
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
235272
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
236273
/* clang-format on */
@@ -264,6 +301,11 @@ void BOARD_BootClockFRO48M(void)
264301
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
265302
}
266303

304+
305+
/*!< Set up system dividers */
306+
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
307+
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
308+
267309
CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
268310

269311
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
@@ -285,10 +327,21 @@ void BOARD_BootClockFRO48M(void)
285327
}
286328

287329
/*!< Set up clock selectors - Attach clocks to the peripheries */
330+
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
331+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
332+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
333+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
334+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
335+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
336+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
337+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
338+
CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
339+
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
340+
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
288341

289342
/*!< Set up dividers */
290-
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
291-
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
343+
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
344+
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
292345

293346
/* Set SystemCoreClock variable */
294347
SystemCoreClock = BOARD_BOOTCLOCKFRO48M_CORE_CLOCK;
@@ -310,8 +363,13 @@ name: BOARD_BootClockFRO64M
310363
- {id: MAIN_clock.outFreq, value: 64 MHz}
311364
- {id: Slow_clock.outFreq, value: 16 MHz}
312365
- {id: System_clock.outFreq, value: 64 MHz}
366+
- {id: TRACE_clock.outFreq, value: 64 MHz}
367+
- {id: UTICK_clock.outFreq, value: 1 MHz}
368+
- {id: WWDT0_clock.outFreq, value: 1 MHz}
313369
settings:
314370
- {id: VDD_CORE, value: voltage_1v1}
371+
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
372+
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
315373
- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
316374
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
317375
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
@@ -349,6 +407,11 @@ void BOARD_BootClockFRO64M(void)
349407
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
350408
}
351409

410+
411+
/*!< Set up system dividers */
412+
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
413+
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
414+
352415
CLOCK_SetupFROHFClocking(64000000U); /*!< Enable FRO HF(64MHz) output */
353416

354417
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
@@ -370,10 +433,21 @@ void BOARD_BootClockFRO64M(void)
370433
}
371434

372435
/*!< Set up clock selectors - Attach clocks to the peripheries */
436+
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
437+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
438+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
439+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
440+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
441+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
442+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
443+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
444+
CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
445+
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
446+
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
373447

374448
/*!< Set up dividers */
375-
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
376-
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
449+
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
450+
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
377451

378452
/* Set SystemCoreClock variable */
379453
SystemCoreClock = BOARD_BOOTCLOCKFRO64M_CORE_CLOCK;
@@ -385,6 +459,7 @@ void BOARD_BootClockFRO64M(void)
385459
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
386460
!!Configuration
387461
name: BOARD_BootClockFRO96M
462+
called_from_default_init: true
388463
outputs:
389464
- {id: CLK_1M_clock.outFreq, value: 1 MHz}
390465
- {id: CLK_48M_clock.outFreq, value: 48 MHz}
@@ -395,12 +470,14 @@ name: BOARD_BootClockFRO96M
395470
- {id: MAIN_clock.outFreq, value: 96 MHz}
396471
- {id: Slow_clock.outFreq, value: 24 MHz}
397472
- {id: System_clock.outFreq, value: 96 MHz}
473+
- {id: TRACE_clock.outFreq, value: 96 MHz}
474+
- {id: UTICK_clock.outFreq, value: 1 MHz}
475+
- {id: WWDT0_clock.outFreq, value: 1 MHz}
398476
settings:
399477
- {id: VDD_CORE, value: voltage_1v1}
400-
- {id: CLKOUTDIV_HALT, value: Enable}
401-
- {id: MRCC.FROHFDIV.scale, value: '1', locked: true}
478+
- {id: MRCC.FREQMEREFCLKSEL.sel, value: MRCC.aoi0_out0}
479+
- {id: MRCC.FREQMETARGETCLKSEL.sel, value: MRCC.aoi0_out0}
402480
- {id: MRCC.OSTIMERCLKSEL.sel, value: VBAT.CLK16K_1}
403-
- {id: SYSCON.AHBCLKDIV.scale, value: '1', locked: true}
404481
sources:
405482
- {id: SCG.FIRC.outFreq, value: 96 MHz}
406483
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
@@ -435,6 +512,11 @@ void BOARD_BootClockFRO96M(void)
435512
(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
436513
}
437514

515+
516+
/*!< Set up system dividers */
517+
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
518+
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
519+
438520
CLOCK_SetupFROHFClocking(96000000U); /*!< Enable FRO HF(96MHz) output */
439521

440522
CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
@@ -456,10 +538,21 @@ void BOARD_BootClockFRO96M(void)
456538
}
457539

458540
/*!< Set up clock selectors - Attach clocks to the peripheries */
541+
CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
542+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0); /* !< Switch LPSPI0 to FRO_HF_DIV */
543+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1); /* !< Switch LPSPI1 to FRO_HF_DIV */
544+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPI2C0); /* !< Switch LPI2C0 to FRO_HF_DIV */
545+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART0); /* !< Switch LPUART0 to FRO_HF_DIV */
546+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART1); /* !< Switch LPUART1 to FRO_HF_DIV */
547+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPUART2); /* !< Switch LPUART2 to FRO_HF_DIV */
548+
CLOCK_AttachClk(kFRO_HF_DIV_to_LPTMR0); /* !< Switch LPTMR0 to FRO_HF_DIV */
549+
CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK); /* !< Switch I3C0FCLK to FRO_HF_DIV */
550+
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP0); /* !< Switch CMP0 to FRO_HF_DIV */
551+
CLOCK_AttachClk(kFRO_HF_DIV_to_CMP1); /* !< Switch CMP1 to FRO_HF_DIV */
459552

460553
/*!< Set up dividers */
461-
CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set AHBCLKDIV divider to value 1 */
462-
CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
554+
CLOCK_SetClockDiv(kCLOCK_DivTRACE, 1U); /* !< Set TRACECLKDIV divider to value 1 */
555+
CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U); /* !< Set WWDT0CLKDIV divider to value 1 */
463556

464557
/* Set SystemCoreClock variable */
465558
SystemCoreClock = BOARD_BOOTCLOCKFRO96M_CORE_CLOCK;

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