|
39 | 39 | #define DWC2_DEBUG 2 |
40 | 40 |
|
41 | 41 | #include "device/dcd.h" |
| 42 | +#include "device/usbd.h" |
42 | 43 | #include "device/usbd_pvt.h" |
43 | 44 | #include "dwc2_common.h" |
44 | 45 |
|
@@ -76,6 +77,10 @@ CFG_TUD_MEM_SECTION static struct { |
76 | 77 | TUD_EPBUF_DEF(setup_packet, 8); |
77 | 78 | } _dcd_usbbuf; |
78 | 79 |
|
| 80 | +static tud_configure_dwc2_t _tud_cfg = { |
| 81 | + .bm_double_buffered = 0 |
| 82 | +}; |
| 83 | + |
79 | 84 | TU_ATTR_ALWAYS_INLINE static inline uint8_t dwc2_ep_count(const dwc2_regs_t* dwc2) { |
80 | 85 | #if TU_CHECK_MCU(OPT_MCU_GD32VF103) |
81 | 86 | (void) dwc2; |
@@ -212,8 +217,8 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { |
212 | 217 | _dcd_data.allocated_epin_count++; |
213 | 218 | } |
214 | 219 |
|
215 | | - // If The TXFELVL is configured as half empty, the fifo must be twice the max_size. |
216 | | - if ((dwc2->gahbcfg & GAHBCFG_TX_FIFO_EPMTY_LVL) == 0) { |
| 220 | + // Enable double buffering if configured |
| 221 | + if (((_tud_cfg.bm_double_buffered & (1 << epnum)) != 0) && (epnum > 0)) { |
217 | 222 | fifo_size *= 2; |
218 | 223 | } |
219 | 224 |
|
@@ -446,6 +451,16 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin |
446 | 451 | //-------------------------------------------------------------------- |
447 | 452 | // Controller API |
448 | 453 | //-------------------------------------------------------------------- |
| 454 | +// optional dcd configuration, called by tud_configure() |
| 455 | +bool dcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { |
| 456 | + (void) rhport; |
| 457 | + TU_VERIFY(cfg_id == TUD_CFGID_DWC2 && cfg_param != NULL); |
| 458 | + |
| 459 | + const tud_configure_param_t* const cfg = (const tud_configure_param_t*) cfg_param; |
| 460 | + _tud_cfg = cfg->dwc2; |
| 461 | + return true; |
| 462 | +} |
| 463 | + |
449 | 464 | bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { |
450 | 465 | (void) rh_init; |
451 | 466 | dwc2_regs_t* dwc2 = DWC2_REG(rhport); |
@@ -494,7 +509,6 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { |
494 | 509 |
|
495 | 510 | // TX FIFO empty level for interrupt is complete empty |
496 | 511 | uint32_t gahbcfg = dwc2->gahbcfg; |
497 | | - gahbcfg |= GAHBCFG_TX_FIFO_EPMTY_LVL; |
498 | 512 | gahbcfg |= GAHBCFG_GINT; // Enable global interrupt |
499 | 513 | dwc2->gahbcfg = gahbcfg; |
500 | 514 |
|
|
0 commit comments