[audio_device] Allow user-defined memory attributes for DMA buffers

[yamamo2shun1]

Environment

• MCU: STM32H7S3 (Cortex-M7, DCache enabled)
• Mode: DWC2 DMA mode (CFG_TUD_DWC2_DMA_ENABLE=1)
• Class: USB Audio Class (4ch, 24bit, 48/96kHz)
• Symptom: Random HardFault after 5min ~ 2hours of audio streaming

Problem

When using DWC2 in DMA mode (CFG_TUD_DWC2_DMA_ENABLE=1) on Cortex-M7 with
DCache enabled, the audio class buffers cause cache coherency issues.

Root Cause

In audio_device.c#L76-L85, IN_SW_BUF_MEM_ATTR and OUT_SW_BUF_MEM_ATTR
use TU_ATTR_ALIGNED(4) when CFG_TUD_EDPT_DEDICATED_HWFIFO=0.

However, per tusb_option.h#L311-L319, CFG_TUD_EDPT_DEDICATED_HWFIFO=1
is only set for Slave mode, not DMA mode.

This means DMA mode uses software buffers (ep_in_sw_buf, ep_out_sw_buf)
that are accessed by DMA but placed in cacheable memory.

Proposed Fix

Add #ifndef guards to allow users to override buffer memory attributes via tusb_config.h:

Before (audio_device.c#L76-L85):

#if !CFG_TUD_EDPT_DEDICATED_HWFIFO
  #define IN_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
#else
  #define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
#endif
#if !CFG_TUD_EDPT_DEDICATED_HWFIFO
  #define OUT_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
#else
  #define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
#endif

After

#ifndef IN_SW_BUF_MEM_ATTR
  #if !CFG_TUD_EDPT_DEDICATED_HWFIFO
    #define IN_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
  #else
    #define IN_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
  #endif
#endif
#ifndef OUT_SW_BUF_MEM_ATTR
  #if !CFG_TUD_EDPT_DEDICATED_HWFIFO
    #define OUT_SW_BUF_MEM_ATTR TU_ATTR_ALIGNED(4)
  #else
    #define OUT_SW_BUF_MEM_ATTR CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN
  #endif
#endif

User configuration (tusb_config.h):

// Place audio buffers in noncacheable region for DWC2 DMA mode
#define IN_SW_BUF_MEM_ATTR  __attribute__((section("noncacheable_buffer"), aligned(32)))
#define OUT_SW_BUF_MEM_ATTR __attribute__((section("noncacheable_buffer"), aligned(32)))

[HiFiPhile]

This means DMA mode uses software buffers (ep_in_sw_buf, ep_out_sw_buf)
that are accessed by DMA but placed in cacheable memory.

It's not how it works. When DMA is enabled, DWC2 doesn't support transfer directly into/from fifo, a linear buffer is used, that's why CFG_TUD_EDPT_DEDICATED_HWFIFO=0.

USB->lin_buf_out->ep_out_sw_buf

lin_buf_out has already section and alignment defined:

tu_static CFG_TUD_MEM_SECTION struct {
  #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX > 0
  TUD_EPBUF_DEF(buf_1, CFG_TUD_AUDIO_FUNC_1_EP_OUT_SZ_MAX);
  #endif
  #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX > 0
  TUD_EPBUF_DEF(buf_2, CFG_TUD_AUDIO_FUNC_2_EP_OUT_SZ_MAX);
  #endif
  #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX > 0
  TUD_EPBUF_DEF(buf_3, CFG_TUD_AUDIO_FUNC_3_EP_OUT_SZ_MAX);
  #endif
} lin_buf_out;

Your hardfault is caused something else.