Missing definitions as per inadvertent IR match masks - cont.

[hazzaclark]

Going off of my recent testing with the Sonic 1 ROM file, I am noticing that whenever it tries to BNE and BEQ (which now works mind you), it is causing an inadvertent bug where it is reading the Opcode sort of Big Endian right to left and making it so that it reads the EA of the PREVIOUS Opcode which would otherwise need a manual PC advance or something of that association in order to properly read the instruction properly - at least that is my assumption

-------------------------------------------------------------
[PC -> 0240]  [IR -> 1A1D]  ILLEGAL INSTRUCTION FOUND AT PC -> (0x0240) -> CURRENT OPCODE: (0x1A1D)
[ERROR] -> MEMORY REGION IS UNMAPPED [SIZE: 32]: NO BUFFER FOUND FOR ADDRESS: 0x00FFFE00
[ERROR] -> MEMORY ENCOUNTERED A BAD READ [SIZE: 32]: ADDRESS: 0x00FFFE00
[JUMP TRACE] TO PC: 0x03E6 FROM PC: 0x0000
CYCLES: 0, TOTAL ELAPSED: 152
-------------------------------------------------------------

It's reading the imm data of one instruction and the mode of another

The only possible solutions I can think of are to make a new def for the missing instruction or to cheese something else - either way, more work for me and then some

This issues board will remain here for the foreseeable future as I work my way through each of these inconsistencies - no point in making multiple issues for what is essentially the SAME issue

[hazzaclark]

Going off of my recent testing with the Sonic 1 ROM file, I am noticing that whenever it tries to BNE and BEQ (which now works mind you), it is causing an inadvertent bug where it is reading the Opcode sort of Big Endian right to left and making it so that it reads the EA of the PREVIOUS Opcode which would otherwise need a manual PC advance or something of that association in order to properly read the instruction properly - at least that is my assumption

-------------------------------------------------------------
[PC -> 0240]  [IR -> 1A1D]  ILLEGAL INSTRUCTION FOUND AT PC -> (0x0240) -> CURRENT OPCODE: (0x1A1D)
[ERROR] -> MEMORY REGION IS UNMAPPED [SIZE: 32]: NO BUFFER FOUND FOR ADDRESS: 0x00FFFE00
[ERROR] -> MEMORY ENCOUNTERED A BAD READ [SIZE: 32]: ADDRESS: 0x00FFFE00
[JUMP TRACE] TO PC: 0x03E6 FROM PC: 0x0000
CYCLES: 0, TOTAL ELAPSED: 152
-------------------------------------------------------------

`It's reading the imm data of one instruction and the mode of another`

The only possible solutions I can think of are to make a new def for the missing instruction or to cheese something else - either way, more work for me and then some

This issues board will remain here for the foreseeable future as I work my way through each of these inconsistencies - no point in making multiple issues for what is essentially the SAME issue

As mentioned in the description of this commit, I was actually looking at the wrong def this whole time.
a9bca93

Matter of fact, there was an IR mask of 0x1A1D which extracts bits 12 - 9 and 3 - 0 from the MOVE instruction to discern the EA and the POST_INC values - this def was higher up in the trace as seen by PC 0x240

Moral of the story for this time is to properly pay attention to the PC location and read the disasm from there

If there is anything to blame this for, I blame ImHex and it's searching system for defaulting the search to that PC value SO large and out of the way for now

[hazzaclark]

Updated implementation for additional Opcodes that were causing overarching memory leaks
604e659

The reproduced error

-------------------------------------------------------------
[PC -> 0242]  [IR -> 3885]  [ERROR] -> MEMORY OUT OF BOUNDS [SIZE: 16]: ATTEMPT TO WRITE TO AN ADDRESS RANGE BEYOND THE ADDRESSABLE SPACE: 0x120000C0
[ERROR] -> MEMORY VIOLATES A RESERVED RANGE [SIZE: 16]: ATTEMPT TO WRITE TO RESERVED ADDRESS RANGE: 0x120000C0
[ERROR] -> MEMORY ENCOUNTERED A BAD WRITE [SIZE: 16]: VALUE: 0x294, ADDRESS: 0x120000C0
CYCLES: 10, TOTAL ELAPSED: 160
-------------------------------------------------------------

The fix:

unsigned EA = M68K_BIT_SHIFT_N_24(M68K_ADDRESS_HIGH);

Just made sure to properly mask accordingly
First time I have had to use N_24 for EA calculations but, the reason why this works is because it masks the highest nibble of 16 bits for the EA displacement - so it works

[hazzaclark]

Recent change made to account for proper masking increment for POST_INC for MOVE

2fa3bc3