What: UART baud rate configuration hardcodes the fractional divider (div_fra) to 0, losing precision when the baud rate divides unevenly.
Why: The C SDK calculates div_fra = (remainder * 64) / (16 * baud) to refine the clock divisor when integer division leaves a remainder. Setting div_fra to 0 degrades baud rate accuracy (e.g., 115200 baud on 160MHz UART clock).
Acceptance criteria:
- Compute remainder from the baud rate calculation
- Set div_fra to
(remainder * 64) / (16 * baud) as per C SDK hal_spi_v151.c / hal_uart.c
- Verify baud rate precision matches SDK within ±2%
Evidence: crates/hisi-riscv-hal/src/uart.rs:108; review 2026-05 page 84 'UART 硬编码 16x 过采样与零分数分频器'
Filed from the hisi-riscv-rs open-task audit (ROADMAP · review ledger · code TODOs · architecture docs).
What: UART baud rate configuration hardcodes the fractional divider (div_fra) to 0, losing precision when the baud rate divides unevenly.
Why: The C SDK calculates
div_fra = (remainder * 64) / (16 * baud)to refine the clock divisor when integer division leaves a remainder. Setting div_fra to 0 degrades baud rate accuracy (e.g., 115200 baud on 160MHz UART clock).Acceptance criteria:
(remainder * 64) / (16 * baud)as per C SDKhal_spi_v151.c/hal_uart.cEvidence: crates/hisi-riscv-hal/src/uart.rs:108; review 2026-05 page 84 'UART 硬编码 16x 过采样与零分数分频器'
Filed from the hisi-riscv-rs open-task audit (ROADMAP · review ledger · code TODOs · architecture docs).