HAL: extend the async (embedded-hal-async) driver layer to chip-bs21

[sanchuanhehe]

The embassy time-driver was made chip-neutral and now runs on BS2X (hisi-riscv-hal 0.3.1: embassy::ALARM_IRQ, embassy decoupled from async). But the broader async feature — the interrupt + waker driven embedded-hal-async / embedded-io-async driver layer — is still chip-ws63-only:

• asynch (the wfi block_on + IrqSignal) — #[cfg(all(feature = "chip-ws63", feature = "async"))]
• timer::AsyncDelay (DelayNs), gpio digital::Wait, uart Read/Write, spi SpiBus, i2c I2c

These reference the WS63-only asynch module + WS63 interrupt names (DMA_INT / GPIO_INT0.. / TIMER_INT0..) in their per-driver on_interrupt, so they don't compile under chip-bs21.

Task: make the async driver layer build + work on BS2X (chip-bs21):

• Generalize the per-driver on_interrupt / IRQ references through soc::chip (BS2X IRQ numbers: GPIO_0=34, UART_0=39, TIMER_0=53, DMA=…) instead of WS63 literals.
• Un-gate asynch + the per-driver async impls from chip-ws63 to just async where the register access is already chip-neutral (TCXO/TIMER/GPIO/UART/SPI/I2C blocks are register-identical across the family, as verified for the embassy driver).
• Validate on qemu-system-riscv32 -M bs21/bs21e/bs22/bs20 (e.g. an async_delay / async_bus analogue under examples/bs21).

Today BS2X users get embassy (the common async path); this issue closes the gap for the lower-level embedded-hal-async drivers. Surfaced during the 2026-06-12 embassy-on-BS2X bring-up.

[sanchuanhehe]

Status note (2026-06-14): the premise is partly stale. The per-driver async impls are no longer gated on chip-ws63 — spi.rs:339, i2c.rs:375, uart.rs:303, timer.rs:359, gpio.rs:599, dma.rs:639 now gate asynch_impl on just feature = "async". So the gating-removal part has landed.

What remains for chip-bs21: the async impls still use WS63-literal IRQ names (timer.rs:372 Interrupt::TIMER_INT0..2, gpio.rs:613 GPIO_INT0..2, dma.rs:653 DMA_INT) that don't exist on bs21's Interrupt enum (bs21 re-exports TIMER_0/GPIO_0/… from bs2x_pac), and the asynch module (block_on/IrqSignal) is still chip-ws63-gated (lib.rs:54). So it won't build under chip-bs21 yet — the remaining work is generalizing the IRQ names through soc::chip + un-gating asynch + bs21 validation.