Cannot make generic RISC-V U-encoding rule

[aperezdc]

I am trying to write a rule set to encode 32-bit RISC-V instructions, and I cannot make the following to work:

#bits 8
#subruledef register
{
	x{num: u5} => num
}
#ruledef rv32i
{
	// Instruction U-encoding
	insn/U {imm: i20}, {rd: register}, {opcode: u7} => le(imm @ rd @ opcode)
}

insn/U 0, x1, 0b0110111

This error is produced:

error: no match for instruction found
 --> asm:14:1:
 12 | } 
 13 |  
 14 | insn/U 0, x1, 0b0110111
    | ^^^^^^^^^^^^^^^^^^^^^^^ 

I tried combinations of few different things, which did not work:

• Renaming insn/U to insn.u or insnu (just in case the slash in the name was a problem).
• Removing the #subruledef and passing 1'5 directly instead of x1 as the rd parameter.
• Passing the imm as 0x00000 (5 nibbles = 20 bits) or 0'20.

What I am doing wrong?

[hlorenzi]

Oh! It's your C-style // comment -- you should instead use assembly-style ; ones.

[aperezdc]

Right, using the wrong comment style was indeed the problem here, thanks!

[aperezdc]

I have a related issue. If I extend the example above with a lui rule which reuses insn/U with an asm {} block, I also get an error:

#bits 8
#subruledef register {
	x{num: u5} => num
}
#ruledef rv32_encoding {
	insn/U {imm: i20}, {rd: register}, {opcode: u7} => le(imm @ rd @ opcode)
}
insn/U 0, x1, 0b0110111

#ruledef rv32i {
	lui {rd: register}, {imm: i20} => asm { insn/U imm, rd, 0b0110111 }
}
lui x1, 0

This is the error:

error: failed to resolve instruction
 --> asm:13:1:
 11 |   lui {rd: register}, {imm: i20} => asm { insn/U imm, rd, 0b0110111 } 
 12 | } 
 13 | lui x1, 0
    | ^^^^^^^^^ 
 === error: no match for instruction found
 --> asm:11:42:
  9 |  
 10 | #ruledef rv32i { 
 11 |   lui {rd: register}, {imm: i20} => asm { insn/U imm, rd, 0b0110111 } 
    |                                           ^^^^^^^^^^^^^^^^^^^^^^^^^    
 12 | } 
 13 | lui x1, 0

Again, I tried moving things around without much luck. I wonder if I am hitting some bug now (but probably I am doing something wrong again) 🤔

[aperezdc]

Interestingly, a similar example which defines the ecall instruction reusing an insn/I definition works well:

#bits 8
#subruledef register {
	x{num: u5} => num
}
#ruledef rv32_encoding {
	insn/I {imm: i12}, {rs1: register}, {funct3: u3}, {rd: register}, {opcode: u7} =>
		le(imm @ rs1 @ funct3 @ rd @ opcode)
}

#ruledef rv32i {
	ecall   => asm { insn/I 0, x0, 0, x0, 0b1110011 }
}

ecall  ; This assembles fine!

Maybe there is some issue related to passing arguments from one rule to the one inside the asm statement?

[aperezdc]

Okay, I figured out reading this comment that I have to use {} around subruledef parameters when passing them around, like this:

#ruledef rv32i {
      lui {rd: register}, {imm: i20} => asm { insn/U imm, {rd}, 0b0110111 }
                                 ; Note the brackets here ^^^^
}
lui x0, 0  ; This now works

Yay! 🙌🏼

[hlorenzi]

Yes, that's it!