System Verilog Error #1395
Unanswered
christopherleeCE
asked this question in
Q&A
Replies: 0 comments
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
-
I am trying to get system verilog working with iverilog, and I am running into this issue. I have the compiler flag set to "-g2012", but digital/iverilog seems to be trying to grab "logic" as the port names instead of "A" and "Z", and I am getting 3 more separate errors that I cant seem to understand (there is no line 16 or 17)
Does anyone know what I am doing wrong here?
Beta Was this translation helpful? Give feedback.
All reactions