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Same issue with the EEPROM. In my circuit there are ~460 elements, so I experienced that curios write at 90% of times… :/ So thank you for this solution! This works for me. |
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It's possible to set a RAM as "program memory" and have it reloaded with fresh data at every start of the simulation. But I'm experiencing a spurious write to it at the start in like 10% of the cases. Considering stuff starts up in random states it's just to be expected, and a real design would have a write protect circuity during power-on & reset for this.
But here it's not so simple as just gating the ~WE or ~CS with the Reset component. Regardless how many "ingenious" combinations I try I still get spurious writes. It seems that a write pulse slips though during startup anyways. The RAM2 example here is one variant of them all.
Not until I pulled out all the stops and entered "big brain" mode I figured out a variant that worked - the one in example RAM1.
It's a bit annoying to have to resort to craziness like that to keep the data safe. I'm not sure that having the Digital application keep all memories (RAM/EEPROM) in write-disable mode during the initial shakedown of the nets so they stabilise and the reset component signals it's done. It wouldn't work like that in a real circuit. But on the other hand a simple gate would probably work there.
I haven't tried if the same issue occurs for the EEPROM component, but I assume it does considering they are basically the same from the users perspective when set for reload at startup.
Maybe there's a easier way of making the RAM playing nice during system startup that I've just not realized yet?
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