How to solve the error: "the logic seems to oscillate"

[nek70]

I made a JK flip-flop using NAND logic gates (attached the file).
JK_flip_flop.zip
I have an error when J=1 and K=1. The error is "the logic seems to oscillate". If I use the JK flip-flop contained in the Digital library, the problem doesn't occur. Why? How I can solve the problem? Many thanks. Regards

[mengstr]

Your JK FlipFlop dosen't have a real clock (only does it's thing on an edge) input , it's more an enable (does it thing as long as it's active) input. If you set it constantly high the outputs will change directly when you change the J and K inputs. So when you set both J and K high for it to toggle it will just keep on toggling as long as the (fake) clock input is high.

The pre-made JK component is made so the clock is a real edge triggered input, and will only update the outputs at at a falling (or rising) edge. So you only get one update per "pulse" of the clock. Not a continuous stream of updates as long as the "clock" is held high.

To fix it you have to hook up two JK-flip flops in an after each other like below. Read more about it here: https://www.electronics-tutorials.ws/sequential/seq_2.html

[nek70]

You are absolutely right, I apologize for my ignorance.
Many thanks
Regards