Wanted to share my RISC-V build in Digital

[jgalak]

I used Logisim in college, almost 30 years ago, where we had to use it to build a PowerPC CPU. Recently discovered Digital, and was inspired by a combination of nostalgia and curiosity to build something similar. I decided to do a RISC-V processor. Images below, the design is heavily based on the Harris & Harris book.

This is a single-cycle processor with separate program and data memory, and it implements every non-privileged instruction in the rv32i set - everything except FENCE, FENCE.TSO, PAUSE, ECALL, and EBREAK. It does not currently support any privileged architecture such as CSRs.

I'm going to keep working on this, but the current state is a major milestone, so I thought I'd share. Things I'm considering for future development: unifying the memory (tricky with a single-cycle processor, I'll need to use dual-ported RAM, I think), pipelining the processor, and/or adding some parts of the privileged architecture (traps, some CSRs, etc.)

Anyway, here is the main circuit:
(most of the display circuitry I "borrowed" from the YouTuber rj32)

[mengstr]

Nice.... Any plans to maybe far in the future build this out of real parts?

[jgalak]

Probably not. I'm currently building a Ben Eater - style 8bit processor on breadboard with my kid, but a 32 bit cpu like this would be ridiculously time consuming.

I might try to burn it to an fpga some day, but that's not a high-priority item for me.