feat: 250409 블로그 숫자수정

Author: hyeokls

_posts/2025-04-09-[HDL Bits] 11.Circuits - Seq Logic - Counters.md

@@ -38,7 +38,7 @@ Circuits 는 다음과 같은 목차로 구성되어 있다.
 
 ---
 
-## 3.4.2.1. Four-bit binary counter
+## 3.4.3.1. Four-bit binary counter
 ### Module Declaration
 난이도: ★☆☆☆☆
 ```verilog
@@ -80,7 +80,7 @@ endmodule
 
 ```
 
-## 3.4.2.2. Decade counter (Count10)
+## 3.4.3.2. Decade counter (Count10)
 ### Module Declaration
 난이도:  ★☆☆☆☆
 ```verilog
@@ -122,7 +122,7 @@ endmodule
 ```
 
 
-## 3.4.2.3. Decade counter again (Count1to10)
+## 3.4.3.3. Decade counter again (Count1to10)
 ### Module Declaration
 난이도:  ★☆☆☆☆
 ```verilog
@@ -163,7 +163,7 @@ module top_module (
 endmodule
 ```
 
-## 3.4.2.4. Slow decade counter Countslow
+## 3.4.3.4. Slow decade counter Countslow (Countslow) 
 ### Module Declaration
 난이도:  ★★☆☆☆
 ```verilog
@@ -208,7 +208,7 @@ endmodule
 ```
 
 
-## 3.4.2.5. Counter 1-12 (Exmas/ece241 2014 q7a)
+## 3.4.3.5. Counter 1-12 (Exmas/ece241 2014 q7a)
 ### Module Declaration
 난이도:  ★★★★☆
 ```verilog
@@ -308,7 +308,7 @@ endmodule
 
 <br>
 
-## 3.4.2.6. Counter 1000 (Exams/ece241 2014 q7b)
+## 3.4.3.6. Counter 1000 (Exams/ece241 2014 q7b)
 ### Module Declaration
 난이도:  ★★★☆☆
 ```verilog
@@ -369,7 +369,7 @@ endmodule
 
 ```
 
-## 3.4.2.7. 4-digit decimal counter (Countbcd)
+## 3.4.3.7. 4-digit decimal counter (Countbcd)
 ### Module Declaration
 난이도: ★★★☆☆
 ```verilog
@@ -431,7 +431,7 @@ module cnt_bcd(
 endmodule
 ```
 
-## 3.4.2.8. 12-hour clock (Count clock)
+## 3.4.3.8. 12-hour clock (Count clock)
 ### Module Declaration
 난이도: ★★★★☆
 ```verilog