diff --git a/IBPSA/Controls/OBC/CDL/Logical/Latch.mo b/IBPSA/Controls/OBC/CDL/Logical/Latch.mo
index 4b4d8e8a29..b89bc36aa3 100644
--- a/IBPSA/Controls/OBC/CDL/Logical/Latch.mo
+++ b/IBPSA/Controls/OBC/CDL/Logical/Latch.mo
@@ -10,10 +10,11 @@ block Latch
IBPSA.Controls.OBC.CDL.Interfaces.BooleanOutput y
"Output with latched signal"
annotation (Placement(transformation(extent={{100,-20},{140,20}})));
+
+initial equation
+ y = not clr and u;
equation
- when initial() then
- y=not clr and u;
- elsewhen {clr, u} then
+ when {clr, u} then
y=not clr and u;
end when;
annotation (
@@ -118,6 +119,11 @@ At initial time, if clr = false, then the output will be
revisions="