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Drop RDNA4 clock offset workaround, rename clock table types to GCN/RDNA (#13)
* Rename tables types to GCN and RDNA * chore: drop RDNA4 workaround * drop old offset range parsing
1 parent cf579bb commit 4d836d6

26 files changed

Lines changed: 42 additions & 140 deletions

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‎Cargo.toml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
[package]
22
name = "amdgpu-sysfs"
3-
version = "0.18.2"
3+
version = "0.19.0"
44
authors = ["Ilya Zlobintsev <ilya.zl@protonmail.com>"]
55
edition = "2021"
66
license = "GPL-3.0"

‎src/gpu_handle/mod.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -228,7 +228,7 @@ impl GpuHandle {
228228
}
229229
}
230230
}
231-
if let Some(s) = line.split(':').last() {
231+
if let Some(s) = line.split(':').next_back() {
232232
let parse_result = if let Some(suffix) = kind.value_suffix() {
233233
let raw_value = s.trim().to_lowercase();
234234
let value = raw_value.strip_suffix(suffix).ok_or_else(|| {

src/gpu_handle/overdrive/vega10.rs renamed to src/gpu_handle/overdrive/gcn.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -273,7 +273,7 @@ enum Section {
273273
mod tests {
274274
use super::{ClocksLevel, Table};
275275
use crate::{
276-
gpu_handle::overdrive::{arr_commands, vega10::OdRange, ClocksTable, Range},
276+
gpu_handle::overdrive::{arr_commands, gcn::OdRange, ClocksTable, Range},
277277
include_table,
278278
};
279279
use pretty_assertions::assert_eq;

‎src/gpu_handle/overdrive/mod.rs‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
//! GPU overdrive (overclocking)
22
//!
33
//! <https://kernel.org/doc/html/latest/gpu/amdgpu/thermal.html#pp-od-clk-voltage>
4-
pub mod vega10;
5-
pub mod vega20;
4+
pub mod gcn;
5+
pub mod rdna;
66

77
use crate::{
88
error::{Error, ErrorKind},
@@ -157,8 +157,8 @@ fn check_clockspeed_in_range(range: Option<Range>, clockspeed: i32) -> Result<()
157157

158158
/// Representation of clocks and voltage table (`pp_od_clk_voltage`).
159159
///
160-
/// NOTE: despite the names, the tables here are not exclusive to Vega10 and 20!
161-
/// Vega10 covers everything Vega10 and older (including Polaris), while Vega20 includes all newer gpus as well (like Navi)
160+
/// NOTE: the variant names are not 100% accurate, they roughly represent what generations of GPUs use each format.
161+
/// For example, Radeon VII (Vega20) uses the new "RDNA" format.
162162
#[derive(Debug, Clone)]
163163
#[cfg_attr(feature = "serde", derive(Serialize, Deserialize))]
164164
#[cfg_attr(
@@ -168,9 +168,9 @@ fn check_clockspeed_in_range(range: Option<Range>, clockspeed: i32) -> Result<()
168168
#[enum_dispatch(ClocksTable)]
169169
pub enum ClocksTableGen {
170170
/// Vega10 (and older) format
171-
Vega10(vega10::Table),
171+
Gcn(gcn::Table),
172172
/// Vega20 (and newer) format
173-
Vega20(vega20::Table),
173+
Rdna(rdna::Table),
174174
}
175175

176176
impl FromStr for ClocksTableGen {
@@ -185,9 +185,9 @@ impl FromStr for ClocksTableGen {
185185
sclk_line.contains("mhz") && !sclk_line.contains("mv")
186186
})
187187
} {
188-
vega20::Table::from_str(s).map(Self::Vega20)
188+
rdna::Table::from_str(s).map(Self::Rdna)
189189
} else {
190-
vega10::Table::from_str(s).map(Self::Vega10)
190+
gcn::Table::from_str(s).map(Self::Gcn)
191191
}
192192
}
193193
}

src/gpu_handle/overdrive/vega20.rs renamed to src/gpu_handle/overdrive/rdna.rs

Lines changed: 11 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -20,9 +20,6 @@ pub struct Table {
2020
pub current_sclk_range: Range,
2121
/// The current core clock offset (RDNA4+)
2222
pub sclk_offset: Option<i32>,
23-
/// Workaround for the original buggy SCLK offset range format on RDNA4
24-
/// TODO: drop this when the new format is widely used (should be kernel 6.15+)
25-
pub rdna4_sclk_offset_workaround: bool,
2623
/// The current memory clock range. Empty on iGPUs.
2724
pub current_mclk_range: Range,
2825
/// The current voltage curve. May be empty if the GPU does not support it.
@@ -42,7 +39,7 @@ impl ClocksTable for Table {
4239
writer: &mut W,
4340
previous_table: &ClocksTableGen,
4441
) -> Result<()> {
45-
let ClocksTableGen::Vega20(previous_table) = previous_table else {
42+
let ClocksTableGen::Rdna(previous_table) = previous_table else {
4643
return Err(Error::not_allowed(
4744
"Mismatched clocks table format".to_owned(),
4845
));
@@ -81,17 +78,10 @@ impl ClocksTable for Table {
8178
]);
8279

8380
if let Some(sclk_offset) = self.sclk_offset {
84-
if self.rdna4_sclk_offset_workaround {
85-
let line = format!("s 1 {sclk_offset}\n");
86-
writer
87-
.write_all(line.as_bytes())
88-
.context("Could not write sclk offset")?;
89-
} else {
90-
let line = format!("s {sclk_offset}\n");
91-
writer
92-
.write_all(line.as_bytes())
93-
.context("Could not write sclk offset")?;
94-
}
81+
let line = format!("s {sclk_offset}\n");
82+
writer
83+
.write_all(line.as_bytes())
84+
.context("Could not write sclk offset")?;
9585
}
9686

9787
for (maybe_clockspeed, symbol, index) in clocks_commands {
@@ -242,7 +232,6 @@ impl FromStr for Table {
242232
let mut current_section = None;
243233

244234
let mut current_sclk_range = None;
245-
let mut current_sclk_offset_range = None;
246235
let mut current_mclk_range = None;
247236
let mut allowed_sclk_range = None;
248237
let mut allowed_sclk_offset_range = None;
@@ -306,20 +295,12 @@ impl FromStr for Table {
306295
}
307296
Some(Section::Sclk) => parse_min_max_line(line, i, &mut current_sclk_range)?,
308297
Some(Section::SclkOffset) => {
309-
if line
310-
.split_ascii_whitespace()
311-
.next()
312-
.is_some_and(|start| start == "0:" || start == "1:")
313-
{
314-
parse_min_max_line(line, i, &mut current_sclk_offset_range)?
315-
} else {
316-
let line = line.to_ascii_lowercase();
317-
let raw_value = line.trim_end_matches("mhz");
318-
let value = raw_value
319-
.parse()
320-
.context("Could not parse sclk offset value")?;
321-
sclk_offset = Some(value);
322-
}
298+
let line = line.to_ascii_lowercase();
299+
let raw_value = line.trim_end_matches("mhz");
300+
let value = raw_value
301+
.parse()
302+
.context("Could not parse sclk offset value")?;
303+
sclk_offset = Some(value);
323304
}
324305
Some(Section::Mclk) => parse_min_max_line(line, i, &mut current_mclk_range)?,
325306
Some(Section::VddcCurve) => {
@@ -350,13 +331,9 @@ impl FromStr for Table {
350331
voltage_offset: voltage_offset_range,
351332
};
352333

353-
let sclk_offset =
354-
sclk_offset.or_else(|| current_sclk_offset_range.and_then(|range| range.max));
355-
356334
Ok(Self {
357335
current_sclk_range: current_sclk_range.unwrap_or_default(),
358336
sclk_offset,
359-
rdna4_sclk_offset_workaround: current_sclk_offset_range.is_some(),
360337
current_mclk_range: current_mclk_range.unwrap_or_default(),
361338
vddc_curve,
362339
od_range,
@@ -510,7 +487,6 @@ mod tests {
510487
const TABLE_7900XT: &str = include_table!("rx7900xt");
511488
const TABLE_7800XT: &str = include_table!("rx7800xt");
512489
const TABLE_9070XT: &str = include_table!("rx9070xt");
513-
const TABLE_9070XT_NEW: &str = include_test_data!("rx9070xt/pp_od_clk_voltage_new");
514490
const TABLE_VANGOGH: &str = include_table!("vangogh");
515491

516492
#[test]
@@ -640,7 +616,6 @@ mod tests {
640616
current_sclk_range: Range::empty(),
641617
current_mclk_range: Range::full(500, 1000),
642618
sclk_offset: None,
643-
rdna4_sclk_offset_workaround: false,
644619
vddc_curve: vec![ClocksLevel::new(300, 600), ClocksLevel::new(1000, 1000)],
645620
voltage_offset: None,
646621
od_range: OdRange {
@@ -794,12 +769,6 @@ mod tests {
794769
assert_yaml_snapshot!(table);
795770
}
796771

797-
#[test]
798-
fn parse_9070xt_new_full() {
799-
let table = Table::from_str(TABLE_9070XT_NEW).unwrap();
800-
assert_yaml_snapshot!(table);
801-
}
802-
803772
#[test]
804773
fn set_clock_offset_9070xt() {
805774
let mut table = Table::from_str(TABLE_9070XT).unwrap();
@@ -809,15 +778,6 @@ mod tests {
809778
assert_yaml_snapshot!(table.get_commands(&table.clone().into()).unwrap());
810779
}
811780

812-
#[test]
813-
fn set_clock_offset_9070xt_new() {
814-
let mut table = Table::from_str(TABLE_9070XT_NEW).unwrap();
815-
table.clear();
816-
table.sclk_offset = Some(200);
817-
table.voltage_offset = Some(-50);
818-
assert_yaml_snapshot!(table.get_commands(&table.clone().into()).unwrap());
819-
}
820-
821781
#[test]
822782
fn set_7800xt_voltage() {
823783
let mut table = Table::from_str(TABLE_7800XT).unwrap();

src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__vega20__tests__parse_6700xt_full.snap renamed to src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_6700xt_full.snap

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,11 @@
11
---
2-
source: src/gpu_handle/overdrive/vega20.rs
2+
source: src/gpu_handle/overdrive/rdna.rs
33
expression: table
44
---
55
current_sclk_range:
66
min: 500
77
max: 2725
88
sclk_offset: ~
9-
rdna4_sclk_offset_workaround: false
109
current_mclk_range:
1110
min: 97
1211
max: 1000

src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__vega20__tests__parse_6800_full.snap renamed to src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_6800_full.snap

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,11 @@
11
---
2-
source: src/gpu_handle/overdrive/vega20.rs
2+
source: src/gpu_handle/overdrive/rdna.rs
33
expression: table
44
---
55
current_sclk_range:
66
min: 500
77
max: 2314
88
sclk_offset: ~
9-
rdna4_sclk_offset_workaround: false
109
current_mclk_range:
1110
min: 97
1211
max: 1000

src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__vega20__tests__parse_6900xt_full.snap renamed to src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_6900xt_full.snap

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,11 @@
11
---
2-
source: src/gpu_handle/overdrive/vega20.rs
2+
source: src/gpu_handle/overdrive/rdna.rs
33
expression: table
44
---
55
current_sclk_range:
66
min: 500
77
max: 2499
88
sclk_offset: ~
9-
rdna4_sclk_offset_workaround: false
109
current_mclk_range:
1110
min: 97
1211
max: 1000

src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__vega20__tests__parse_7800xt_full.snap renamed to src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_7800xt_full.snap

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,11 @@
11
---
2-
source: src/gpu_handle/overdrive/vega20.rs
2+
source: src/gpu_handle/overdrive/rdna.rs
33
expression: table
44
---
55
current_sclk_range:
66
min: 500
77
max: 2660
88
sclk_offset: ~
9-
rdna4_sclk_offset_workaround: false
109
current_mclk_range:
1110
min: 97
1211
max: 1219

src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__vega20__tests__parse_7900xt_full.snap renamed to src/gpu_handle/overdrive/snapshots/amdgpu_sysfs__gpu_handle__overdrive__rdna__tests__parse_7900xt_full.snap

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,11 @@
11
---
2-
source: src/gpu_handle/overdrive/vega20.rs
2+
source: src/gpu_handle/overdrive/rdna.rs
33
expression: table
44
---
55
current_sclk_range:
66
min: 500
77
max: 2735
88
sclk_offset: ~
9-
rdna4_sclk_offset_workaround: false
109
current_mclk_range:
1110
min: 97
1211
max: 1250

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