Is it possible to use the SPI testpoints for JTAG?

[snoop911]

I understand the Ice40 doesn't have a native JTAG, but since a soft-jtag is often instantiated for Lattice Reveal software, I imagine it could be done via LiteX? Perhaps something like:

python3 -m litex_boards.targets.fomu
--board=fomu
--cpu-type=vexriscv
--cpu-variant=standard+debug
--uart-name=crossover
--with-jtagbone
--csr-csv=csr.csv
--build

I've tried but haven't had any luck getting SpinalHDL OpenOCD (0.11.0+dev-04036-ga0220ad30) to recognize the VexRiscV:
dtmcontrol is 0 or JTAG scan chain interrogation failed: all ones.

./src/openocd -c "adapter driver ftdi"
-c "ftdi vid_pid 0x0403 0x6010"
-c "ftdi channel 0"
-c "adapter speed 1000"
-c "transport select jtag"
-c 'jtag newtap lx cpu -irlen 4'
-c 'target create lx.cpu0 vexriscv -endian little -chain-position lx.cpu -dbgbase 0xF00F0000'
-c 'vexriscv cpuConfigFile cpu0.yaml'
-c 'init'
-c 'reset halt'

[xobs]

You certainly could repurpose the JTAG pins that way, but doing so requires additional hardware in the form of:

1. A test jig to hit the pins
2. A hardware debugger to speak JTAG

neither of which are very common in beginner circles. Additionally, if your openocd is looking for "dmcontrol" then that's looking for a standard risc-v debug spec implementation, which isn't present on Fomu. Perhaps a newer version of the vexriscv cpu would have it, yes, but that would require more work.

[snoop911]

Yes, that's the goal. Thru the normal USB/SPI interface I want to program a bitstream design that instantiates a JTAG controller on the 4 user I/O pins.

I tacked wires on the I/Os and connected it to an OpenOcd supported jtag chip (FTDI F2232H).

I've checked the connection between the Fomu and the JTAG adapter, and everything is going where it should yet SpinalHDL OpenOCD does not see the VexRiscV.

Error: JTAG scan chain interrogation failed: all ones
Info : JTAG tap: riscv.tap tap/device found: 0x41111043 (mfg: 0x021 (Lattice Semi.), part: 0x1111, v
er: 0x4)
Error: dtmcontrol is 0. Check JTAG connectivity/board power.
Warn : target riscv.cpu examination failed
Error: Trying to use configured scan chain anyway...
Error: lx.cpu: IR capture error; saw 0x0f not 0x01
Error: ERROR: Error while reading from socket: No error
Error: Can't communicate with the CPU
Warn : target lx.cpu0 examination failed
Warn : There are no enabled taps. AUTO PROBING MIGHT NOT WORK!! 
Warn : Bypassing JTAG setup events due to errors
Error: !!!
TARGET: lx.cpu0 - Not halted

I know by default the fomu uses the vexriscv minimal variant, but is there any reason standard+debug can't work? Should I try instantiating a different Cpu.. NEORV32? I'm not too familiar with LiteX or openocd so I'm sure the issue is between the keyboard and the chair... but I've hit a wall trying to figure it out what!

[xobs]

The failure of JTAG to get even an IDCODE does indicate that it's not configured.

You'll have to tristate all of your JTAG pins when the ICE40 boots, since all four wires are needed for SPI communication. If you drive TDI then the SPI signal won't function properly.

You could come up with a simple blinky demo that runs from ROM and see if it will still run in your configuration with the JTAG harness hooked up. That will prove that the ICE40 is still able to load a bitstream.

Actually, thinking on it further, you won't really be able to reuse those pins as JTAG as they're needed for actual SPI communication -- as soon as you toggle CS then flash will start driving CIPO.

You might have better luck repurposing the four touch pads, which should give you just enough wires to do full JTAG.